1*f005ef32Sjsg /* 2*f005ef32Sjsg * Copyright 2023 Advanced Micro Devices, Inc. 3*f005ef32Sjsg * 4*f005ef32Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*f005ef32Sjsg * copy of this software and associated documentation files (the "Software"), 6*f005ef32Sjsg * to deal in the Software without restriction, including without limitation 7*f005ef32Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*f005ef32Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9*f005ef32Sjsg * Software is furnished to do so, subject to the following conditions: 10*f005ef32Sjsg * 11*f005ef32Sjsg * The above copyright notice and this permission notice shall be included in 12*f005ef32Sjsg * all copies or substantial portions of the Software. 13*f005ef32Sjsg * 14*f005ef32Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*f005ef32Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*f005ef32Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*f005ef32Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*f005ef32Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*f005ef32Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*f005ef32Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21*f005ef32Sjsg * 22*f005ef32Sjsg * Authors: AMD 23*f005ef32Sjsg * 24*f005ef32Sjsg */ 25*f005ef32Sjsg 26*f005ef32Sjsg #ifndef _DMUB_REPLAY_H_ 27*f005ef32Sjsg #define _DMUB_REPLAY_H_ 28*f005ef32Sjsg 29*f005ef32Sjsg #include "dc_types.h" 30*f005ef32Sjsg #include "dmub_cmd.h" 31*f005ef32Sjsg struct dc_link; 32*f005ef32Sjsg struct dmub_replay_funcs; 33*f005ef32Sjsg 34*f005ef32Sjsg struct dmub_replay { 35*f005ef32Sjsg struct dc_context *ctx; 36*f005ef32Sjsg const struct dmub_replay_funcs *funcs; 37*f005ef32Sjsg }; 38*f005ef32Sjsg 39*f005ef32Sjsg struct dmub_replay_funcs { 40*f005ef32Sjsg void (*replay_get_state)(struct dmub_replay *dmub, enum replay_state *state, 41*f005ef32Sjsg uint8_t panel_inst); 42*f005ef32Sjsg void (*replay_enable)(struct dmub_replay *dmub, bool enable, bool wait, 43*f005ef32Sjsg uint8_t panel_inst); 44*f005ef32Sjsg bool (*replay_copy_settings)(struct dmub_replay *dmub, struct dc_link *link, 45*f005ef32Sjsg struct replay_context *replay_context, uint8_t panel_inst); 46*f005ef32Sjsg void (*replay_set_power_opt)(struct dmub_replay *dmub, unsigned int power_opt, 47*f005ef32Sjsg uint8_t panel_inst); 48*f005ef32Sjsg void (*replay_set_coasting_vtotal)(struct dmub_replay *dmub, uint16_t coasting_vtotal, 49*f005ef32Sjsg uint8_t panel_inst); 50*f005ef32Sjsg void (*replay_residency)(struct dmub_replay *dmub, 51*f005ef32Sjsg uint8_t panel_inst, uint32_t *residency, const bool is_start, const bool is_alpm); 52*f005ef32Sjsg }; 53*f005ef32Sjsg 54*f005ef32Sjsg struct dmub_replay *dmub_replay_create(struct dc_context *ctx); 55*f005ef32Sjsg void dmub_replay_destroy(struct dmub_replay **dmub); 56*f005ef32Sjsg 57*f005ef32Sjsg 58*f005ef32Sjsg #endif /* _DMUB_REPLAY_H_ */ 59