1*c349dbc7Sjsg /* 2*c349dbc7Sjsg * Copyright 2018 Advanced Micro Devices, Inc. 3*c349dbc7Sjsg * 4*c349dbc7Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*c349dbc7Sjsg * copy of this software and associated documentation files (the "Software"), 6*c349dbc7Sjsg * to deal in the Software without restriction, including without limitation 7*c349dbc7Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*c349dbc7Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9*c349dbc7Sjsg * Software is furnished to do so, subject to the following conditions: 10*c349dbc7Sjsg * 11*c349dbc7Sjsg * The above copyright notice and this permission notice shall be included in 12*c349dbc7Sjsg * all copies or substantial portions of the Software. 13*c349dbc7Sjsg * 14*c349dbc7Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*c349dbc7Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*c349dbc7Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*c349dbc7Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*c349dbc7Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*c349dbc7Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*c349dbc7Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21*c349dbc7Sjsg * 22*c349dbc7Sjsg * Authors: AMD 23*c349dbc7Sjsg * 24*c349dbc7Sjsg */ 25*c349dbc7Sjsg 26*c349dbc7Sjsg #ifndef DAL_DC_DCN20_DCN20_VMID_H_ 27*c349dbc7Sjsg #define DAL_DC_DCN20_DCN20_VMID_H_ 28*c349dbc7Sjsg 29*c349dbc7Sjsg #include "vmid.h" 30*c349dbc7Sjsg 31*c349dbc7Sjsg #define DCN20_VMID_REG_LIST(id)\ 32*c349dbc7Sjsg SRI(CNTL, DCN_VM_CONTEXT, id),\ 33*c349dbc7Sjsg SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\ 34*c349dbc7Sjsg SRI(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id),\ 35*c349dbc7Sjsg SRI(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id),\ 36*c349dbc7Sjsg SRI(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id),\ 37*c349dbc7Sjsg SRI(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id),\ 38*c349dbc7Sjsg SRI(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id) 39*c349dbc7Sjsg 40*c349dbc7Sjsg #define DCN20_VMID_MASK_SH_LIST(mask_sh)\ 41*c349dbc7Sjsg SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\ 42*c349dbc7Sjsg SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\ 43*c349dbc7Sjsg SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 44*c349dbc7Sjsg SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 45*c349dbc7Sjsg SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 46*c349dbc7Sjsg SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 47*c349dbc7Sjsg SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 48*c349dbc7Sjsg SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh) 49*c349dbc7Sjsg 50*c349dbc7Sjsg #define DCN20_VMID_REG_FIELD_LIST(type)\ 51*c349dbc7Sjsg type VM_CONTEXT0_PAGE_TABLE_DEPTH;\ 52*c349dbc7Sjsg type VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE;\ 53*c349dbc7Sjsg type VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32;\ 54*c349dbc7Sjsg type VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32;\ 55*c349dbc7Sjsg type VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4;\ 56*c349dbc7Sjsg type VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32;\ 57*c349dbc7Sjsg type VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4;\ 58*c349dbc7Sjsg type VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32 59*c349dbc7Sjsg 60*c349dbc7Sjsg struct dcn20_vmid_shift { 61*c349dbc7Sjsg DCN20_VMID_REG_FIELD_LIST(uint8_t); 62*c349dbc7Sjsg }; 63*c349dbc7Sjsg 64*c349dbc7Sjsg struct dcn20_vmid_mask { 65*c349dbc7Sjsg DCN20_VMID_REG_FIELD_LIST(uint32_t); 66*c349dbc7Sjsg }; 67*c349dbc7Sjsg 68*c349dbc7Sjsg struct dcn20_vmid { 69*c349dbc7Sjsg struct dc_context *ctx; 70*c349dbc7Sjsg const struct dcn_vmid_registers *regs; 71*c349dbc7Sjsg const struct dcn20_vmid_shift *shifts; 72*c349dbc7Sjsg const struct dcn20_vmid_mask *masks; 73*c349dbc7Sjsg }; 74*c349dbc7Sjsg 75*c349dbc7Sjsg void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config); 76*c349dbc7Sjsg 77*c349dbc7Sjsg #endif /* DAL_DC_DCN20_DCN20_VMID_H_ */ 78