1*1bb76ff1Sjsg /* 2*1bb76ff1Sjsg * Copyright 2012-15 Advanced Micro Devices, Inc. 3*1bb76ff1Sjsg * 4*1bb76ff1Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*1bb76ff1Sjsg * copy of this software and associated documentation files (the "Software"), 6*1bb76ff1Sjsg * to deal in the Software without restriction, including without limitation 7*1bb76ff1Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*1bb76ff1Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9*1bb76ff1Sjsg * Software is furnished to do so, subject to the following conditions: 10*1bb76ff1Sjsg * 11*1bb76ff1Sjsg * The above copyright notice and this permission notice shall be included in 12*1bb76ff1Sjsg * all copies or substantial portions of the Software. 13*1bb76ff1Sjsg * 14*1bb76ff1Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*1bb76ff1Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*1bb76ff1Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*1bb76ff1Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*1bb76ff1Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*1bb76ff1Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*1bb76ff1Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21*1bb76ff1Sjsg * 22*1bb76ff1Sjsg * Authors: AMD 23*1bb76ff1Sjsg * 24*1bb76ff1Sjsg */ 25*1bb76ff1Sjsg 26*1bb76ff1Sjsg #ifndef __DC_OPTC_DCN201_H__ 27*1bb76ff1Sjsg #define __DC_OPTC_DCN201_H__ 28*1bb76ff1Sjsg 29*1bb76ff1Sjsg #include "dcn20/dcn20_optc.h" 30*1bb76ff1Sjsg 31*1bb76ff1Sjsg #define TG_COMMON_REG_LIST_DCN201(inst) \ 32*1bb76ff1Sjsg TG_COMMON_REG_LIST_DCN(inst),\ 33*1bb76ff1Sjsg SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\ 34*1bb76ff1Sjsg SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ 35*1bb76ff1Sjsg SRI(OTG_GSL_WINDOW_X, OTG, inst),\ 36*1bb76ff1Sjsg SRI(OTG_GSL_WINDOW_Y, OTG, inst),\ 37*1bb76ff1Sjsg SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\ 38*1bb76ff1Sjsg SRI(OTG_DSC_START_POSITION, OTG, inst),\ 39*1bb76ff1Sjsg SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\ 40*1bb76ff1Sjsg SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\ 41*1bb76ff1Sjsg SRI(OPTC_WIDTH_CONTROL, ODM, inst),\ 42*1bb76ff1Sjsg SR(DWB_SOURCE_SELECT) 43*1bb76ff1Sjsg 44*1bb76ff1Sjsg #define TG_COMMON_MASK_SH_LIST_DCN201(mask_sh)\ 45*1bb76ff1Sjsg TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ 46*1bb76ff1Sjsg SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\ 47*1bb76ff1Sjsg SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\ 48*1bb76ff1Sjsg SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\ 49*1bb76ff1Sjsg SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ 50*1bb76ff1Sjsg SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ 51*1bb76ff1Sjsg SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ 52*1bb76ff1Sjsg SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ 53*1bb76ff1Sjsg SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\ 54*1bb76ff1Sjsg SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\ 55*1bb76ff1Sjsg SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ 56*1bb76ff1Sjsg SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ 57*1bb76ff1Sjsg SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ 58*1bb76ff1Sjsg SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \ 59*1bb76ff1Sjsg SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \ 60*1bb76ff1Sjsg SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \ 61*1bb76ff1Sjsg SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\ 62*1bb76ff1Sjsg SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\ 63*1bb76ff1Sjsg SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\ 64*1bb76ff1Sjsg SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\ 65*1bb76ff1Sjsg SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\ 66*1bb76ff1Sjsg SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\ 67*1bb76ff1Sjsg SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\ 68*1bb76ff1Sjsg SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh) 69*1bb76ff1Sjsg 70*1bb76ff1Sjsg void dcn201_timing_generator_init(struct optc *optc); 71*1bb76ff1Sjsg 72*1bb76ff1Sjsg bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing); 73*1bb76ff1Sjsg 74*1bb76ff1Sjsg #endif 75