1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn315_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 #include "dcn31/dcn31_resource.h" 39 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn30/dcn30_hubbub.h" 42 #include "dcn31/dcn31_hubbub.h" 43 #include "dcn30/dcn30_mpc.h" 44 #include "dcn31/dcn31_hubp.h" 45 #include "irq/dcn315/irq_service_dcn315.h" 46 #include "dcn30/dcn30_dpp.h" 47 #include "dcn31/dcn31_optc.h" 48 #include "dcn20/dcn20_hwseq.h" 49 #include "dcn30/dcn30_hwseq.h" 50 #include "dce110/dce110_hw_sequencer.h" 51 #include "dcn30/dcn30_opp.h" 52 #include "dcn20/dcn20_dsc.h" 53 #include "dcn30/dcn30_vpg.h" 54 #include "dcn30/dcn30_afmt.h" 55 #include "dcn30/dcn30_dio_stream_encoder.h" 56 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 58 #include "dcn31/dcn31_apg.h" 59 #include "dcn31/dcn31_dio_link_encoder.h" 60 #include "dcn31/dcn31_vpg.h" 61 #include "dcn31/dcn31_afmt.h" 62 #include "dce/dce_clock_source.h" 63 #include "dce/dce_audio.h" 64 #include "dce/dce_hwseq.h" 65 #include "clk_mgr.h" 66 #include "virtual/virtual_stream_encoder.h" 67 #include "dce110/dce110_resource.h" 68 #include "dml/display_mode_vba.h" 69 #include "dml/dcn31/dcn31_fpu.h" 70 #include "dcn31/dcn31_dccg.h" 71 #include "dcn10/dcn10_resource.h" 72 #include "dcn31/dcn31_panel_cntl.h" 73 74 #include "dcn30/dcn30_dwb.h" 75 #include "dcn30/dcn30_mmhubbub.h" 76 77 #include "dcn/dcn_3_1_5_offset.h" 78 #include "dcn/dcn_3_1_5_sh_mask.h" 79 #include "dpcs/dpcs_4_2_2_offset.h" 80 #include "dpcs/dpcs_4_2_2_sh_mask.h" 81 82 #define NBIO_BASE__INST0_SEG0 0x00000000 83 #define NBIO_BASE__INST0_SEG1 0x00000014 84 #define NBIO_BASE__INST0_SEG2 0x00000D20 85 #define NBIO_BASE__INST0_SEG3 0x00010400 86 #define NBIO_BASE__INST0_SEG4 0x0241B000 87 #define NBIO_BASE__INST0_SEG5 0x04040000 88 89 #define DPCS_BASE__INST0_SEG0 0x00000012 90 #define DPCS_BASE__INST0_SEG1 0x000000C0 91 #define DPCS_BASE__INST0_SEG2 0x000034C0 92 #define DPCS_BASE__INST0_SEG3 0x00009000 93 #define DPCS_BASE__INST0_SEG4 0x02403C00 94 #define DPCS_BASE__INST0_SEG5 0 95 96 #define DCN_BASE__INST0_SEG0 0x00000012 97 #define DCN_BASE__INST0_SEG1 0x000000C0 98 #define DCN_BASE__INST0_SEG2 0x000034C0 99 #define DCN_BASE__INST0_SEG3 0x00009000 100 #define DCN_BASE__INST0_SEG4 0x02403C00 101 #define DCN_BASE__INST0_SEG5 0 102 103 #define regBIF_BX_PF2_RSMU_INDEX 0x0000 104 #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX 1 105 #define regBIF_BX_PF2_RSMU_DATA 0x0001 106 #define regBIF_BX_PF2_RSMU_DATA_BASE_IDX 1 107 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e 108 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 109 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 110 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL 111 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a 112 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 113 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 114 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL 115 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b 116 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 117 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 118 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL 119 120 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 121 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 122 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 123 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 124 125 #include "reg_helper.h" 126 #include "dce/dmub_abm.h" 127 #include "dce/dmub_psr.h" 128 #include "dce/dce_aux.h" 129 #include "dce/dce_i2c.h" 130 131 #include "dml/dcn30/display_mode_vba_30.h" 132 #include "vm_helper.h" 133 #include "dcn20/dcn20_vmid.h" 134 135 #include "link_enc_cfg.h" 136 137 #define DCN3_15_MAX_DET_SIZE 384 138 #define DCN3_15_CRB_SEGMENT_SIZE_KB 64 139 #define DCN3_15_MAX_DET_SEGS (DCN3_15_MAX_DET_SIZE / DCN3_15_CRB_SEGMENT_SIZE_KB) 140 /* Minimum 2 extra segments need to be in compbuf and claimable to guarantee seamless mpo transitions */ 141 #define MIN_RESERVED_DET_SEGS 2 142 143 enum dcn31_clk_src_array_id { 144 DCN31_CLK_SRC_PLL0, 145 DCN31_CLK_SRC_PLL1, 146 DCN31_CLK_SRC_PLL2, 147 DCN31_CLK_SRC_PLL3, 148 DCN31_CLK_SRC_PLL4, 149 DCN30_CLK_SRC_TOTAL 150 }; 151 152 /* begin ********************* 153 * macros to expend register list macro defined in HW object header file 154 */ 155 156 /* DCN */ 157 /* TODO awful hack. fixup dcn20_dwb.h */ 158 #undef BASE_INNER 159 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 160 161 #define BASE(seg) BASE_INNER(seg) 162 163 #define SR(reg_name)\ 164 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 165 reg ## reg_name 166 167 #define SRI(reg_name, block, id)\ 168 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 169 reg ## block ## id ## _ ## reg_name 170 171 #define SRI2(reg_name, block, id)\ 172 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 173 reg ## reg_name 174 175 #define SRIR(var_name, reg_name, block, id)\ 176 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 177 reg ## block ## id ## _ ## reg_name 178 179 #define SRII(reg_name, block, id)\ 180 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 181 reg ## block ## id ## _ ## reg_name 182 183 #define SRII_MPC_RMU(reg_name, block, id)\ 184 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 185 reg ## block ## id ## _ ## reg_name 186 187 #define SRII_DWB(reg_name, temp_name, block, id)\ 188 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 189 reg ## block ## id ## _ ## temp_name 190 191 #define DCCG_SRII(reg_name, block, id)\ 192 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 193 reg ## block ## id ## _ ## reg_name 194 195 #define VUPDATE_SRII(reg_name, block, id)\ 196 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 197 reg ## reg_name ## _ ## block ## id 198 199 /* NBIO */ 200 #define NBIO_BASE_INNER(seg) \ 201 NBIO_BASE__INST0_SEG ## seg 202 203 #define NBIO_BASE(seg) \ 204 NBIO_BASE_INNER(seg) 205 206 #define NBIO_SR(reg_name)\ 207 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 208 regBIF_BX2_ ## reg_name 209 210 static const struct bios_registers bios_regs = { 211 NBIO_SR(BIOS_SCRATCH_3), 212 NBIO_SR(BIOS_SCRATCH_6) 213 }; 214 215 #define clk_src_regs(index, pllid)\ 216 [index] = {\ 217 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 218 } 219 220 static const struct dce110_clk_src_regs clk_src_regs[] = { 221 clk_src_regs(0, A), 222 clk_src_regs(1, B), 223 clk_src_regs(2, C), 224 clk_src_regs(3, D), 225 clk_src_regs(4, E) 226 }; 227 228 static const struct dce110_clk_src_shift cs_shift = { 229 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 230 }; 231 232 static const struct dce110_clk_src_mask cs_mask = { 233 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 234 }; 235 236 #define abm_regs(id)\ 237 [id] = {\ 238 ABM_DCN302_REG_LIST(id)\ 239 } 240 241 static const struct dce_abm_registers abm_regs[] = { 242 abm_regs(0), 243 abm_regs(1), 244 abm_regs(2), 245 abm_regs(3), 246 }; 247 248 static const struct dce_abm_shift abm_shift = { 249 ABM_MASK_SH_LIST_DCN30(__SHIFT) 250 }; 251 252 static const struct dce_abm_mask abm_mask = { 253 ABM_MASK_SH_LIST_DCN30(_MASK) 254 }; 255 256 #define audio_regs(id)\ 257 [id] = {\ 258 AUD_COMMON_REG_LIST(id)\ 259 } 260 261 static const struct dce_audio_registers audio_regs[] = { 262 audio_regs(0), 263 audio_regs(1), 264 audio_regs(2), 265 audio_regs(3), 266 audio_regs(4), 267 audio_regs(5), 268 audio_regs(6) 269 }; 270 271 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 272 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 273 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 274 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 275 276 static const struct dce_audio_shift audio_shift = { 277 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 278 }; 279 280 static const struct dce_audio_mask audio_mask = { 281 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 282 }; 283 284 #define vpg_regs(id)\ 285 [id] = {\ 286 VPG_DCN31_REG_LIST(id)\ 287 } 288 289 static const struct dcn31_vpg_registers vpg_regs[] = { 290 vpg_regs(0), 291 vpg_regs(1), 292 vpg_regs(2), 293 vpg_regs(3), 294 vpg_regs(4), 295 vpg_regs(5), 296 vpg_regs(6), 297 vpg_regs(7), 298 vpg_regs(8), 299 vpg_regs(9), 300 }; 301 302 static const struct dcn31_vpg_shift vpg_shift = { 303 DCN31_VPG_MASK_SH_LIST(__SHIFT) 304 }; 305 306 static const struct dcn31_vpg_mask vpg_mask = { 307 DCN31_VPG_MASK_SH_LIST(_MASK) 308 }; 309 310 #define afmt_regs(id)\ 311 [id] = {\ 312 AFMT_DCN31_REG_LIST(id)\ 313 } 314 315 static const struct dcn31_afmt_registers afmt_regs[] = { 316 afmt_regs(0), 317 afmt_regs(1), 318 afmt_regs(2), 319 afmt_regs(3), 320 afmt_regs(4), 321 afmt_regs(5) 322 }; 323 324 static const struct dcn31_afmt_shift afmt_shift = { 325 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 326 }; 327 328 static const struct dcn31_afmt_mask afmt_mask = { 329 DCN31_AFMT_MASK_SH_LIST(_MASK) 330 }; 331 332 #define apg_regs(id)\ 333 [id] = {\ 334 APG_DCN31_REG_LIST(id)\ 335 } 336 337 static const struct dcn31_apg_registers apg_regs[] = { 338 apg_regs(0), 339 apg_regs(1), 340 apg_regs(2), 341 apg_regs(3) 342 }; 343 344 static const struct dcn31_apg_shift apg_shift = { 345 DCN31_APG_MASK_SH_LIST(__SHIFT) 346 }; 347 348 static const struct dcn31_apg_mask apg_mask = { 349 DCN31_APG_MASK_SH_LIST(_MASK) 350 }; 351 352 #define stream_enc_regs(id)\ 353 [id] = {\ 354 SE_DCN3_REG_LIST(id)\ 355 } 356 357 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 358 stream_enc_regs(0), 359 stream_enc_regs(1), 360 stream_enc_regs(2), 361 stream_enc_regs(3), 362 stream_enc_regs(4) 363 }; 364 365 static const struct dcn10_stream_encoder_shift se_shift = { 366 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 367 }; 368 369 static const struct dcn10_stream_encoder_mask se_mask = { 370 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 371 }; 372 373 374 #define aux_regs(id)\ 375 [id] = {\ 376 DCN2_AUX_REG_LIST(id)\ 377 } 378 379 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 380 aux_regs(0), 381 aux_regs(1), 382 aux_regs(2), 383 aux_regs(3), 384 aux_regs(4) 385 }; 386 387 #define hpd_regs(id)\ 388 [id] = {\ 389 HPD_REG_LIST(id)\ 390 } 391 392 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 393 hpd_regs(0), 394 hpd_regs(1), 395 hpd_regs(2), 396 hpd_regs(3), 397 hpd_regs(4) 398 }; 399 400 #define link_regs(id, phyid)\ 401 [id] = {\ 402 LE_DCN31_REG_LIST(id), \ 403 UNIPHY_DCN2_REG_LIST(phyid), \ 404 DPCS_DCN31_REG_LIST(id), \ 405 } 406 407 static const struct dce110_aux_registers_shift aux_shift = { 408 DCN_AUX_MASK_SH_LIST(__SHIFT) 409 }; 410 411 static const struct dce110_aux_registers_mask aux_mask = { 412 DCN_AUX_MASK_SH_LIST(_MASK) 413 }; 414 415 static const struct dcn10_link_enc_registers link_enc_regs[] = { 416 link_regs(0, A), 417 link_regs(1, B), 418 link_regs(2, C), 419 link_regs(3, D), 420 link_regs(4, E) 421 }; 422 423 static const struct dcn10_link_enc_shift le_shift = { 424 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 425 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 426 }; 427 428 static const struct dcn10_link_enc_mask le_mask = { 429 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 430 DPCS_DCN31_MASK_SH_LIST(_MASK) 431 }; 432 433 #define hpo_dp_stream_encoder_reg_list(id)\ 434 [id] = {\ 435 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 436 } 437 438 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 439 hpo_dp_stream_encoder_reg_list(0), 440 hpo_dp_stream_encoder_reg_list(1), 441 hpo_dp_stream_encoder_reg_list(2), 442 hpo_dp_stream_encoder_reg_list(3), 443 }; 444 445 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 446 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 447 }; 448 449 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 450 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 451 }; 452 453 454 #define hpo_dp_link_encoder_reg_list(id)\ 455 [id] = {\ 456 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 457 DCN3_1_RDPCSTX_REG_LIST(0),\ 458 DCN3_1_RDPCSTX_REG_LIST(1),\ 459 DCN3_1_RDPCSTX_REG_LIST(2),\ 460 DCN3_1_RDPCSTX_REG_LIST(3),\ 461 DCN3_1_RDPCSTX_REG_LIST(4)\ 462 } 463 464 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 465 hpo_dp_link_encoder_reg_list(0), 466 hpo_dp_link_encoder_reg_list(1), 467 }; 468 469 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 470 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 471 }; 472 473 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 474 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 475 }; 476 477 #define dpp_regs(id)\ 478 [id] = {\ 479 DPP_REG_LIST_DCN30(id),\ 480 } 481 482 static const struct dcn3_dpp_registers dpp_regs[] = { 483 dpp_regs(0), 484 dpp_regs(1), 485 dpp_regs(2), 486 dpp_regs(3) 487 }; 488 489 static const struct dcn3_dpp_shift tf_shift = { 490 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 491 }; 492 493 static const struct dcn3_dpp_mask tf_mask = { 494 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 495 }; 496 497 #define opp_regs(id)\ 498 [id] = {\ 499 OPP_REG_LIST_DCN30(id),\ 500 } 501 502 static const struct dcn20_opp_registers opp_regs[] = { 503 opp_regs(0), 504 opp_regs(1), 505 opp_regs(2), 506 opp_regs(3) 507 }; 508 509 static const struct dcn20_opp_shift opp_shift = { 510 OPP_MASK_SH_LIST_DCN20(__SHIFT) 511 }; 512 513 static const struct dcn20_opp_mask opp_mask = { 514 OPP_MASK_SH_LIST_DCN20(_MASK) 515 }; 516 517 #define aux_engine_regs(id)\ 518 [id] = {\ 519 AUX_COMMON_REG_LIST0(id), \ 520 .AUXN_IMPCAL = 0, \ 521 .AUXP_IMPCAL = 0, \ 522 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 523 } 524 525 static const struct dce110_aux_registers aux_engine_regs[] = { 526 aux_engine_regs(0), 527 aux_engine_regs(1), 528 aux_engine_regs(2), 529 aux_engine_regs(3), 530 aux_engine_regs(4) 531 }; 532 533 #define dwbc_regs_dcn3(id)\ 534 [id] = {\ 535 DWBC_COMMON_REG_LIST_DCN30(id),\ 536 } 537 538 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 539 dwbc_regs_dcn3(0), 540 }; 541 542 static const struct dcn30_dwbc_shift dwbc30_shift = { 543 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 544 }; 545 546 static const struct dcn30_dwbc_mask dwbc30_mask = { 547 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 548 }; 549 550 #define mcif_wb_regs_dcn3(id)\ 551 [id] = {\ 552 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 553 } 554 555 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 556 mcif_wb_regs_dcn3(0) 557 }; 558 559 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 560 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 561 }; 562 563 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 564 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 565 }; 566 567 #define dsc_regsDCN20(id)\ 568 [id] = {\ 569 DSC_REG_LIST_DCN20(id)\ 570 } 571 572 static const struct dcn20_dsc_registers dsc_regs[] = { 573 dsc_regsDCN20(0), 574 dsc_regsDCN20(1), 575 dsc_regsDCN20(2) 576 }; 577 578 static const struct dcn20_dsc_shift dsc_shift = { 579 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 580 }; 581 582 static const struct dcn20_dsc_mask dsc_mask = { 583 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 584 }; 585 586 static const struct dcn30_mpc_registers mpc_regs = { 587 MPC_REG_LIST_DCN3_0(0), 588 MPC_REG_LIST_DCN3_0(1), 589 MPC_REG_LIST_DCN3_0(2), 590 MPC_REG_LIST_DCN3_0(3), 591 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 592 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 593 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 594 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 595 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 596 }; 597 598 static const struct dcn30_mpc_shift mpc_shift = { 599 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 600 }; 601 602 static const struct dcn30_mpc_mask mpc_mask = { 603 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 604 }; 605 606 #define optc_regs(id)\ 607 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 608 609 static const struct dcn_optc_registers optc_regs[] = { 610 optc_regs(0), 611 optc_regs(1), 612 optc_regs(2), 613 optc_regs(3) 614 }; 615 616 static const struct dcn_optc_shift optc_shift = { 617 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 618 }; 619 620 static const struct dcn_optc_mask optc_mask = { 621 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 622 }; 623 624 #define hubp_regs(id)\ 625 [id] = {\ 626 HUBP_REG_LIST_DCN30(id)\ 627 } 628 629 static const struct dcn_hubp2_registers hubp_regs[] = { 630 hubp_regs(0), 631 hubp_regs(1), 632 hubp_regs(2), 633 hubp_regs(3) 634 }; 635 636 637 static const struct dcn_hubp2_shift hubp_shift = { 638 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 639 }; 640 641 static const struct dcn_hubp2_mask hubp_mask = { 642 HUBP_MASK_SH_LIST_DCN31(_MASK) 643 }; 644 static const struct dcn_hubbub_registers hubbub_reg = { 645 HUBBUB_REG_LIST_DCN31(0) 646 }; 647 648 static const struct dcn_hubbub_shift hubbub_shift = { 649 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 650 }; 651 652 static const struct dcn_hubbub_mask hubbub_mask = { 653 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 654 }; 655 656 static const struct dccg_registers dccg_regs = { 657 DCCG_REG_LIST_DCN31() 658 }; 659 660 static const struct dccg_shift dccg_shift = { 661 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 662 }; 663 664 static const struct dccg_mask dccg_mask = { 665 DCCG_MASK_SH_LIST_DCN31(_MASK) 666 }; 667 668 669 #define SRII2(reg_name_pre, reg_name_post, id)\ 670 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 671 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 672 reg ## reg_name_pre ## id ## _ ## reg_name_post 673 674 675 #define HWSEQ_DCN31_REG_LIST()\ 676 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 677 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 678 SR(DIO_MEM_PWR_CTRL), \ 679 SR(ODM_MEM_PWR_CTRL3), \ 680 SR(DMU_MEM_PWR_CNTL), \ 681 SR(MMHUBBUB_MEM_PWR_CNTL), \ 682 SR(DCCG_GATE_DISABLE_CNTL), \ 683 SR(DCCG_GATE_DISABLE_CNTL2), \ 684 SR(DCFCLK_CNTL),\ 685 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 686 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 687 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 688 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 689 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 691 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 692 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 694 SR(MICROSECOND_TIME_BASE_DIV), \ 695 SR(MILLISECOND_TIME_BASE_DIV), \ 696 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 697 SR(RBBMIF_TIMEOUT_DIS), \ 698 SR(RBBMIF_TIMEOUT_DIS_2), \ 699 SR(DCHUBBUB_CRC_CTRL), \ 700 SR(DPP_TOP0_DPP_CRC_CTRL), \ 701 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 702 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 703 SR(MPC_CRC_CTRL), \ 704 SR(MPC_CRC_RESULT_GB), \ 705 SR(MPC_CRC_RESULT_C), \ 706 SR(MPC_CRC_RESULT_AR), \ 707 SR(DOMAIN0_PG_CONFIG), \ 708 SR(DOMAIN1_PG_CONFIG), \ 709 SR(DOMAIN2_PG_CONFIG), \ 710 SR(DOMAIN3_PG_CONFIG), \ 711 SR(DOMAIN16_PG_CONFIG), \ 712 SR(DOMAIN17_PG_CONFIG), \ 713 SR(DOMAIN18_PG_CONFIG), \ 714 SR(DOMAIN0_PG_STATUS), \ 715 SR(DOMAIN1_PG_STATUS), \ 716 SR(DOMAIN2_PG_STATUS), \ 717 SR(DOMAIN3_PG_STATUS), \ 718 SR(DOMAIN16_PG_STATUS), \ 719 SR(DOMAIN17_PG_STATUS), \ 720 SR(DOMAIN18_PG_STATUS), \ 721 SR(D1VGA_CONTROL), \ 722 SR(D2VGA_CONTROL), \ 723 SR(D3VGA_CONTROL), \ 724 SR(D4VGA_CONTROL), \ 725 SR(D5VGA_CONTROL), \ 726 SR(D6VGA_CONTROL), \ 727 SR(DC_IP_REQUEST_CNTL), \ 728 SR(AZALIA_AUDIO_DTO), \ 729 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 730 SR(HPO_TOP_HW_CONTROL) 731 732 static const struct dce_hwseq_registers hwseq_reg = { 733 HWSEQ_DCN31_REG_LIST() 734 }; 735 736 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 737 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 738 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 739 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 740 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 741 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 742 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 743 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 744 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 745 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 746 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 747 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 748 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 749 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 750 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 751 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 752 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 753 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 754 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 755 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 756 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 757 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 758 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 759 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 760 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 761 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 762 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 763 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 764 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 765 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 766 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 767 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 768 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 769 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 770 771 static const struct dce_hwseq_shift hwseq_shift = { 772 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 773 }; 774 775 static const struct dce_hwseq_mask hwseq_mask = { 776 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 777 }; 778 #define vmid_regs(id)\ 779 [id] = {\ 780 DCN20_VMID_REG_LIST(id)\ 781 } 782 783 static const struct dcn_vmid_registers vmid_regs[] = { 784 vmid_regs(0), 785 vmid_regs(1), 786 vmid_regs(2), 787 vmid_regs(3), 788 vmid_regs(4), 789 vmid_regs(5), 790 vmid_regs(6), 791 vmid_regs(7), 792 vmid_regs(8), 793 vmid_regs(9), 794 vmid_regs(10), 795 vmid_regs(11), 796 vmid_regs(12), 797 vmid_regs(13), 798 vmid_regs(14), 799 vmid_regs(15) 800 }; 801 802 static const struct dcn20_vmid_shift vmid_shifts = { 803 DCN20_VMID_MASK_SH_LIST(__SHIFT) 804 }; 805 806 static const struct dcn20_vmid_mask vmid_masks = { 807 DCN20_VMID_MASK_SH_LIST(_MASK) 808 }; 809 810 static const struct resource_caps res_cap_dcn31 = { 811 .num_timing_generator = 4, 812 .num_opp = 4, 813 .num_video_plane = 4, 814 .num_audio = 5, 815 .num_stream_encoder = 5, 816 .num_dig_link_enc = 5, 817 .num_hpo_dp_stream_encoder = 4, 818 .num_hpo_dp_link_encoder = 2, 819 .num_pll = 5, 820 .num_dwb = 1, 821 .num_ddc = 5, 822 .num_vmid = 16, 823 .num_mpc_3dlut = 2, 824 .num_dsc = 3, 825 }; 826 827 static const struct dc_plane_cap plane_cap = { 828 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 829 .blends_with_above = true, 830 .blends_with_below = true, 831 .per_pixel_alpha = true, 832 833 .pixel_format_support = { 834 .argb8888 = true, 835 .nv12 = true, 836 .fp16 = true, 837 .p010 = true, 838 .ayuv = false, 839 }, 840 841 .max_upscale_factor = { 842 .argb8888 = 16000, 843 .nv12 = 16000, 844 .fp16 = 16000 845 }, 846 847 // 6:1 downscaling ratio: 1000/6 = 166.666 848 .max_downscale_factor = { 849 .argb8888 = 167, 850 .nv12 = 167, 851 .fp16 = 167 852 }, 853 64, 854 64 855 }; 856 857 static const struct dc_debug_options debug_defaults_drv = { 858 .disable_z10 = true, /*hw not support it*/ 859 .disable_dmcu = true, 860 .force_abm_enable = false, 861 .timing_trace = false, 862 .clock_trace = true, 863 .disable_pplib_clock_request = false, 864 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 865 .force_single_disp_pipe_split = false, 866 .disable_dcc = DCC_ENABLE, 867 .vsr_support = true, 868 .performance_trace = false, 869 .max_downscale_src_width = 4096,/*upto true 4k*/ 870 .disable_pplib_wm_range = false, 871 .scl_reset_length10 = true, 872 .sanity_checks = false, 873 .underflow_assert_delay_us = 0xFFFFFFFF, 874 .dwb_fi_phase = -1, // -1 = disable, 875 .dmub_command_table = true, 876 .pstate_enabled = true, 877 .use_max_lb = true, 878 .enable_mem_low_power = { 879 .bits = { 880 .vga = true, 881 .i2c = true, 882 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 883 .dscl = true, 884 .cm = true, 885 .mpc = true, 886 .optc = true, 887 .vpg = true, 888 .afmt = true, 889 } 890 }, 891 .psr_power_use_phy_fsm = 0, 892 }; 893 894 static const struct dc_debug_options debug_defaults_diags = { 895 .disable_dmcu = true, 896 .force_abm_enable = false, 897 .timing_trace = true, 898 .clock_trace = true, 899 .disable_dpp_power_gate = true, 900 .disable_hubp_power_gate = true, 901 .disable_clock_gate = true, 902 .disable_pplib_clock_request = true, 903 .disable_pplib_wm_range = true, 904 .disable_stutter = false, 905 .scl_reset_length10 = true, 906 .dwb_fi_phase = -1, // -1 = disable 907 .dmub_command_table = true, 908 .enable_tri_buf = true, 909 .use_max_lb = true 910 }; 911 912 static const struct dc_panel_config panel_config_defaults = { 913 .psr = { 914 .disable_psr = false, 915 .disallow_psrsu = false, 916 }, 917 .ilr = { 918 .optimize_edp_link_rate = true, 919 }, 920 }; 921 922 static void dcn31_dpp_destroy(struct dpp **dpp) 923 { 924 kfree(TO_DCN20_DPP(*dpp)); 925 *dpp = NULL; 926 } 927 928 static struct dpp *dcn31_dpp_create( 929 struct dc_context *ctx, 930 uint32_t inst) 931 { 932 struct dcn3_dpp *dpp = 933 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 934 935 if (!dpp) 936 return NULL; 937 938 if (dpp3_construct(dpp, ctx, inst, 939 &dpp_regs[inst], &tf_shift, &tf_mask)) 940 return &dpp->base; 941 942 BREAK_TO_DEBUGGER(); 943 kfree(dpp); 944 return NULL; 945 } 946 947 static struct output_pixel_processor *dcn31_opp_create( 948 struct dc_context *ctx, uint32_t inst) 949 { 950 struct dcn20_opp *opp = 951 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 952 953 if (!opp) { 954 BREAK_TO_DEBUGGER(); 955 return NULL; 956 } 957 958 dcn20_opp_construct(opp, ctx, inst, 959 &opp_regs[inst], &opp_shift, &opp_mask); 960 return &opp->base; 961 } 962 963 static struct dce_aux *dcn31_aux_engine_create( 964 struct dc_context *ctx, 965 uint32_t inst) 966 { 967 struct aux_engine_dce110 *aux_engine = 968 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 969 970 if (!aux_engine) 971 return NULL; 972 973 dce110_aux_engine_construct(aux_engine, ctx, inst, 974 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 975 &aux_engine_regs[inst], 976 &aux_mask, 977 &aux_shift, 978 ctx->dc->caps.extended_aux_timeout_support); 979 980 return &aux_engine->base; 981 } 982 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 983 984 static const struct dce_i2c_registers i2c_hw_regs[] = { 985 i2c_inst_regs(1), 986 i2c_inst_regs(2), 987 i2c_inst_regs(3), 988 i2c_inst_regs(4), 989 i2c_inst_regs(5), 990 }; 991 992 static const struct dce_i2c_shift i2c_shifts = { 993 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 994 }; 995 996 static const struct dce_i2c_mask i2c_masks = { 997 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 998 }; 999 1000 static struct dce_i2c_hw *dcn31_i2c_hw_create( 1001 struct dc_context *ctx, 1002 uint32_t inst) 1003 { 1004 struct dce_i2c_hw *dce_i2c_hw = 1005 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1006 1007 if (!dce_i2c_hw) 1008 return NULL; 1009 1010 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1011 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1012 1013 return dce_i2c_hw; 1014 } 1015 static struct mpc *dcn31_mpc_create( 1016 struct dc_context *ctx, 1017 int num_mpcc, 1018 int num_rmu) 1019 { 1020 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1021 GFP_KERNEL); 1022 1023 if (!mpc30) 1024 return NULL; 1025 1026 dcn30_mpc_construct(mpc30, ctx, 1027 &mpc_regs, 1028 &mpc_shift, 1029 &mpc_mask, 1030 num_mpcc, 1031 num_rmu); 1032 1033 return &mpc30->base; 1034 } 1035 1036 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1037 { 1038 int i; 1039 1040 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1041 GFP_KERNEL); 1042 1043 if (!hubbub3) 1044 return NULL; 1045 1046 hubbub31_construct(hubbub3, ctx, 1047 &hubbub_reg, 1048 &hubbub_shift, 1049 &hubbub_mask, 1050 dcn3_15_ip.det_buffer_size_kbytes, 1051 dcn3_15_ip.pixel_chunk_size_kbytes, 1052 dcn3_15_ip.config_return_buffer_size_in_kbytes); 1053 1054 1055 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1056 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1057 1058 vmid->ctx = ctx; 1059 1060 vmid->regs = &vmid_regs[i]; 1061 vmid->shifts = &vmid_shifts; 1062 vmid->masks = &vmid_masks; 1063 } 1064 1065 return &hubbub3->base; 1066 } 1067 1068 static struct timing_generator *dcn31_timing_generator_create( 1069 struct dc_context *ctx, 1070 uint32_t instance) 1071 { 1072 struct optc *tgn10 = 1073 kzalloc(sizeof(struct optc), GFP_KERNEL); 1074 1075 if (!tgn10) 1076 return NULL; 1077 1078 tgn10->base.inst = instance; 1079 tgn10->base.ctx = ctx; 1080 1081 tgn10->tg_regs = &optc_regs[instance]; 1082 tgn10->tg_shift = &optc_shift; 1083 tgn10->tg_mask = &optc_mask; 1084 1085 dcn31_timing_generator_init(tgn10); 1086 1087 return &tgn10->base; 1088 } 1089 1090 static const struct encoder_feature_support link_enc_feature = { 1091 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1092 .max_hdmi_pixel_clock = 600000, 1093 .hdmi_ycbcr420_supported = true, 1094 .dp_ycbcr420_supported = true, 1095 .fec_supported = true, 1096 .flags.bits.IS_HBR2_CAPABLE = true, 1097 .flags.bits.IS_HBR3_CAPABLE = true, 1098 .flags.bits.IS_TPS3_CAPABLE = true, 1099 .flags.bits.IS_TPS4_CAPABLE = true 1100 }; 1101 1102 static struct link_encoder *dcn31_link_encoder_create( 1103 struct dc_context *ctx, 1104 const struct encoder_init_data *enc_init_data) 1105 { 1106 struct dcn20_link_encoder *enc20 = 1107 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1108 1109 if (!enc20) 1110 return NULL; 1111 1112 dcn31_link_encoder_construct(enc20, 1113 enc_init_data, 1114 &link_enc_feature, 1115 &link_enc_regs[enc_init_data->transmitter], 1116 &link_enc_aux_regs[enc_init_data->channel - 1], 1117 &link_enc_hpd_regs[enc_init_data->hpd_source], 1118 &le_shift, 1119 &le_mask); 1120 1121 return &enc20->enc10.base; 1122 } 1123 1124 /* Create a minimal link encoder object not associated with a particular 1125 * physical connector. 1126 * resource_funcs.link_enc_create_minimal 1127 */ 1128 static struct link_encoder *dcn31_link_enc_create_minimal( 1129 struct dc_context *ctx, enum engine_id eng_id) 1130 { 1131 struct dcn20_link_encoder *enc20; 1132 1133 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1134 return NULL; 1135 1136 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1137 if (!enc20) 1138 return NULL; 1139 1140 dcn31_link_encoder_construct_minimal( 1141 enc20, 1142 ctx, 1143 &link_enc_feature, 1144 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1145 eng_id); 1146 1147 return &enc20->enc10.base; 1148 } 1149 1150 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1151 { 1152 struct dcn31_panel_cntl *panel_cntl = 1153 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1154 1155 if (!panel_cntl) 1156 return NULL; 1157 1158 dcn31_panel_cntl_construct(panel_cntl, init_data); 1159 1160 return &panel_cntl->base; 1161 } 1162 1163 static void read_dce_straps( 1164 struct dc_context *ctx, 1165 struct resource_straps *straps) 1166 { 1167 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1168 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1169 1170 } 1171 1172 static struct audio *dcn31_create_audio( 1173 struct dc_context *ctx, unsigned int inst) 1174 { 1175 return dce_audio_create(ctx, inst, 1176 &audio_regs[inst], &audio_shift, &audio_mask); 1177 } 1178 1179 static struct vpg *dcn31_vpg_create( 1180 struct dc_context *ctx, 1181 uint32_t inst) 1182 { 1183 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1184 1185 if (!vpg31) 1186 return NULL; 1187 1188 vpg31_construct(vpg31, ctx, inst, 1189 &vpg_regs[inst], 1190 &vpg_shift, 1191 &vpg_mask); 1192 1193 return &vpg31->base; 1194 } 1195 1196 static struct afmt *dcn31_afmt_create( 1197 struct dc_context *ctx, 1198 uint32_t inst) 1199 { 1200 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1201 1202 if (!afmt31) 1203 return NULL; 1204 1205 afmt31_construct(afmt31, ctx, inst, 1206 &afmt_regs[inst], 1207 &afmt_shift, 1208 &afmt_mask); 1209 1210 // Light sleep by default, no need to power down here 1211 1212 return &afmt31->base; 1213 } 1214 1215 static struct apg *dcn31_apg_create( 1216 struct dc_context *ctx, 1217 uint32_t inst) 1218 { 1219 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1220 1221 if (!apg31) 1222 return NULL; 1223 1224 apg31_construct(apg31, ctx, inst, 1225 &apg_regs[inst], 1226 &apg_shift, 1227 &apg_mask); 1228 1229 return &apg31->base; 1230 } 1231 1232 static struct stream_encoder *dcn315_stream_encoder_create( 1233 enum engine_id eng_id, 1234 struct dc_context *ctx) 1235 { 1236 struct dcn10_stream_encoder *enc1; 1237 struct vpg *vpg; 1238 struct afmt *afmt; 1239 int vpg_inst; 1240 int afmt_inst; 1241 1242 /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/ 1243 1244 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1245 if (eng_id <= ENGINE_ID_DIGF) { 1246 vpg_inst = eng_id; 1247 afmt_inst = eng_id; 1248 } else 1249 return NULL; 1250 1251 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1252 vpg = dcn31_vpg_create(ctx, vpg_inst); 1253 afmt = dcn31_afmt_create(ctx, afmt_inst); 1254 1255 if (!enc1 || !vpg || !afmt) { 1256 kfree(enc1); 1257 kfree(vpg); 1258 kfree(afmt); 1259 return NULL; 1260 } 1261 1262 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1263 eng_id, vpg, afmt, 1264 &stream_enc_regs[eng_id], 1265 &se_shift, &se_mask); 1266 1267 return &enc1->base; 1268 } 1269 1270 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1271 enum engine_id eng_id, 1272 struct dc_context *ctx) 1273 { 1274 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1275 struct vpg *vpg; 1276 struct apg *apg; 1277 uint32_t hpo_dp_inst; 1278 uint32_t vpg_inst; 1279 uint32_t apg_inst; 1280 1281 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1282 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1283 1284 /* Mapping of VPG register blocks to HPO DP block instance: 1285 * VPG[6] -> HPO_DP[0] 1286 * VPG[7] -> HPO_DP[1] 1287 * VPG[8] -> HPO_DP[2] 1288 * VPG[9] -> HPO_DP[3] 1289 */ 1290 vpg_inst = hpo_dp_inst + 6; 1291 1292 /* Mapping of APG register blocks to HPO DP block instance: 1293 * APG[0] -> HPO_DP[0] 1294 * APG[1] -> HPO_DP[1] 1295 * APG[2] -> HPO_DP[2] 1296 * APG[3] -> HPO_DP[3] 1297 */ 1298 apg_inst = hpo_dp_inst; 1299 1300 /* allocate HPO stream encoder and create VPG sub-block */ 1301 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1302 vpg = dcn31_vpg_create(ctx, vpg_inst); 1303 apg = dcn31_apg_create(ctx, apg_inst); 1304 1305 if (!hpo_dp_enc31 || !vpg || !apg) { 1306 kfree(hpo_dp_enc31); 1307 kfree(vpg); 1308 kfree(apg); 1309 return NULL; 1310 } 1311 1312 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1313 hpo_dp_inst, eng_id, vpg, apg, 1314 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1315 &hpo_dp_se_shift, &hpo_dp_se_mask); 1316 1317 return &hpo_dp_enc31->base; 1318 } 1319 1320 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1321 uint8_t inst, 1322 struct dc_context *ctx) 1323 { 1324 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1325 1326 /* allocate HPO link encoder */ 1327 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1328 1329 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1330 &hpo_dp_link_enc_regs[inst], 1331 &hpo_dp_le_shift, &hpo_dp_le_mask); 1332 1333 return &hpo_dp_enc31->base; 1334 } 1335 1336 static struct dce_hwseq *dcn31_hwseq_create( 1337 struct dc_context *ctx) 1338 { 1339 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1340 1341 if (hws) { 1342 hws->ctx = ctx; 1343 hws->regs = &hwseq_reg; 1344 hws->shifts = &hwseq_shift; 1345 hws->masks = &hwseq_mask; 1346 /* DCN3.1 FPGA Workaround 1347 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1348 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1349 * function core_link_enable_stream 1350 */ 1351 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1352 hws->wa.dp_hpo_and_otg_sequence = true; 1353 } 1354 return hws; 1355 } 1356 static const struct resource_create_funcs res_create_funcs = { 1357 .read_dce_straps = read_dce_straps, 1358 .create_audio = dcn31_create_audio, 1359 .create_stream_encoder = dcn315_stream_encoder_create, 1360 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1361 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1362 .create_hwseq = dcn31_hwseq_create, 1363 }; 1364 1365 static const struct resource_create_funcs res_create_maximus_funcs = { 1366 .read_dce_straps = NULL, 1367 .create_audio = NULL, 1368 .create_stream_encoder = NULL, 1369 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1370 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1371 .create_hwseq = dcn31_hwseq_create, 1372 }; 1373 1374 static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) 1375 { 1376 unsigned int i; 1377 1378 for (i = 0; i < pool->base.stream_enc_count; i++) { 1379 if (pool->base.stream_enc[i] != NULL) { 1380 if (pool->base.stream_enc[i]->vpg != NULL) { 1381 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1382 pool->base.stream_enc[i]->vpg = NULL; 1383 } 1384 if (pool->base.stream_enc[i]->afmt != NULL) { 1385 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1386 pool->base.stream_enc[i]->afmt = NULL; 1387 } 1388 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1389 pool->base.stream_enc[i] = NULL; 1390 } 1391 } 1392 1393 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1394 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1395 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1396 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1397 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1398 } 1399 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1400 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1401 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1402 } 1403 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1404 pool->base.hpo_dp_stream_enc[i] = NULL; 1405 } 1406 } 1407 1408 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1409 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1410 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1411 pool->base.hpo_dp_link_enc[i] = NULL; 1412 } 1413 } 1414 1415 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1416 if (pool->base.dscs[i] != NULL) 1417 dcn20_dsc_destroy(&pool->base.dscs[i]); 1418 } 1419 1420 if (pool->base.mpc != NULL) { 1421 kfree(TO_DCN20_MPC(pool->base.mpc)); 1422 pool->base.mpc = NULL; 1423 } 1424 if (pool->base.hubbub != NULL) { 1425 kfree(pool->base.hubbub); 1426 pool->base.hubbub = NULL; 1427 } 1428 for (i = 0; i < pool->base.pipe_count; i++) { 1429 if (pool->base.dpps[i] != NULL) 1430 dcn31_dpp_destroy(&pool->base.dpps[i]); 1431 1432 if (pool->base.ipps[i] != NULL) 1433 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1434 1435 if (pool->base.hubps[i] != NULL) { 1436 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1437 pool->base.hubps[i] = NULL; 1438 } 1439 1440 if (pool->base.irqs != NULL) { 1441 dal_irq_service_destroy(&pool->base.irqs); 1442 } 1443 } 1444 1445 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1446 if (pool->base.engines[i] != NULL) 1447 dce110_engine_destroy(&pool->base.engines[i]); 1448 if (pool->base.hw_i2cs[i] != NULL) { 1449 kfree(pool->base.hw_i2cs[i]); 1450 pool->base.hw_i2cs[i] = NULL; 1451 } 1452 if (pool->base.sw_i2cs[i] != NULL) { 1453 kfree(pool->base.sw_i2cs[i]); 1454 pool->base.sw_i2cs[i] = NULL; 1455 } 1456 } 1457 1458 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1459 if (pool->base.opps[i] != NULL) 1460 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1461 } 1462 1463 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1464 if (pool->base.timing_generators[i] != NULL) { 1465 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1466 pool->base.timing_generators[i] = NULL; 1467 } 1468 } 1469 1470 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1471 if (pool->base.dwbc[i] != NULL) { 1472 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1473 pool->base.dwbc[i] = NULL; 1474 } 1475 if (pool->base.mcif_wb[i] != NULL) { 1476 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1477 pool->base.mcif_wb[i] = NULL; 1478 } 1479 } 1480 1481 for (i = 0; i < pool->base.audio_count; i++) { 1482 if (pool->base.audios[i]) 1483 dce_aud_destroy(&pool->base.audios[i]); 1484 } 1485 1486 for (i = 0; i < pool->base.clk_src_count; i++) { 1487 if (pool->base.clock_sources[i] != NULL) { 1488 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1489 pool->base.clock_sources[i] = NULL; 1490 } 1491 } 1492 1493 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1494 if (pool->base.mpc_lut[i] != NULL) { 1495 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1496 pool->base.mpc_lut[i] = NULL; 1497 } 1498 if (pool->base.mpc_shaper[i] != NULL) { 1499 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1500 pool->base.mpc_shaper[i] = NULL; 1501 } 1502 } 1503 1504 if (pool->base.dp_clock_source != NULL) { 1505 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1506 pool->base.dp_clock_source = NULL; 1507 } 1508 1509 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1510 if (pool->base.multiple_abms[i] != NULL) 1511 dce_abm_destroy(&pool->base.multiple_abms[i]); 1512 } 1513 1514 if (pool->base.psr != NULL) 1515 dmub_psr_destroy(&pool->base.psr); 1516 1517 if (pool->base.dccg != NULL) 1518 dcn_dccg_destroy(&pool->base.dccg); 1519 } 1520 1521 static struct hubp *dcn31_hubp_create( 1522 struct dc_context *ctx, 1523 uint32_t inst) 1524 { 1525 struct dcn20_hubp *hubp2 = 1526 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1527 1528 if (!hubp2) 1529 return NULL; 1530 1531 if (hubp31_construct(hubp2, ctx, inst, 1532 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1533 return &hubp2->base; 1534 1535 BREAK_TO_DEBUGGER(); 1536 kfree(hubp2); 1537 return NULL; 1538 } 1539 1540 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1541 { 1542 int i; 1543 uint32_t pipe_count = pool->res_cap->num_dwb; 1544 1545 for (i = 0; i < pipe_count; i++) { 1546 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1547 GFP_KERNEL); 1548 1549 if (!dwbc30) { 1550 dm_error("DC: failed to create dwbc30!\n"); 1551 return false; 1552 } 1553 1554 dcn30_dwbc_construct(dwbc30, ctx, 1555 &dwbc30_regs[i], 1556 &dwbc30_shift, 1557 &dwbc30_mask, 1558 i); 1559 1560 pool->dwbc[i] = &dwbc30->base; 1561 } 1562 return true; 1563 } 1564 1565 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1566 { 1567 int i; 1568 uint32_t pipe_count = pool->res_cap->num_dwb; 1569 1570 for (i = 0; i < pipe_count; i++) { 1571 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1572 GFP_KERNEL); 1573 1574 if (!mcif_wb30) { 1575 dm_error("DC: failed to create mcif_wb30!\n"); 1576 return false; 1577 } 1578 1579 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1580 &mcif_wb30_regs[i], 1581 &mcif_wb30_shift, 1582 &mcif_wb30_mask, 1583 i); 1584 1585 pool->mcif_wb[i] = &mcif_wb30->base; 1586 } 1587 return true; 1588 } 1589 1590 static struct display_stream_compressor *dcn31_dsc_create( 1591 struct dc_context *ctx, uint32_t inst) 1592 { 1593 struct dcn20_dsc *dsc = 1594 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1595 1596 if (!dsc) { 1597 BREAK_TO_DEBUGGER(); 1598 return NULL; 1599 } 1600 1601 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1602 return &dsc->base; 1603 } 1604 1605 static void dcn315_destroy_resource_pool(struct resource_pool **pool) 1606 { 1607 struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool); 1608 1609 dcn315_resource_destruct(dcn31_pool); 1610 kfree(dcn31_pool); 1611 *pool = NULL; 1612 } 1613 1614 static struct clock_source *dcn31_clock_source_create( 1615 struct dc_context *ctx, 1616 struct dc_bios *bios, 1617 enum clock_source_id id, 1618 const struct dce110_clk_src_regs *regs, 1619 bool dp_clk_src) 1620 { 1621 struct dce110_clk_src *clk_src = 1622 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1623 1624 if (!clk_src) 1625 return NULL; 1626 1627 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1628 regs, &cs_shift, &cs_mask)) { 1629 clk_src->base.dp_clk_src = dp_clk_src; 1630 return &clk_src->base; 1631 } 1632 1633 BREAK_TO_DEBUGGER(); 1634 return NULL; 1635 } 1636 1637 static bool is_dual_plane(enum surface_pixel_format format) 1638 { 1639 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1640 } 1641 1642 static int source_format_to_bpp (enum source_format_class SourcePixelFormat) 1643 { 1644 if (SourcePixelFormat == dm_444_64) 1645 return 8; 1646 else if (SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_16) 1647 return 2; 1648 else if (SourcePixelFormat == dm_444_8) 1649 return 1; 1650 else if (SourcePixelFormat == dm_rgbe_alpha) 1651 return 5; 1652 else if (SourcePixelFormat == dm_420_8) 1653 return 3; 1654 else if (SourcePixelFormat == dm_420_12) 1655 return 6; 1656 else 1657 return 4; 1658 } 1659 1660 static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context) 1661 { 1662 int i; 1663 struct resource_context *res_ctx = &context->res_ctx; 1664 1665 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1666 if (!res_ctx->pipe_ctx[i].stream) 1667 continue; 1668 1669 /*Don't apply if MPO to avoid transition issues*/ 1670 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_ctx[i].plane_state) 1671 return false; 1672 } 1673 return true; 1674 } 1675 1676 static int dcn315_populate_dml_pipes_from_context( 1677 struct dc *dc, struct dc_state *context, 1678 display_e2e_pipe_params_st *pipes, 1679 bool fast_validate) 1680 { 1681 int i, pipe_cnt, crb_idx, crb_pipes; 1682 struct resource_context *res_ctx = &context->res_ctx; 1683 struct pipe_ctx *pipe; 1684 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB; 1685 int remaining_det_segs = max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB; 1686 bool pixel_rate_crb = allow_pixel_rate_crb(dc, context); 1687 1688 DC_FP_START(); 1689 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1690 DC_FP_END(); 1691 1692 for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) { 1693 struct dc_crtc_timing *timing; 1694 1695 if (!res_ctx->pipe_ctx[i].stream) 1696 continue; 1697 pipe = &res_ctx->pipe_ctx[i]; 1698 timing = &pipe->stream->timing; 1699 1700 /* 1701 * Immediate flip can be set dynamically after enabling the plane. 1702 * We need to require support for immediate flip or underflow can be 1703 * intermittently experienced depending on peak b/w requirements. 1704 */ 1705 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1706 1707 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1708 pipes[pipe_cnt].pipe.src.gpuvm = true; 1709 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1710 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1711 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1712 DC_FP_START(); 1713 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1714 if (pixel_rate_crb && !pipe->top_pipe && !pipe->prev_odm_pipe) { 1715 int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format); 1716 /* Ceil to crb segment size */ 1717 int approx_det_segs_required_for_pstate = dcn_get_approx_det_segs_required_for_pstate( 1718 &context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB); 1719 if (approx_det_segs_required_for_pstate <= 2 * DCN3_15_MAX_DET_SEGS) { 1720 bool split_required = approx_det_segs_required_for_pstate > DCN3_15_MAX_DET_SEGS; 1721 split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc); 1722 split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); 1723 if (split_required) 1724 approx_det_segs_required_for_pstate += approx_det_segs_required_for_pstate % 2; 1725 pipes[pipe_cnt].pipe.src.det_size_override = approx_det_segs_required_for_pstate; 1726 remaining_det_segs -= approx_det_segs_required_for_pstate; 1727 } else 1728 remaining_det_segs = -1; 1729 crb_pipes++; 1730 } 1731 DC_FP_END(); 1732 1733 if (pipes[pipe_cnt].dout.dsc_enable) { 1734 switch (timing->display_color_depth) { 1735 case COLOR_DEPTH_888: 1736 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1737 break; 1738 case COLOR_DEPTH_101010: 1739 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1740 break; 1741 case COLOR_DEPTH_121212: 1742 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1743 break; 1744 default: 1745 ASSERT(0); 1746 break; 1747 } 1748 } 1749 pipe_cnt++; 1750 } 1751 1752 /* Spread remaining unreserved crb evenly among all pipes, use default policy if not enough det or single pipe */ 1753 if (pixel_rate_crb) { 1754 for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) { 1755 pipe = &res_ctx->pipe_ctx[i]; 1756 if (!pipe->stream) 1757 continue; 1758 1759 if (!pipe->top_pipe && !pipe->prev_odm_pipe) { 1760 bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc) 1761 || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); 1762 1763 if (remaining_det_segs < 0 || crb_pipes == 1) 1764 pipes[pipe_cnt].pipe.src.det_size_override = 0; 1765 if (remaining_det_segs > MIN_RESERVED_DET_SEGS) 1766 pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS) / crb_pipes + 1767 (crb_idx < (remaining_det_segs - MIN_RESERVED_DET_SEGS) % crb_pipes ? 1 : 0); 1768 if (pipes[pipe_cnt].pipe.src.det_size_override > 2 * DCN3_15_MAX_DET_SEGS) { 1769 /* Clamp to 2 pipe split max det segments */ 1770 remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override - 2 * (DCN3_15_MAX_DET_SEGS); 1771 pipes[pipe_cnt].pipe.src.det_size_override = 2 * DCN3_15_MAX_DET_SEGS; 1772 } 1773 if (pipes[pipe_cnt].pipe.src.det_size_override > DCN3_15_MAX_DET_SEGS || split_required) { 1774 /* If we are splitting we must have an even number of segments */ 1775 remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override % 2; 1776 pipes[pipe_cnt].pipe.src.det_size_override -= pipes[pipe_cnt].pipe.src.det_size_override % 2; 1777 } 1778 /* Convert segments into size for DML use */ 1779 pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB; 1780 crb_idx++; 1781 } 1782 pipe_cnt++; 1783 } 1784 } 1785 1786 if (pipe_cnt) 1787 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1788 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1789 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE) 1790 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE; 1791 1792 dc->config.enable_4to1MPC = false; 1793 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1794 if (is_dual_plane(pipe->plane_state->format) 1795 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1796 dc->config.enable_4to1MPC = true; 1797 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1798 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1799 } else if (!is_dual_plane(pipe->plane_state->format) 1800 && pipe->plane_state->src_rect.width <= 5120 1801 && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) { 1802 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ 1803 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1804 pipes[0].pipe.src.unbounded_req_mode = true; 1805 } 1806 } 1807 1808 return pipe_cnt; 1809 } 1810 1811 static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_config) 1812 { 1813 *panel_config = panel_config_defaults; 1814 } 1815 1816 static struct dc_cap_funcs cap_funcs = { 1817 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1818 }; 1819 1820 static struct resource_funcs dcn315_res_pool_funcs = { 1821 .destroy = dcn315_destroy_resource_pool, 1822 .link_enc_create = dcn31_link_encoder_create, 1823 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1824 .link_encs_assign = link_enc_cfg_link_encs_assign, 1825 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1826 .panel_cntl_create = dcn31_panel_cntl_create, 1827 .validate_bandwidth = dcn31_validate_bandwidth, 1828 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1829 .update_soc_for_wm_a = dcn315_update_soc_for_wm_a, 1830 .populate_dml_pipes = dcn315_populate_dml_pipes_from_context, 1831 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1832 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1833 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1834 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1835 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, 1836 .set_mcif_arb_params = dcn31_set_mcif_arb_params, 1837 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1838 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1839 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1840 .update_bw_bounding_box = dcn315_update_bw_bounding_box, 1841 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1842 .get_panel_config_defaults = dcn315_get_panel_config_defaults, 1843 }; 1844 1845 static bool dcn315_resource_construct( 1846 uint8_t num_virtual_links, 1847 struct dc *dc, 1848 struct dcn315_resource_pool *pool) 1849 { 1850 int i; 1851 struct dc_context *ctx = dc->ctx; 1852 struct irq_service_init_data init_data; 1853 1854 ctx->dc_bios->regs = &bios_regs; 1855 1856 pool->base.res_cap = &res_cap_dcn31; 1857 1858 pool->base.funcs = &dcn315_res_pool_funcs; 1859 1860 /************************************************* 1861 * Resource + asic cap harcoding * 1862 *************************************************/ 1863 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1864 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1865 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1866 dc->caps.max_downscale_ratio = 600; 1867 dc->caps.i2c_speed_in_khz = 100; 1868 dc->caps.i2c_speed_in_khz_hdcp = 100; 1869 dc->caps.max_cursor_size = 256; 1870 dc->caps.min_horizontal_blanking_period = 80; 1871 dc->caps.dmdata_alloc_size = 2048; 1872 dc->caps.max_slave_planes = 2; 1873 dc->caps.max_slave_yuv_planes = 2; 1874 dc->caps.max_slave_rgb_planes = 2; 1875 dc->caps.post_blend_color_processing = true; 1876 dc->caps.force_dp_tps4_for_cp2520 = true; 1877 dc->caps.dp_hpo = true; 1878 dc->caps.dp_hdmi21_pcon_support = true; 1879 dc->caps.edp_dsc_support = true; 1880 dc->caps.extended_aux_timeout_support = true; 1881 dc->caps.dmcub_support = true; 1882 dc->caps.is_apu = true; 1883 1884 /* Color pipeline capabilities */ 1885 dc->caps.color.dpp.dcn_arch = 1; 1886 dc->caps.color.dpp.input_lut_shared = 0; 1887 dc->caps.color.dpp.icsc = 1; 1888 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1889 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1890 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1891 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1892 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1893 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1894 dc->caps.color.dpp.post_csc = 1; 1895 dc->caps.color.dpp.gamma_corr = 1; 1896 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1897 1898 dc->caps.color.dpp.hw_3d_lut = 1; 1899 dc->caps.color.dpp.ogam_ram = 1; 1900 // no OGAM ROM on DCN301 1901 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1902 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1903 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1904 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1905 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1906 dc->caps.color.dpp.ocsc = 0; 1907 1908 dc->caps.color.mpc.gamut_remap = 1; 1909 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1910 dc->caps.color.mpc.ogam_ram = 1; 1911 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1912 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1913 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1914 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1915 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1916 dc->caps.color.mpc.ocsc = 1; 1917 1918 /* read VBIOS LTTPR caps */ 1919 { 1920 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1921 enum bp_result bp_query_result; 1922 uint8_t is_vbios_lttpr_enable = 0; 1923 1924 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1925 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1926 } 1927 1928 /* interop bit is implicit */ 1929 { 1930 dc->caps.vbios_lttpr_aware = true; 1931 } 1932 } 1933 1934 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1935 dc->debug = debug_defaults_drv; 1936 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1937 dc->debug = debug_defaults_diags; 1938 } else 1939 dc->debug = debug_defaults_diags; 1940 // Init the vm_helper 1941 if (dc->vm_helper) 1942 vm_helper_init(dc->vm_helper, 16); 1943 1944 /************************************************* 1945 * Create resources * 1946 *************************************************/ 1947 1948 /* Clock Sources for Pixel Clock*/ 1949 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1950 dcn31_clock_source_create(ctx, ctx->dc_bios, 1951 CLOCK_SOURCE_COMBO_PHY_PLL0, 1952 &clk_src_regs[0], false); 1953 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1954 dcn31_clock_source_create(ctx, ctx->dc_bios, 1955 CLOCK_SOURCE_COMBO_PHY_PLL1, 1956 &clk_src_regs[1], false); 1957 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1958 dcn31_clock_source_create(ctx, ctx->dc_bios, 1959 CLOCK_SOURCE_COMBO_PHY_PLL2, 1960 &clk_src_regs[2], false); 1961 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1962 dcn31_clock_source_create(ctx, ctx->dc_bios, 1963 CLOCK_SOURCE_COMBO_PHY_PLL3, 1964 &clk_src_regs[3], false); 1965 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1966 dcn31_clock_source_create(ctx, ctx->dc_bios, 1967 CLOCK_SOURCE_COMBO_PHY_PLL4, 1968 &clk_src_regs[4], false); 1969 1970 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1971 1972 /* todo: not reuse phy_pll registers */ 1973 pool->base.dp_clock_source = 1974 dcn31_clock_source_create(ctx, ctx->dc_bios, 1975 CLOCK_SOURCE_ID_DP_DTO, 1976 &clk_src_regs[0], true); 1977 1978 for (i = 0; i < pool->base.clk_src_count; i++) { 1979 if (pool->base.clock_sources[i] == NULL) { 1980 dm_error("DC: failed to create clock sources!\n"); 1981 BREAK_TO_DEBUGGER(); 1982 goto create_fail; 1983 } 1984 } 1985 1986 /* TODO: DCCG */ 1987 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1988 if (pool->base.dccg == NULL) { 1989 dm_error("DC: failed to create dccg!\n"); 1990 BREAK_TO_DEBUGGER(); 1991 goto create_fail; 1992 } 1993 1994 /* TODO: IRQ */ 1995 init_data.ctx = dc->ctx; 1996 pool->base.irqs = dal_irq_service_dcn315_create(&init_data); 1997 if (!pool->base.irqs) 1998 goto create_fail; 1999 2000 /* HUBBUB */ 2001 pool->base.hubbub = dcn31_hubbub_create(ctx); 2002 if (pool->base.hubbub == NULL) { 2003 BREAK_TO_DEBUGGER(); 2004 dm_error("DC: failed to create hubbub!\n"); 2005 goto create_fail; 2006 } 2007 2008 /* HUBPs, DPPs, OPPs and TGs */ 2009 for (i = 0; i < pool->base.pipe_count; i++) { 2010 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2011 if (pool->base.hubps[i] == NULL) { 2012 BREAK_TO_DEBUGGER(); 2013 dm_error( 2014 "DC: failed to create hubps!\n"); 2015 goto create_fail; 2016 } 2017 2018 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2019 if (pool->base.dpps[i] == NULL) { 2020 BREAK_TO_DEBUGGER(); 2021 dm_error( 2022 "DC: failed to create dpps!\n"); 2023 goto create_fail; 2024 } 2025 } 2026 2027 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2028 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2029 if (pool->base.opps[i] == NULL) { 2030 BREAK_TO_DEBUGGER(); 2031 dm_error( 2032 "DC: failed to create output pixel processor!\n"); 2033 goto create_fail; 2034 } 2035 } 2036 2037 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2038 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2039 ctx, i); 2040 if (pool->base.timing_generators[i] == NULL) { 2041 BREAK_TO_DEBUGGER(); 2042 dm_error("DC: failed to create tg!\n"); 2043 goto create_fail; 2044 } 2045 } 2046 pool->base.timing_generator_count = i; 2047 2048 /* PSR */ 2049 pool->base.psr = dmub_psr_create(ctx); 2050 if (pool->base.psr == NULL) { 2051 dm_error("DC: failed to create psr obj!\n"); 2052 BREAK_TO_DEBUGGER(); 2053 goto create_fail; 2054 } 2055 2056 /* ABM */ 2057 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2058 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2059 &abm_regs[i], 2060 &abm_shift, 2061 &abm_mask); 2062 if (pool->base.multiple_abms[i] == NULL) { 2063 dm_error("DC: failed to create abm for pipe %d!\n", i); 2064 BREAK_TO_DEBUGGER(); 2065 goto create_fail; 2066 } 2067 } 2068 2069 /* MPC and DSC */ 2070 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2071 if (pool->base.mpc == NULL) { 2072 BREAK_TO_DEBUGGER(); 2073 dm_error("DC: failed to create mpc!\n"); 2074 goto create_fail; 2075 } 2076 2077 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2078 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 2079 if (pool->base.dscs[i] == NULL) { 2080 BREAK_TO_DEBUGGER(); 2081 dm_error("DC: failed to create display stream compressor %d!\n", i); 2082 goto create_fail; 2083 } 2084 } 2085 2086 /* DWB and MMHUBBUB */ 2087 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2088 BREAK_TO_DEBUGGER(); 2089 dm_error("DC: failed to create dwbc!\n"); 2090 goto create_fail; 2091 } 2092 2093 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2094 BREAK_TO_DEBUGGER(); 2095 dm_error("DC: failed to create mcif_wb!\n"); 2096 goto create_fail; 2097 } 2098 2099 /* AUX and I2C */ 2100 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2101 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2102 if (pool->base.engines[i] == NULL) { 2103 BREAK_TO_DEBUGGER(); 2104 dm_error( 2105 "DC:failed to create aux engine!!\n"); 2106 goto create_fail; 2107 } 2108 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2109 if (pool->base.hw_i2cs[i] == NULL) { 2110 BREAK_TO_DEBUGGER(); 2111 dm_error( 2112 "DC:failed to create hw i2c!!\n"); 2113 goto create_fail; 2114 } 2115 pool->base.sw_i2cs[i] = NULL; 2116 } 2117 2118 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2119 if (!resource_construct(num_virtual_links, dc, &pool->base, 2120 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2121 &res_create_funcs : &res_create_maximus_funcs))) 2122 goto create_fail; 2123 2124 /* HW Sequencer and Plane caps */ 2125 dcn31_hw_sequencer_construct(dc); 2126 2127 dc->caps.max_planes = pool->base.pipe_count; 2128 2129 for (i = 0; i < dc->caps.max_planes; ++i) 2130 dc->caps.planes[i] = plane_cap; 2131 2132 dc->cap_funcs = cap_funcs; 2133 2134 dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp; 2135 2136 return true; 2137 2138 create_fail: 2139 2140 dcn315_resource_destruct(pool); 2141 2142 return false; 2143 } 2144 2145 struct resource_pool *dcn315_create_resource_pool( 2146 const struct dc_init_data *init_data, 2147 struct dc *dc) 2148 { 2149 struct dcn315_resource_pool *pool = 2150 kzalloc(sizeof(struct dcn315_resource_pool), GFP_KERNEL); 2151 2152 if (!pool) 2153 return NULL; 2154 2155 if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool)) 2156 return &pool->base; 2157 2158 BREAK_TO_DEBUGGER(); 2159 kfree(pool); 2160 return NULL; 2161 } 2162