1c349dbc7Sjsg /*
2c349dbc7Sjsg * Copyright 2012-17 Advanced Micro Devices, Inc.
3c349dbc7Sjsg *
4c349dbc7Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
5c349dbc7Sjsg * copy of this software and associated documentation files (the "Software"),
6c349dbc7Sjsg * to deal in the Software without restriction, including without limitation
7c349dbc7Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8c349dbc7Sjsg * and/or sell copies of the Software, and to permit persons to whom the
9c349dbc7Sjsg * Software is furnished to do so, subject to the following conditions:
10c349dbc7Sjsg *
11c349dbc7Sjsg * The above copyright notice and this permission notice shall be included in
12c349dbc7Sjsg * all copies or substantial portions of the Software.
13c349dbc7Sjsg *
14c349dbc7Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15c349dbc7Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16c349dbc7Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17c349dbc7Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18c349dbc7Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19c349dbc7Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20c349dbc7Sjsg * OTHER DEALINGS IN THE SOFTWARE.
21c349dbc7Sjsg *
22c349dbc7Sjsg * Authors: AMD
23c349dbc7Sjsg *
24c349dbc7Sjsg */
251bb76ff1Sjsg #include <drm/display/drm_dsc_helper.h>
26c349dbc7Sjsg #include "dscc_types.h"
27c349dbc7Sjsg #include "rc_calc.h"
28c349dbc7Sjsg
copy_pps_fields(struct drm_dsc_config * to,const struct drm_dsc_config * from)29c349dbc7Sjsg static void copy_pps_fields(struct drm_dsc_config *to, const struct drm_dsc_config *from)
30c349dbc7Sjsg {
31c349dbc7Sjsg to->line_buf_depth = from->line_buf_depth;
32c349dbc7Sjsg to->bits_per_component = from->bits_per_component;
33c349dbc7Sjsg to->convert_rgb = from->convert_rgb;
34c349dbc7Sjsg to->slice_width = from->slice_width;
35c349dbc7Sjsg to->slice_height = from->slice_height;
36c349dbc7Sjsg to->simple_422 = from->simple_422;
37c349dbc7Sjsg to->native_422 = from->native_422;
38c349dbc7Sjsg to->native_420 = from->native_420;
39c349dbc7Sjsg to->pic_width = from->pic_width;
40c349dbc7Sjsg to->pic_height = from->pic_height;
41c349dbc7Sjsg to->rc_tgt_offset_high = from->rc_tgt_offset_high;
42c349dbc7Sjsg to->rc_tgt_offset_low = from->rc_tgt_offset_low;
43c349dbc7Sjsg to->bits_per_pixel = from->bits_per_pixel;
44c349dbc7Sjsg to->rc_edge_factor = from->rc_edge_factor;
45c349dbc7Sjsg to->rc_quant_incr_limit1 = from->rc_quant_incr_limit1;
46c349dbc7Sjsg to->rc_quant_incr_limit0 = from->rc_quant_incr_limit0;
47c349dbc7Sjsg to->initial_xmit_delay = from->initial_xmit_delay;
48c349dbc7Sjsg to->initial_dec_delay = from->initial_dec_delay;
49c349dbc7Sjsg to->block_pred_enable = from->block_pred_enable;
50c349dbc7Sjsg to->first_line_bpg_offset = from->first_line_bpg_offset;
51c349dbc7Sjsg to->second_line_bpg_offset = from->second_line_bpg_offset;
52c349dbc7Sjsg to->initial_offset = from->initial_offset;
53c349dbc7Sjsg memcpy(&to->rc_buf_thresh, &from->rc_buf_thresh, sizeof(from->rc_buf_thresh));
54c349dbc7Sjsg memcpy(&to->rc_range_params, &from->rc_range_params, sizeof(from->rc_range_params));
55c349dbc7Sjsg to->rc_model_size = from->rc_model_size;
56c349dbc7Sjsg to->flatness_min_qp = from->flatness_min_qp;
57c349dbc7Sjsg to->flatness_max_qp = from->flatness_max_qp;
58c349dbc7Sjsg to->initial_scale_value = from->initial_scale_value;
59c349dbc7Sjsg to->scale_decrement_interval = from->scale_decrement_interval;
60c349dbc7Sjsg to->scale_increment_interval = from->scale_increment_interval;
61c349dbc7Sjsg to->nfl_bpg_offset = from->nfl_bpg_offset;
62c349dbc7Sjsg to->nsl_bpg_offset = from->nsl_bpg_offset;
63c349dbc7Sjsg to->slice_bpg_offset = from->slice_bpg_offset;
64c349dbc7Sjsg to->final_offset = from->final_offset;
65c349dbc7Sjsg to->vbr_enable = from->vbr_enable;
66c349dbc7Sjsg to->slice_chunk_size = from->slice_chunk_size;
67c349dbc7Sjsg to->second_line_offset_adj = from->second_line_offset_adj;
68c349dbc7Sjsg to->dsc_version_minor = from->dsc_version_minor;
69c349dbc7Sjsg }
70c349dbc7Sjsg
copy_rc_to_cfg(struct drm_dsc_config * dsc_cfg,const struct rc_params * rc)71c349dbc7Sjsg static void copy_rc_to_cfg(struct drm_dsc_config *dsc_cfg, const struct rc_params *rc)
72c349dbc7Sjsg {
73c349dbc7Sjsg int i;
74c349dbc7Sjsg
75c349dbc7Sjsg dsc_cfg->rc_quant_incr_limit0 = rc->rc_quant_incr_limit0;
76c349dbc7Sjsg dsc_cfg->rc_quant_incr_limit1 = rc->rc_quant_incr_limit1;
77c349dbc7Sjsg dsc_cfg->initial_offset = rc->initial_fullness_offset;
78c349dbc7Sjsg dsc_cfg->initial_xmit_delay = rc->initial_xmit_delay;
79c349dbc7Sjsg dsc_cfg->first_line_bpg_offset = rc->first_line_bpg_offset;
80c349dbc7Sjsg dsc_cfg->second_line_bpg_offset = rc->second_line_bpg_offset;
81c349dbc7Sjsg dsc_cfg->flatness_min_qp = rc->flatness_min_qp;
82c349dbc7Sjsg dsc_cfg->flatness_max_qp = rc->flatness_max_qp;
83c349dbc7Sjsg for (i = 0; i < QP_SET_SIZE; ++i) {
84c349dbc7Sjsg dsc_cfg->rc_range_params[i].range_min_qp = rc->qp_min[i];
85c349dbc7Sjsg dsc_cfg->rc_range_params[i].range_max_qp = rc->qp_max[i];
86c349dbc7Sjsg /* Truncate 8-bit signed value to 6-bit signed value */
87c349dbc7Sjsg dsc_cfg->rc_range_params[i].range_bpg_offset = 0x3f & rc->ofs[i];
88c349dbc7Sjsg }
89c349dbc7Sjsg dsc_cfg->rc_model_size = rc->rc_model_size;
90c349dbc7Sjsg dsc_cfg->rc_edge_factor = rc->rc_edge_factor;
91c349dbc7Sjsg dsc_cfg->rc_tgt_offset_high = rc->rc_tgt_offset_hi;
92c349dbc7Sjsg dsc_cfg->rc_tgt_offset_low = rc->rc_tgt_offset_lo;
93c349dbc7Sjsg
94c349dbc7Sjsg for (i = 0; i < QP_SET_SIZE - 1; ++i)
95c349dbc7Sjsg dsc_cfg->rc_buf_thresh[i] = rc->rc_buf_thresh[i];
96c349dbc7Sjsg }
97c349dbc7Sjsg
dscc_compute_dsc_parameters(const struct drm_dsc_config * pps,const struct rc_params * rc,struct dsc_parameters * dsc_params)98*f005ef32Sjsg int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps,
99*f005ef32Sjsg const struct rc_params *rc,
100*f005ef32Sjsg struct dsc_parameters *dsc_params)
101c349dbc7Sjsg {
102c349dbc7Sjsg int ret;
103c349dbc7Sjsg struct drm_dsc_config dsc_cfg;
1041bb76ff1Sjsg unsigned long long tmp;
105c349dbc7Sjsg
106c349dbc7Sjsg dsc_params->pps = *pps;
107*f005ef32Sjsg dsc_params->pps.initial_scale_value = 8 * rc->rc_model_size / (rc->rc_model_size - rc->initial_fullness_offset);
108c349dbc7Sjsg
109c349dbc7Sjsg copy_pps_fields(&dsc_cfg, &dsc_params->pps);
110*f005ef32Sjsg copy_rc_to_cfg(&dsc_cfg, rc);
111c349dbc7Sjsg
112c349dbc7Sjsg dsc_cfg.mux_word_size = dsc_params->pps.bits_per_component <= 10 ? 48 : 64;
113c349dbc7Sjsg
114c349dbc7Sjsg ret = drm_dsc_compute_rc_parameters(&dsc_cfg);
1151bb76ff1Sjsg tmp = (unsigned long long)dsc_cfg.slice_chunk_size * 0x10000000 + (dsc_cfg.slice_width - 1);
1161bb76ff1Sjsg do_div(tmp, (uint32_t)dsc_cfg.slice_width); //ROUND-UP
1171bb76ff1Sjsg dsc_params->bytes_per_pixel = (uint32_t)tmp;
118c349dbc7Sjsg
119c349dbc7Sjsg copy_pps_fields(&dsc_params->pps, &dsc_cfg);
120c349dbc7Sjsg dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits;
121c349dbc7Sjsg return ret;
122c349dbc7Sjsg }
123c349dbc7Sjsg
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