1*5ca02815Sjsg // SPDX-License-Identifier: MIT
2*5ca02815Sjsg /*
3*5ca02815Sjsg  * Copyright (C) 2021 Advanced Micro Devices, Inc.
4*5ca02815Sjsg  *
5*5ca02815Sjsg  * Authors: AMD
6*5ca02815Sjsg  */
7*5ca02815Sjsg 
8*5ca02815Sjsg #include "../dmub_srv.h"
9*5ca02815Sjsg #include "dmub_reg.h"
10*5ca02815Sjsg #include "dmub_dcn303.h"
11*5ca02815Sjsg 
12*5ca02815Sjsg #include "sienna_cichlid_ip_offset.h"
13*5ca02815Sjsg #include "dcn/dcn_3_0_3_offset.h"
14*5ca02815Sjsg #include "dcn/dcn_3_0_3_sh_mask.h"
15*5ca02815Sjsg 
16*5ca02815Sjsg #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
17*5ca02815Sjsg #define CTX dmub
18*5ca02815Sjsg #define REGS dmub->regs
19*5ca02815Sjsg 
20*5ca02815Sjsg /* Registers. */
21*5ca02815Sjsg 
22*5ca02815Sjsg const struct dmub_srv_common_regs dmub_srv_dcn303_regs = {
23*5ca02815Sjsg #define DMUB_SR(reg) REG_OFFSET(reg),
24*5ca02815Sjsg 	{
25*5ca02815Sjsg 		DMUB_COMMON_REGS()
26*5ca02815Sjsg 		DMCUB_INTERNAL_REGS()
27*5ca02815Sjsg 	},
28*5ca02815Sjsg #undef DMUB_SR
29*5ca02815Sjsg 
30*5ca02815Sjsg #define DMUB_SF(reg, field) FD_MASK(reg, field),
31*5ca02815Sjsg 	{ DMUB_COMMON_FIELDS() },
32*5ca02815Sjsg #undef DMUB_SF
33*5ca02815Sjsg 
34*5ca02815Sjsg #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
35*5ca02815Sjsg 	{ DMUB_COMMON_FIELDS() },
36*5ca02815Sjsg #undef DMUB_SF
37*5ca02815Sjsg };
38*5ca02815Sjsg 
39*5ca02815Sjsg /* Shared functions. */
40*5ca02815Sjsg 
41