1*fb4d8502Sjsg /* 2*fb4d8502Sjsg * 3*fb4d8502Sjsg * Copyright (C) 2016 Advanced Micro Devices, Inc. 4*fb4d8502Sjsg * 5*fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 6*fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 7*fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 8*fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9*fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 10*fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 11*fb4d8502Sjsg * 12*fb4d8502Sjsg * The above copyright notice and this permission notice shall be included 13*fb4d8502Sjsg * in all copies or substantial portions of the Software. 14*fb4d8502Sjsg * 15*fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16*fb4d8502Sjsg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19*fb4d8502Sjsg * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20*fb4d8502Sjsg * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21*fb4d8502Sjsg */ 22*fb4d8502Sjsg 23*fb4d8502Sjsg #ifndef BIF_3_0_D_H 24*fb4d8502Sjsg #define BIF_3_0_D_H 25*fb4d8502Sjsg 26*fb4d8502Sjsg #define ixPB0_DFT_DEBUG_CTRL_REG0 0x1300C 27*fb4d8502Sjsg #define ixPB0_DFT_JIT_INJ_REG0 0x13000 28*fb4d8502Sjsg #define ixPB0_DFT_JIT_INJ_REG1 0x13004 29*fb4d8502Sjsg #define ixPB0_DFT_JIT_INJ_REG2 0x13008 30*fb4d8502Sjsg #define ixPB0_GLB_CTRL_REG0 0x10004 31*fb4d8502Sjsg #define ixPB0_GLB_CTRL_REG1 0x10008 32*fb4d8502Sjsg #define ixPB0_GLB_CTRL_REG2 0x1000C 33*fb4d8502Sjsg #define ixPB0_GLB_CTRL_REG3 0x10010 34*fb4d8502Sjsg #define ixPB0_GLB_CTRL_REG4 0x10014 35*fb4d8502Sjsg #define ixPB0_GLB_CTRL_REG5 0x10018 36*fb4d8502Sjsg #define ixPB0_GLB_OVRD_REG0 0x10030 37*fb4d8502Sjsg #define ixPB0_GLB_OVRD_REG1 0x10034 38*fb4d8502Sjsg #define ixPB0_GLB_OVRD_REG2 0x10038 39*fb4d8502Sjsg #define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x1001C 40*fb4d8502Sjsg #define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x10020 41*fb4d8502Sjsg #define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x10024 42*fb4d8502Sjsg #define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x10028 43*fb4d8502Sjsg #define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x1002C 44*fb4d8502Sjsg #define ixPB0_HW_DEBUG 0x12004 45*fb4d8502Sjsg #define ixPB0_PIF_CNTL 0x0010 46*fb4d8502Sjsg #define ixPB0_PIF_CNTL2 0x0014 47*fb4d8502Sjsg #define ixPB0_PIF_HW_DEBUG 0x0002 48*fb4d8502Sjsg #define ixPB0_PIF_PAIRING 0x0011 49*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_0 0x0020 50*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_10 0x0032 51*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_1 0x0021 52*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_11 0x0033 53*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_12 0x0034 54*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_13 0x0035 55*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_14 0x0036 56*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_15 0x0037 57*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_2 0x0022 58*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_3 0x0023 59*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_4 0x0024 60*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_5 0x0025 61*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_6 0x0026 62*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_7 0x0027 63*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_8 0x0030 64*fb4d8502Sjsg #define ixPB0_PIF_PDNB_OVERRIDE_9 0x0031 65*fb4d8502Sjsg #define ixPB0_PIF_PWRDOWN_0 0x0012 66*fb4d8502Sjsg #define ixPB0_PIF_PWRDOWN_1 0x0013 67*fb4d8502Sjsg #define ixPB0_PIF_PWRDOWN_2 0x0017 68*fb4d8502Sjsg #define ixPB0_PIF_PWRDOWN_3 0x0018 69*fb4d8502Sjsg #define ixPB0_PIF_SC_CTL 0x0016 70*fb4d8502Sjsg #define ixPB0_PIF_SCRATCH 0x0001 71*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_0 0x0028 72*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_10 0x003A 73*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_1 0x0029 74*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_11 0x003B 75*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_12 0x003C 76*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_13 0x003D 77*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_14 0x003E 78*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_15 0x003F 79*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_2 0x002A 80*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_3 0x002B 81*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_4 0x002C 82*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_5 0x002D 83*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_6 0x002E 84*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_7 0x002F 85*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_8 0x0038 86*fb4d8502Sjsg #define ixPB0_PIF_SEQ_STATUS_9 0x0039 87*fb4d8502Sjsg #define ixPB0_PIF_TXPHYSTATUS 0x0015 88*fb4d8502Sjsg #define ixPB0_PLL_LC0_CTRL_REG0 0x14480 89*fb4d8502Sjsg #define ixPB0_PLL_LC0_OVRD_REG0 0x14490 90*fb4d8502Sjsg #define ixPB0_PLL_LC0_OVRD_REG1 0x14494 91*fb4d8502Sjsg #define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500 92*fb4d8502Sjsg #define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504 93*fb4d8502Sjsg #define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508 94*fb4d8502Sjsg #define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C 95*fb4d8502Sjsg #define ixPB0_PLL_RO0_CTRL_REG0 0x14440 96*fb4d8502Sjsg #define ixPB0_PLL_RO0_OVRD_REG0 0x14450 97*fb4d8502Sjsg #define ixPB0_PLL_RO0_OVRD_REG1 0x14454 98*fb4d8502Sjsg #define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460 99*fb4d8502Sjsg #define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464 100*fb4d8502Sjsg #define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468 101*fb4d8502Sjsg #define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C 102*fb4d8502Sjsg #define ixPB0_PLL_RO_GLB_CTRL_REG0 0x14000 103*fb4d8502Sjsg #define ixPB0_PLL_RO_GLB_OVRD_REG0 0x14010 104*fb4d8502Sjsg #define ixPB0_RX_GLB_CTRL_REG0 0x16000 105*fb4d8502Sjsg #define ixPB0_RX_GLB_CTRL_REG1 0x16004 106*fb4d8502Sjsg #define ixPB0_RX_GLB_CTRL_REG2 0x16008 107*fb4d8502Sjsg #define ixPB0_RX_GLB_CTRL_REG3 0x1600C 108*fb4d8502Sjsg #define ixPB0_RX_GLB_CTRL_REG4 0x16010 109*fb4d8502Sjsg #define ixPB0_RX_GLB_CTRL_REG5 0x16014 110*fb4d8502Sjsg #define ixPB0_RX_GLB_CTRL_REG6 0x16018 111*fb4d8502Sjsg #define ixPB0_RX_GLB_CTRL_REG7 0x1601C 112*fb4d8502Sjsg #define ixPB0_RX_GLB_CTRL_REG8 0x16020 113*fb4d8502Sjsg #define ixPB0_RX_GLB_OVRD_REG0 0x16030 114*fb4d8502Sjsg #define ixPB0_RX_GLB_OVRD_REG1 0x16034 115*fb4d8502Sjsg #define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x16028 116*fb4d8502Sjsg #define ixPB0_RX_LANE0_CTRL_REG0 0x16440 117*fb4d8502Sjsg #define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448 118*fb4d8502Sjsg #define ixPB0_RX_LANE10_CTRL_REG0 0x17500 119*fb4d8502Sjsg #define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508 120*fb4d8502Sjsg #define ixPB0_RX_LANE11_CTRL_REG0 0x17600 121*fb4d8502Sjsg #define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608 122*fb4d8502Sjsg #define ixPB0_RX_LANE12_CTRL_REG0 0x17840 123*fb4d8502Sjsg #define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848 124*fb4d8502Sjsg #define ixPB0_RX_LANE13_CTRL_REG0 0x17880 125*fb4d8502Sjsg #define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888 126*fb4d8502Sjsg #define ixPB0_RX_LANE14_CTRL_REG0 0x17900 127*fb4d8502Sjsg #define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908 128*fb4d8502Sjsg #define ixPB0_RX_LANE15_CTRL_REG0 0x17A00 129*fb4d8502Sjsg #define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08 130*fb4d8502Sjsg #define ixPB0_RX_LANE1_CTRL_REG0 0x16480 131*fb4d8502Sjsg #define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488 132*fb4d8502Sjsg #define ixPB0_RX_LANE2_CTRL_REG0 0x16500 133*fb4d8502Sjsg #define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508 134*fb4d8502Sjsg #define ixPB0_RX_LANE3_CTRL_REG0 0x16600 135*fb4d8502Sjsg #define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608 136*fb4d8502Sjsg #define ixPB0_RX_LANE4_CTRL_REG0 0x16800 137*fb4d8502Sjsg #define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848 138*fb4d8502Sjsg #define ixPB0_RX_LANE5_CTRL_REG0 0x16880 139*fb4d8502Sjsg #define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888 140*fb4d8502Sjsg #define ixPB0_RX_LANE6_CTRL_REG0 0x16900 141*fb4d8502Sjsg #define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908 142*fb4d8502Sjsg #define ixPB0_RX_LANE7_CTRL_REG0 0x16A00 143*fb4d8502Sjsg #define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08 144*fb4d8502Sjsg #define ixPB0_RX_LANE8_CTRL_REG0 0x17440 145*fb4d8502Sjsg #define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448 146*fb4d8502Sjsg #define ixPB0_RX_LANE9_CTRL_REG0 0x17480 147*fb4d8502Sjsg #define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488 148*fb4d8502Sjsg #define ixPB0_STRAP_GLB_REG0 0x12020 149*fb4d8502Sjsg #define ixPB0_STRAP_PLL_REG0 0x12030 150*fb4d8502Sjsg #define ixPB0_STRAP_RX_REG0 0x12028 151*fb4d8502Sjsg #define ixPB0_STRAP_RX_REG1 0x1202C 152*fb4d8502Sjsg #define ixPB0_STRAP_TX_REG0 0x12024 153*fb4d8502Sjsg #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014 154*fb4d8502Sjsg #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018 155*fb4d8502Sjsg #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C 156*fb4d8502Sjsg #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020 157*fb4d8502Sjsg #define ixPB0_TX_GLB_CTRL_REG0 0x18000 158*fb4d8502Sjsg #define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x18004 159*fb4d8502Sjsg #define ixPB0_TX_GLB_OVRD_REG0 0x18030 160*fb4d8502Sjsg #define ixPB0_TX_GLB_OVRD_REG1 0x18034 161*fb4d8502Sjsg #define ixPB0_TX_GLB_OVRD_REG2 0x18038 162*fb4d8502Sjsg #define ixPB0_TX_GLB_OVRD_REG3 0x1803C 163*fb4d8502Sjsg #define ixPB0_TX_GLB_OVRD_REG4 0x18040 164*fb4d8502Sjsg #define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x18010 165*fb4d8502Sjsg #define ixPB0_TX_LANE0_CTRL_REG0 0x18440 166*fb4d8502Sjsg #define ixPB0_TX_LANE0_OVRD_REG0 0x18444 167*fb4d8502Sjsg #define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448 168*fb4d8502Sjsg #define ixPB0_TX_LANE10_CTRL_REG0 0x19500 169*fb4d8502Sjsg #define ixPB0_TX_LANE10_OVRD_REG0 0x19504 170*fb4d8502Sjsg #define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508 171*fb4d8502Sjsg #define ixPB0_TX_LANE11_CTRL_REG0 0x19600 172*fb4d8502Sjsg #define ixPB0_TX_LANE11_OVRD_REG0 0x19604 173*fb4d8502Sjsg #define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608 174*fb4d8502Sjsg #define ixPB0_TX_LANE12_CTRL_REG0 0x19840 175*fb4d8502Sjsg #define ixPB0_TX_LANE12_OVRD_REG0 0x19844 176*fb4d8502Sjsg #define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848 177*fb4d8502Sjsg #define ixPB0_TX_LANE13_CTRL_REG0 0x19880 178*fb4d8502Sjsg #define ixPB0_TX_LANE13_OVRD_REG0 0x19884 179*fb4d8502Sjsg #define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888 180*fb4d8502Sjsg #define ixPB0_TX_LANE14_CTRL_REG0 0x19900 181*fb4d8502Sjsg #define ixPB0_TX_LANE14_OVRD_REG0 0x19904 182*fb4d8502Sjsg #define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908 183*fb4d8502Sjsg #define ixPB0_TX_LANE15_CTRL_REG0 0x19A00 184*fb4d8502Sjsg #define ixPB0_TX_LANE15_OVRD_REG0 0x19A04 185*fb4d8502Sjsg #define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08 186*fb4d8502Sjsg #define ixPB0_TX_LANE1_CTRL_REG0 0x18480 187*fb4d8502Sjsg #define ixPB0_TX_LANE1_OVRD_REG0 0x18484 188*fb4d8502Sjsg #define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488 189*fb4d8502Sjsg #define ixPB0_TX_LANE2_CTRL_REG0 0x18500 190*fb4d8502Sjsg #define ixPB0_TX_LANE2_OVRD_REG0 0x18504 191*fb4d8502Sjsg #define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508 192*fb4d8502Sjsg #define ixPB0_TX_LANE3_CTRL_REG0 0x18600 193*fb4d8502Sjsg #define ixPB0_TX_LANE3_OVRD_REG0 0x18604 194*fb4d8502Sjsg #define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608 195*fb4d8502Sjsg #define ixPB0_TX_LANE4_CTRL_REG0 0x18840 196*fb4d8502Sjsg #define ixPB0_TX_LANE4_OVRD_REG0 0x18844 197*fb4d8502Sjsg #define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848 198*fb4d8502Sjsg #define ixPB0_TX_LANE5_CTRL_REG0 0x18880 199*fb4d8502Sjsg #define ixPB0_TX_LANE5_OVRD_REG0 0x18884 200*fb4d8502Sjsg #define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888 201*fb4d8502Sjsg #define ixPB0_TX_LANE6_CTRL_REG0 0x18900 202*fb4d8502Sjsg #define ixPB0_TX_LANE6_OVRD_REG0 0x18904 203*fb4d8502Sjsg #define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908 204*fb4d8502Sjsg #define ixPB0_TX_LANE7_CTRL_REG0 0x18A00 205*fb4d8502Sjsg #define ixPB0_TX_LANE7_OVRD_REG0 0x18A04 206*fb4d8502Sjsg #define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08 207*fb4d8502Sjsg #define ixPB0_TX_LANE8_CTRL_REG0 0x19440 208*fb4d8502Sjsg #define ixPB0_TX_LANE8_OVRD_REG0 0x19444 209*fb4d8502Sjsg #define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448 210*fb4d8502Sjsg #define ixPB0_TX_LANE9_CTRL_REG0 0x19480 211*fb4d8502Sjsg #define ixPB0_TX_LANE9_OVRD_REG0 0x19484 212*fb4d8502Sjsg #define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488 213*fb4d8502Sjsg #define ixPB1_DFT_DEBUG_CTRL_REG0 0x1300C 214*fb4d8502Sjsg #define ixPB1_DFT_JIT_INJ_REG0 0x13000 215*fb4d8502Sjsg #define ixPB1_DFT_JIT_INJ_REG1 0x13004 216*fb4d8502Sjsg #define ixPB1_DFT_JIT_INJ_REG2 0x13008 217*fb4d8502Sjsg #define ixPB1_GLB_CTRL_REG0 0x10004 218*fb4d8502Sjsg #define ixPB1_GLB_CTRL_REG1 0x10008 219*fb4d8502Sjsg #define ixPB1_GLB_CTRL_REG2 0x1000C 220*fb4d8502Sjsg #define ixPB1_GLB_CTRL_REG3 0x10010 221*fb4d8502Sjsg #define ixPB1_GLB_CTRL_REG4 0x10014 222*fb4d8502Sjsg #define ixPB1_GLB_CTRL_REG5 0x10018 223*fb4d8502Sjsg #define ixPB1_GLB_OVRD_REG0 0x10030 224*fb4d8502Sjsg #define ixPB1_GLB_OVRD_REG1 0x10034 225*fb4d8502Sjsg #define ixPB1_GLB_OVRD_REG2 0x10038 226*fb4d8502Sjsg #define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x1001C 227*fb4d8502Sjsg #define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x10020 228*fb4d8502Sjsg #define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x10024 229*fb4d8502Sjsg #define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x10028 230*fb4d8502Sjsg #define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x1002C 231*fb4d8502Sjsg #define ixPB1_HW_DEBUG 0x12004 232*fb4d8502Sjsg #define ixPB1_PIF_CNTL 0x0010 233*fb4d8502Sjsg #define ixPB1_PIF_CNTL2 0x0014 234*fb4d8502Sjsg #define ixPB1_PIF_HW_DEBUG 0x0002 235*fb4d8502Sjsg #define ixPB1_PIF_PAIRING 0x0011 236*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_0 0x0020 237*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_10 0x0032 238*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_1 0x0021 239*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_11 0x0033 240*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_12 0x0034 241*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_13 0x0035 242*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_14 0x0036 243*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_15 0x0037 244*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_2 0x0022 245*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_3 0x0023 246*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_4 0x0024 247*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_5 0x0025 248*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_6 0x0026 249*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_7 0x0027 250*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_8 0x0030 251*fb4d8502Sjsg #define ixPB1_PIF_PDNB_OVERRIDE_9 0x0031 252*fb4d8502Sjsg #define ixPB1_PIF_PWRDOWN_0 0x0012 253*fb4d8502Sjsg #define ixPB1_PIF_PWRDOWN_1 0x0013 254*fb4d8502Sjsg #define ixPB1_PIF_PWRDOWN_2 0x0017 255*fb4d8502Sjsg #define ixPB1_PIF_PWRDOWN_3 0x0018 256*fb4d8502Sjsg #define ixPB1_PIF_SC_CTL 0x0016 257*fb4d8502Sjsg #define ixPB1_PIF_SCRATCH 0x0001 258*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_0 0x0028 259*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_10 0x003A 260*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_1 0x0029 261*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_11 0x003B 262*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_12 0x003C 263*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_13 0x003D 264*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_14 0x003E 265*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_15 0x003F 266*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_2 0x002A 267*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_3 0x002B 268*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_4 0x002C 269*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_5 0x002D 270*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_6 0x002E 271*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_7 0x002F 272*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_8 0x0038 273*fb4d8502Sjsg #define ixPB1_PIF_SEQ_STATUS_9 0x0039 274*fb4d8502Sjsg #define ixPB1_PIF_TXPHYSTATUS 0x0015 275*fb4d8502Sjsg #define ixPB1_PLL_LC0_CTRL_REG0 0x14480 276*fb4d8502Sjsg #define ixPB1_PLL_LC0_OVRD_REG0 0x14490 277*fb4d8502Sjsg #define ixPB1_PLL_LC0_OVRD_REG1 0x14494 278*fb4d8502Sjsg #define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500 279*fb4d8502Sjsg #define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504 280*fb4d8502Sjsg #define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508 281*fb4d8502Sjsg #define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C 282*fb4d8502Sjsg #define ixPB1_PLL_RO0_CTRL_REG0 0x14440 283*fb4d8502Sjsg #define ixPB1_PLL_RO0_OVRD_REG0 0x14450 284*fb4d8502Sjsg #define ixPB1_PLL_RO0_OVRD_REG1 0x14454 285*fb4d8502Sjsg #define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460 286*fb4d8502Sjsg #define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464 287*fb4d8502Sjsg #define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468 288*fb4d8502Sjsg #define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C 289*fb4d8502Sjsg #define ixPB1_PLL_RO_GLB_CTRL_REG0 0x14000 290*fb4d8502Sjsg #define ixPB1_PLL_RO_GLB_OVRD_REG0 0x14010 291*fb4d8502Sjsg #define ixPB1_RX_GLB_CTRL_REG0 0x16000 292*fb4d8502Sjsg #define ixPB1_RX_GLB_CTRL_REG1 0x16004 293*fb4d8502Sjsg #define ixPB1_RX_GLB_CTRL_REG2 0x16008 294*fb4d8502Sjsg #define ixPB1_RX_GLB_CTRL_REG3 0x1600C 295*fb4d8502Sjsg #define ixPB1_RX_GLB_CTRL_REG4 0x16010 296*fb4d8502Sjsg #define ixPB1_RX_GLB_CTRL_REG5 0x16014 297*fb4d8502Sjsg #define ixPB1_RX_GLB_CTRL_REG6 0x16018 298*fb4d8502Sjsg #define ixPB1_RX_GLB_CTRL_REG7 0x1601C 299*fb4d8502Sjsg #define ixPB1_RX_GLB_CTRL_REG8 0x16020 300*fb4d8502Sjsg #define ixPB1_RX_GLB_OVRD_REG0 0x16030 301*fb4d8502Sjsg #define ixPB1_RX_GLB_OVRD_REG1 0x16034 302*fb4d8502Sjsg #define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x16028 303*fb4d8502Sjsg #define ixPB1_RX_LANE0_CTRL_REG0 0x16440 304*fb4d8502Sjsg #define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448 305*fb4d8502Sjsg #define ixPB1_RX_LANE10_CTRL_REG0 0x17500 306*fb4d8502Sjsg #define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508 307*fb4d8502Sjsg #define ixPB1_RX_LANE11_CTRL_REG0 0x17600 308*fb4d8502Sjsg #define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608 309*fb4d8502Sjsg #define ixPB1_RX_LANE12_CTRL_REG0 0x17840 310*fb4d8502Sjsg #define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848 311*fb4d8502Sjsg #define ixPB1_RX_LANE13_CTRL_REG0 0x17880 312*fb4d8502Sjsg #define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888 313*fb4d8502Sjsg #define ixPB1_RX_LANE14_CTRL_REG0 0x17900 314*fb4d8502Sjsg #define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908 315*fb4d8502Sjsg #define ixPB1_RX_LANE15_CTRL_REG0 0x17A00 316*fb4d8502Sjsg #define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08 317*fb4d8502Sjsg #define ixPB1_RX_LANE1_CTRL_REG0 0x16480 318*fb4d8502Sjsg #define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488 319*fb4d8502Sjsg #define ixPB1_RX_LANE2_CTRL_REG0 0x16500 320*fb4d8502Sjsg #define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508 321*fb4d8502Sjsg #define ixPB1_RX_LANE3_CTRL_REG0 0x16600 322*fb4d8502Sjsg #define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608 323*fb4d8502Sjsg #define ixPB1_RX_LANE4_CTRL_REG0 0x16800 324*fb4d8502Sjsg #define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848 325*fb4d8502Sjsg #define ixPB1_RX_LANE5_CTRL_REG0 0x16880 326*fb4d8502Sjsg #define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888 327*fb4d8502Sjsg #define ixPB1_RX_LANE6_CTRL_REG0 0x16900 328*fb4d8502Sjsg #define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908 329*fb4d8502Sjsg #define ixPB1_RX_LANE7_CTRL_REG0 0x16A00 330*fb4d8502Sjsg #define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08 331*fb4d8502Sjsg #define ixPB1_RX_LANE8_CTRL_REG0 0x17440 332*fb4d8502Sjsg #define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448 333*fb4d8502Sjsg #define ixPB1_RX_LANE9_CTRL_REG0 0x17480 334*fb4d8502Sjsg #define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488 335*fb4d8502Sjsg #define ixPB1_STRAP_GLB_REG0 0x12020 336*fb4d8502Sjsg #define ixPB1_STRAP_PLL_REG0 0x12030 337*fb4d8502Sjsg #define ixPB1_STRAP_RX_REG0 0x12028 338*fb4d8502Sjsg #define ixPB1_STRAP_RX_REG1 0x1202C 339*fb4d8502Sjsg #define ixPB1_STRAP_TX_REG0 0x12024 340*fb4d8502Sjsg #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014 341*fb4d8502Sjsg #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018 342*fb4d8502Sjsg #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C 343*fb4d8502Sjsg #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020 344*fb4d8502Sjsg #define ixPB1_TX_GLB_CTRL_REG0 0x18000 345*fb4d8502Sjsg #define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x18004 346*fb4d8502Sjsg #define ixPB1_TX_GLB_OVRD_REG0 0x18030 347*fb4d8502Sjsg #define ixPB1_TX_GLB_OVRD_REG1 0x18034 348*fb4d8502Sjsg #define ixPB1_TX_GLB_OVRD_REG2 0x18038 349*fb4d8502Sjsg #define ixPB1_TX_GLB_OVRD_REG3 0x1803C 350*fb4d8502Sjsg #define ixPB1_TX_GLB_OVRD_REG4 0x18040 351*fb4d8502Sjsg #define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x18010 352*fb4d8502Sjsg #define ixPB1_TX_LANE0_CTRL_REG0 0x18440 353*fb4d8502Sjsg #define ixPB1_TX_LANE0_OVRD_REG0 0x18444 354*fb4d8502Sjsg #define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448 355*fb4d8502Sjsg #define ixPB1_TX_LANE10_CTRL_REG0 0x19500 356*fb4d8502Sjsg #define ixPB1_TX_LANE10_OVRD_REG0 0x19504 357*fb4d8502Sjsg #define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508 358*fb4d8502Sjsg #define ixPB1_TX_LANE11_CTRL_REG0 0x19600 359*fb4d8502Sjsg #define ixPB1_TX_LANE11_OVRD_REG0 0x19604 360*fb4d8502Sjsg #define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608 361*fb4d8502Sjsg #define ixPB1_TX_LANE12_CTRL_REG0 0x19840 362*fb4d8502Sjsg #define ixPB1_TX_LANE12_OVRD_REG0 0x19844 363*fb4d8502Sjsg #define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848 364*fb4d8502Sjsg #define ixPB1_TX_LANE13_CTRL_REG0 0x19880 365*fb4d8502Sjsg #define ixPB1_TX_LANE13_OVRD_REG0 0x19884 366*fb4d8502Sjsg #define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888 367*fb4d8502Sjsg #define ixPB1_TX_LANE14_CTRL_REG0 0x19900 368*fb4d8502Sjsg #define ixPB1_TX_LANE14_OVRD_REG0 0x19904 369*fb4d8502Sjsg #define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908 370*fb4d8502Sjsg #define ixPB1_TX_LANE15_CTRL_REG0 0x19A00 371*fb4d8502Sjsg #define ixPB1_TX_LANE15_OVRD_REG0 0x19A04 372*fb4d8502Sjsg #define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08 373*fb4d8502Sjsg #define ixPB1_TX_LANE1_CTRL_REG0 0x18480 374*fb4d8502Sjsg #define ixPB1_TX_LANE1_OVRD_REG0 0x18484 375*fb4d8502Sjsg #define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488 376*fb4d8502Sjsg #define ixPB1_TX_LANE2_CTRL_REG0 0x18500 377*fb4d8502Sjsg #define ixPB1_TX_LANE2_OVRD_REG0 0x18504 378*fb4d8502Sjsg #define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508 379*fb4d8502Sjsg #define ixPB1_TX_LANE3_CTRL_REG0 0x18600 380*fb4d8502Sjsg #define ixPB1_TX_LANE3_OVRD_REG0 0x18604 381*fb4d8502Sjsg #define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608 382*fb4d8502Sjsg #define ixPB1_TX_LANE4_CTRL_REG0 0x18840 383*fb4d8502Sjsg #define ixPB1_TX_LANE4_OVRD_REG0 0x18844 384*fb4d8502Sjsg #define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848 385*fb4d8502Sjsg #define ixPB1_TX_LANE5_CTRL_REG0 0x18880 386*fb4d8502Sjsg #define ixPB1_TX_LANE5_OVRD_REG0 0x18884 387*fb4d8502Sjsg #define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888 388*fb4d8502Sjsg #define ixPB1_TX_LANE6_CTRL_REG0 0x18900 389*fb4d8502Sjsg #define ixPB1_TX_LANE6_OVRD_REG0 0x18904 390*fb4d8502Sjsg #define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908 391*fb4d8502Sjsg #define ixPB1_TX_LANE7_CTRL_REG0 0x18A00 392*fb4d8502Sjsg #define ixPB1_TX_LANE7_OVRD_REG0 0x18A04 393*fb4d8502Sjsg #define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08 394*fb4d8502Sjsg #define ixPB1_TX_LANE8_CTRL_REG0 0x19440 395*fb4d8502Sjsg #define ixPB1_TX_LANE8_OVRD_REG0 0x19444 396*fb4d8502Sjsg #define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448 397*fb4d8502Sjsg #define ixPB1_TX_LANE9_CTRL_REG0 0x19480 398*fb4d8502Sjsg #define ixPB1_TX_LANE9_OVRD_REG0 0x19484 399*fb4d8502Sjsg #define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488 400*fb4d8502Sjsg #define ixPCIE_BUS_CNTL 0x0021 401*fb4d8502Sjsg #define ixPCIE_CFG_CNTL 0x003C 402*fb4d8502Sjsg #define ixPCIE_CI_CNTL 0x0020 403*fb4d8502Sjsg #define ixPCIE_CNTL 0x0010 404*fb4d8502Sjsg #define ixPCIE_CNTL2 0x001C 405*fb4d8502Sjsg #define ixPCIE_CONFIG_CNTL 0x0011 406*fb4d8502Sjsg #define ixPCIE_DEBUG_CNTL 0x0012 407*fb4d8502Sjsg #define ixPCIE_ERR_CNTL 0x006A 408*fb4d8502Sjsg #define ixPCIE_F0_DPA_CAP 0x00E0 409*fb4d8502Sjsg #define ixPCIE_F0_DPA_CNTL 0x00E5 410*fb4d8502Sjsg #define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x00E4 411*fb4d8502Sjsg #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x00E7 412*fb4d8502Sjsg #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x00E8 413*fb4d8502Sjsg #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x00E9 414*fb4d8502Sjsg #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x00EA 415*fb4d8502Sjsg #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x00EB 416*fb4d8502Sjsg #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x00EC 417*fb4d8502Sjsg #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x00ED 418*fb4d8502Sjsg #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x00EE 419*fb4d8502Sjsg #define ixPCIE_FC_CPL 0x0062 420*fb4d8502Sjsg #define ixPCIE_FC_NP 0x0061 421*fb4d8502Sjsg #define ixPCIE_FC_P 0x0060 422*fb4d8502Sjsg #define ixPCIE_HW_DEBUG 0x0002 423*fb4d8502Sjsg #define ixPCIE_I2C_REG_ADDR_EXPAND 0x003A 424*fb4d8502Sjsg #define ixPCIE_I2C_REG_DATA 0x003B 425*fb4d8502Sjsg #define ixPCIE_INT_CNTL 0x001A 426*fb4d8502Sjsg #define ixPCIE_INT_STATUS 0x001B 427*fb4d8502Sjsg #define ixPCIE_LC_BEST_EQ_SETTINGS 0x00B9 428*fb4d8502Sjsg #define ixPCIE_LC_BW_CHANGE_CNTL 0x00B2 429*fb4d8502Sjsg #define ixPCIE_LC_CDR_CNTL 0x00B3 430*fb4d8502Sjsg #define ixPCIE_LC_CNTL 0x00A0 431*fb4d8502Sjsg #define ixPCIE_LC_CNTL2 0x00B1 432*fb4d8502Sjsg #define ixPCIE_LC_CNTL3 0x00B5 433*fb4d8502Sjsg #define ixPCIE_LC_CNTL4 0x00B6 434*fb4d8502Sjsg #define ixPCIE_LC_CNTL5 0x00B7 435*fb4d8502Sjsg #define ixPCIE_LC_FORCE_COEFF 0x00B8 436*fb4d8502Sjsg #define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x00BA 437*fb4d8502Sjsg #define ixPCIE_LC_LANE_CNTL 0x00B4 438*fb4d8502Sjsg #define ixPCIE_LC_LINK_WIDTH_CNTL 0x00A2 439*fb4d8502Sjsg #define ixPCIE_LC_N_FTS_CNTL 0x00A3 440*fb4d8502Sjsg #define ixPCIE_LC_SPEED_CNTL 0x00A4 441*fb4d8502Sjsg #define ixPCIE_LC_STATE0 0x00A5 442*fb4d8502Sjsg #define ixPCIE_LC_STATE10 0x0026 443*fb4d8502Sjsg #define ixPCIE_LC_STATE1 0x00A6 444*fb4d8502Sjsg #define ixPCIE_LC_STATE11 0x0027 445*fb4d8502Sjsg #define ixPCIE_LC_STATE2 0x00A7 446*fb4d8502Sjsg #define ixPCIE_LC_STATE3 0x00A8 447*fb4d8502Sjsg #define ixPCIE_LC_STATE4 0x00A9 448*fb4d8502Sjsg #define ixPCIE_LC_STATE5 0x00AA 449*fb4d8502Sjsg #define ixPCIE_LC_STATE6 0x0022 450*fb4d8502Sjsg #define ixPCIE_LC_STATE7 0x0023 451*fb4d8502Sjsg #define ixPCIE_LC_STATE8 0x0024 452*fb4d8502Sjsg #define ixPCIE_LC_STATE9 0x0025 453*fb4d8502Sjsg #define ixPCIE_LC_STATUS1 0x0028 454*fb4d8502Sjsg #define ixPCIE_LC_STATUS2 0x0029 455*fb4d8502Sjsg #define ixPCIE_LC_TRAINING_CNTL 0x00A1 456*fb4d8502Sjsg #define ixPCIE_P_BUF_STATUS 0x0041 457*fb4d8502Sjsg #define ixPCIE_P_CNTL 0x0040 458*fb4d8502Sjsg #define ixPCIE_P_DECODER_STATUS 0x0042 459*fb4d8502Sjsg #define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x0093 460*fb4d8502Sjsg #define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x0094 461*fb4d8502Sjsg #define ixPCIE_PERF_CNTL_MST_C_CLK 0x0087 462*fb4d8502Sjsg #define ixPCIE_PERF_CNTL_MST_R_CLK 0x0084 463*fb4d8502Sjsg #define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x0090 464*fb4d8502Sjsg #define ixPCIE_PERF_CNTL_SLV_R_CLK 0x008A 465*fb4d8502Sjsg #define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x008D 466*fb4d8502Sjsg #define ixPCIE_PERF_CNTL_TXCLK 0x0081 467*fb4d8502Sjsg #define ixPCIE_PERF_CNTL_TXCLK2 0x0095 468*fb4d8502Sjsg #define ixPCIE_PERF_COUNT0_MST_C_CLK 0x0088 469*fb4d8502Sjsg #define ixPCIE_PERF_COUNT0_MST_R_CLK 0x0085 470*fb4d8502Sjsg #define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x0091 471*fb4d8502Sjsg #define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x008B 472*fb4d8502Sjsg #define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x008E 473*fb4d8502Sjsg #define ixPCIE_PERF_COUNT0_TXCLK 0x0082 474*fb4d8502Sjsg #define ixPCIE_PERF_COUNT0_TXCLK2 0x0096 475*fb4d8502Sjsg #define ixPCIE_PERF_COUNT1_MST_C_CLK 0x0089 476*fb4d8502Sjsg #define ixPCIE_PERF_COUNT1_MST_R_CLK 0x0086 477*fb4d8502Sjsg #define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x0092 478*fb4d8502Sjsg #define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x008C 479*fb4d8502Sjsg #define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x008F 480*fb4d8502Sjsg #define ixPCIE_PERF_COUNT1_TXCLK 0x0083 481*fb4d8502Sjsg #define ixPCIE_PERF_COUNT1_TXCLK2 0x0097 482*fb4d8502Sjsg #define ixPCIE_PERF_COUNT_CNTL 0x0080 483*fb4d8502Sjsg #define ixPCIEP_HW_DEBUG 0x0002 484*fb4d8502Sjsg #define ixPCIE_P_MISC_STATUS 0x0043 485*fb4d8502Sjsg #define ixPCIEP_PORT_CNTL 0x0010 486*fb4d8502Sjsg #define ixPCIE_P_PORT_LANE_STATUS 0x0050 487*fb4d8502Sjsg #define ixPCIE_PRBS_CLR 0x00C8 488*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_0 0x00D0 489*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_10 0x00DA 490*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_1 0x00D1 491*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_11 0x00DB 492*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_12 0x00DC 493*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_13 0x00DD 494*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_14 0x00DE 495*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_15 0x00DF 496*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_2 0x00D2 497*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_3 0x00D3 498*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_4 0x00D4 499*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_5 0x00D5 500*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_6 0x00D6 501*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_7 0x00D7 502*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_8 0x00D8 503*fb4d8502Sjsg #define ixPCIE_PRBS_ERRCNT_9 0x00D9 504*fb4d8502Sjsg #define ixPCIE_PRBS_FREERUN 0x00CB 505*fb4d8502Sjsg #define ixPCIE_PRBS_HI_BITCNT 0x00CF 506*fb4d8502Sjsg #define ixPCIE_PRBS_LO_BITCNT 0x00CE 507*fb4d8502Sjsg #define ixPCIE_PRBS_MISC 0x00CC 508*fb4d8502Sjsg #define ixPCIE_PRBS_STATUS1 0x00C9 509*fb4d8502Sjsg #define ixPCIE_PRBS_STATUS2 0x00CA 510*fb4d8502Sjsg #define ixPCIE_PRBS_USER_PATTERN 0x00CD 511*fb4d8502Sjsg #define ixPCIE_P_RCV_L0S_FTS_DET 0x0050 512*fb4d8502Sjsg #define ixPCIEP_RESERVED 0x0000 513*fb4d8502Sjsg #define ixPCIEP_SCRATCH 0x0001 514*fb4d8502Sjsg #define ixPCIEP_STRAP_LC 0x00C0 515*fb4d8502Sjsg #define ixPCIEP_STRAP_MISC 0x00C1 516*fb4d8502Sjsg #define ixPCIE_RESERVED 0x0000 517*fb4d8502Sjsg #define ixPCIE_RX_CNTL 0x0070 518*fb4d8502Sjsg #define ixPCIE_RX_CNTL2 0x001D 519*fb4d8502Sjsg #define ixPCIE_RX_CNTL3 0x0074 520*fb4d8502Sjsg #define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x0082 521*fb4d8502Sjsg #define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x0081 522*fb4d8502Sjsg #define ixPCIE_RX_CREDITS_ALLOCATED_P 0x0080 523*fb4d8502Sjsg #define ixPCIE_RX_EXPECTED_SEQNUM 0x0071 524*fb4d8502Sjsg #define ixPCIE_RX_LAST_TLP0 0x0031 525*fb4d8502Sjsg #define ixPCIE_RX_LAST_TLP1 0x0032 526*fb4d8502Sjsg #define ixPCIE_RX_LAST_TLP2 0x0033 527*fb4d8502Sjsg #define ixPCIE_RX_LAST_TLP3 0x0034 528*fb4d8502Sjsg #define ixPCIE_RX_NUM_NAK 0x000E 529*fb4d8502Sjsg #define ixPCIE_RX_NUM_NAK_GENERATED 0x000F 530*fb4d8502Sjsg #define ixPCIE_RX_VENDOR_SPECIFIC 0x0072 531*fb4d8502Sjsg #define ixPCIE_SCRATCH 0x0001 532*fb4d8502Sjsg #define ixPCIE_STRAP_F0 0x00B0 533*fb4d8502Sjsg #define ixPCIE_STRAP_F1 0x00B1 534*fb4d8502Sjsg #define ixPCIE_STRAP_F2 0x00B2 535*fb4d8502Sjsg #define ixPCIE_STRAP_F3 0x00B3 536*fb4d8502Sjsg #define ixPCIE_STRAP_F4 0x00B4 537*fb4d8502Sjsg #define ixPCIE_STRAP_F5 0x00B5 538*fb4d8502Sjsg #define ixPCIE_STRAP_F6 0x00B6 539*fb4d8502Sjsg #define ixPCIE_STRAP_F7 0x00B7 540*fb4d8502Sjsg #define ixPCIE_STRAP_I2C_BD 0x00C4 541*fb4d8502Sjsg #define ixPCIE_STRAP_MISC 0x00C0 542*fb4d8502Sjsg #define ixPCIE_STRAP_MISC2 0x00C1 543*fb4d8502Sjsg #define ixPCIE_STRAP_PI 0x00C2 544*fb4d8502Sjsg #define ixPCIE_TX_ACK_LATENCY_LIMIT 0x0026 545*fb4d8502Sjsg #define ixPCIE_TX_CNTL 0x0020 546*fb4d8502Sjsg #define ixPCIE_TX_CREDITS_ADVT_CPL 0x0032 547*fb4d8502Sjsg #define ixPCIE_TX_CREDITS_ADVT_NP 0x0031 548*fb4d8502Sjsg #define ixPCIE_TX_CREDITS_ADVT_P 0x0030 549*fb4d8502Sjsg #define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x0037 550*fb4d8502Sjsg #define ixPCIE_TX_CREDITS_INIT_CPL 0x0035 551*fb4d8502Sjsg #define ixPCIE_TX_CREDITS_INIT_NP 0x0034 552*fb4d8502Sjsg #define ixPCIE_TX_CREDITS_INIT_P 0x0033 553*fb4d8502Sjsg #define ixPCIE_TX_CREDITS_STATUS 0x0036 554*fb4d8502Sjsg #define ixPCIE_TX_LAST_TLP0 0x0035 555*fb4d8502Sjsg #define ixPCIE_TX_LAST_TLP1 0x0036 556*fb4d8502Sjsg #define ixPCIE_TX_LAST_TLP2 0x0037 557*fb4d8502Sjsg #define ixPCIE_TX_LAST_TLP3 0x0038 558*fb4d8502Sjsg #define ixPCIE_TX_REPLAY 0x0025 559*fb4d8502Sjsg #define ixPCIE_TX_REQUESTER_ID 0x0021 560*fb4d8502Sjsg #define ixPCIE_TX_REQUEST_NUM_CNTL 0x0023 561*fb4d8502Sjsg #define ixPCIE_TX_SEQ 0x0024 562*fb4d8502Sjsg #define ixPCIE_TX_VENDOR_SPECIFIC 0x0022 563*fb4d8502Sjsg #define ixPCIE_WPR_CNTL 0x0030 564*fb4d8502Sjsg #define mmBACO_CNTL 0x14E5 565*fb4d8502Sjsg #define mmBF_ANA_ISO_CNTL 0x14C7 566*fb4d8502Sjsg #define mmBIF_BACO_DEBUG 0x14DF 567*fb4d8502Sjsg #define mmBIF_BACO_DEBUG_LATCH 0x14DC 568*fb4d8502Sjsg #define mmBIF_BACO_MSIC 0x14DE 569*fb4d8502Sjsg #define mmBIF_BUSNUM_CNTL1 0x1525 570*fb4d8502Sjsg #define mmBIF_BUSNUM_CNTL2 0x152B 571*fb4d8502Sjsg #define mmBIF_BUSNUM_LIST0 0x1526 572*fb4d8502Sjsg #define mmBIF_BUSNUM_LIST1 0x1527 573*fb4d8502Sjsg #define mmBIF_BUSY_DELAY_CNTR 0x1529 574*fb4d8502Sjsg #define mmBIF_CLK_PDWN_DELAY_TIMER 0x151F 575*fb4d8502Sjsg #define mmBIF_DEBUG_CNTL 0x151C 576*fb4d8502Sjsg #define mmBIF_DEBUG_MUX 0x151D 577*fb4d8502Sjsg #define mmBIF_DEBUG_OUT 0x151E 578*fb4d8502Sjsg #define mmBIF_DEVFUNCNUM_LIST0 0x14E8 579*fb4d8502Sjsg #define mmBIF_DEVFUNCNUM_LIST1 0x14E7 580*fb4d8502Sjsg #define mmBIF_FB_EN 0x1524 581*fb4d8502Sjsg #define mmBIF_FEATURES_CONTROL_MISC 0x14C2 582*fb4d8502Sjsg #define mmBIF_PERFCOUNTER0_RESULT 0x152D 583*fb4d8502Sjsg #define mmBIF_PERFCOUNTER1_RESULT 0x152E 584*fb4d8502Sjsg #define mmBIF_PERFMON_CNTL 0x152C 585*fb4d8502Sjsg #define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x152F 586*fb4d8502Sjsg #define mmBIF_RESET_EN 0x1511 587*fb4d8502Sjsg #define mmBIF_SCRATCH0 0x150E 588*fb4d8502Sjsg #define mmBIF_SCRATCH1 0x150F 589*fb4d8502Sjsg #define mmBIF_SSA_DISP_LOWER 0x14D2 590*fb4d8502Sjsg #define mmBIF_SSA_DISP_UPPER 0x14D3 591*fb4d8502Sjsg #define mmBIF_SSA_GFX0_LOWER 0x14CA 592*fb4d8502Sjsg #define mmBIF_SSA_GFX0_UPPER 0x14CB 593*fb4d8502Sjsg #define mmBIF_SSA_GFX1_LOWER 0x14CC 594*fb4d8502Sjsg #define mmBIF_SSA_GFX1_UPPER 0x14CD 595*fb4d8502Sjsg #define mmBIF_SSA_GFX2_LOWER 0x14CE 596*fb4d8502Sjsg #define mmBIF_SSA_GFX2_UPPER 0x14CF 597*fb4d8502Sjsg #define mmBIF_SSA_GFX3_LOWER 0x14D0 598*fb4d8502Sjsg #define mmBIF_SSA_GFX3_UPPER 0x14D1 599*fb4d8502Sjsg #define mmBIF_SSA_MC_LOWER 0x14D4 600*fb4d8502Sjsg #define mmBIF_SSA_MC_UPPER 0x14D5 601*fb4d8502Sjsg #define mmBIF_SSA_PWR_STATUS 0x14C8 602*fb4d8502Sjsg #define mmBIF_XDMA_HI 0x14C1 603*fb4d8502Sjsg #define mmBIF_XDMA_LO 0x14C0 604*fb4d8502Sjsg #define mmBIOS_SCRATCH_0 0x05C9 605*fb4d8502Sjsg #define mmBIOS_SCRATCH_10 0x05D3 606*fb4d8502Sjsg #define mmBIOS_SCRATCH_1 0x05CA 607*fb4d8502Sjsg #define mmBIOS_SCRATCH_11 0x05D4 608*fb4d8502Sjsg #define mmBIOS_SCRATCH_12 0x05D5 609*fb4d8502Sjsg #define mmBIOS_SCRATCH_13 0x05D6 610*fb4d8502Sjsg #define mmBIOS_SCRATCH_14 0x05D7 611*fb4d8502Sjsg #define mmBIOS_SCRATCH_15 0x05D8 612*fb4d8502Sjsg #define mmBIOS_SCRATCH_2 0x05CB 613*fb4d8502Sjsg #define mmBIOS_SCRATCH_3 0x05CC 614*fb4d8502Sjsg #define mmBIOS_SCRATCH_4 0x05CD 615*fb4d8502Sjsg #define mmBIOS_SCRATCH_5 0x05CE 616*fb4d8502Sjsg #define mmBIOS_SCRATCH_6 0x05CF 617*fb4d8502Sjsg #define mmBIOS_SCRATCH_7 0x05D0 618*fb4d8502Sjsg #define mmBIOS_SCRATCH_8 0x05D1 619*fb4d8502Sjsg #define mmBIOS_SCRATCH_9 0x05D2 620*fb4d8502Sjsg #define mmBUS_CNTL 0x1508 621*fb4d8502Sjsg #define mmCAPTURE_HOST_BUSNUM 0x153C 622*fb4d8502Sjsg #define mmCLKREQB_PAD_CNTL 0x1521 623*fb4d8502Sjsg #define mmCONFIG_APER_SIZE 0x150C 624*fb4d8502Sjsg #define mmCONFIG_CNTL 0x1509 625*fb4d8502Sjsg #define mmCONFIG_F0_BASE 0x150B 626*fb4d8502Sjsg #define mmCONFIG_MEMSIZE 0x150A 627*fb4d8502Sjsg #define mmCONFIG_REG_APER_SIZE 0x150D 628*fb4d8502Sjsg #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 629*fb4d8502Sjsg #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 630*fb4d8502Sjsg #define mmHOST_BUSNUM 0x153D 631*fb4d8502Sjsg #define mmHW_DEBUG 0x1515 632*fb4d8502Sjsg #define mmIMPCTL_RESET 0x14F5 633*fb4d8502Sjsg #define mmINTERRUPT_CNTL 0x151A 634*fb4d8502Sjsg #define mmINTERRUPT_CNTL2 0x151B 635*fb4d8502Sjsg #define mmMASTER_CREDIT_CNTL 0x1516 636*fb4d8502Sjsg #define mmMM_CFGREGS_CNTL 0x1513 637*fb4d8502Sjsg #define mmMM_DATA 0x0001 638*fb4d8502Sjsg #define mmMM_INDEX 0x0000 639*fb4d8502Sjsg #define mmMM_INDEX_HI 0x0006 640*fb4d8502Sjsg #define mmNEW_REFCLKB_TIMER 0x14EA 641*fb4d8502Sjsg #define mmNEW_REFCLKB_TIMER_1 0x14E9 642*fb4d8502Sjsg #define mmPCIE_DATA 0x000D 643*fb4d8502Sjsg #define mmPCIE_INDEX 0x000C 644*fb4d8502Sjsg #define mmPEER0_FB_OFFSET_HI 0x14F3 645*fb4d8502Sjsg #define mmPEER0_FB_OFFSET_LO 0x14F2 646*fb4d8502Sjsg #define mmPEER1_FB_OFFSET_HI 0x14F1 647*fb4d8502Sjsg #define mmPEER1_FB_OFFSET_LO 0x14F0 648*fb4d8502Sjsg #define mmPEER2_FB_OFFSET_HI 0x14EF 649*fb4d8502Sjsg #define mmPEER2_FB_OFFSET_LO 0x14EE 650*fb4d8502Sjsg #define mmPEER3_FB_OFFSET_HI 0x14ED 651*fb4d8502Sjsg #define mmPEER3_FB_OFFSET_LO 0x14EC 652*fb4d8502Sjsg #define mmPEER_REG_RANGE0 0x153E 653*fb4d8502Sjsg #define mmPEER_REG_RANGE1 0x153F 654*fb4d8502Sjsg #define mmSLAVE_HANG_ERROR 0x153B 655*fb4d8502Sjsg #define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 656*fb4d8502Sjsg #define mmSLAVE_REQ_CREDIT_CNTL 0x1517 657*fb4d8502Sjsg #define mmSMBCLK_PAD_CNTL 0x1523 658*fb4d8502Sjsg #define mmSMBDAT_PAD_CNTL 0x1522 659*fb4d8502Sjsg #define mmSMBUS_BACO_DUMMY 0x14C6 660*fb4d8502Sjsg 661*fb4d8502Sjsg #endif 662