1c349dbc7Sjsg /* 2c349dbc7Sjsg * Copyright (C) 2018 Advanced Micro Devices, Inc. 3c349dbc7Sjsg * 4c349dbc7Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5c349dbc7Sjsg * copy of this software and associated documentation files (the "Software"), 6c349dbc7Sjsg * to deal in the Software without restriction, including without limitation 7c349dbc7Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c349dbc7Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9c349dbc7Sjsg * Software is furnished to do so, subject to the following conditions: 10c349dbc7Sjsg * 11c349dbc7Sjsg * The above copyright notice and this permission notice shall be included 12c349dbc7Sjsg * in all copies or substantial portions of the Software. 13c349dbc7Sjsg * 14c349dbc7Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15c349dbc7Sjsg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c349dbc7Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c349dbc7Sjsg * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18c349dbc7Sjsg * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19c349dbc7Sjsg * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20c349dbc7Sjsg */ 21c349dbc7Sjsg #ifndef _nbio_7_4_OFFSET_HEADER 22c349dbc7Sjsg #define _nbio_7_4_OFFSET_HEADER 23c349dbc7Sjsg 24c349dbc7Sjsg 25c349dbc7Sjsg 26c349dbc7Sjsg // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp 27c349dbc7Sjsg // base address: 0x0 28c349dbc7Sjsg #define cfgPSWUSCFG0_VENDOR_ID 0x0000 29c349dbc7Sjsg #define cfgPSWUSCFG0_DEVICE_ID 0x0002 30c349dbc7Sjsg #define cfgPSWUSCFG0_COMMAND 0x0004 31c349dbc7Sjsg #define cfgPSWUSCFG0_STATUS 0x0006 32c349dbc7Sjsg #define cfgPSWUSCFG0_REVISION_ID 0x0008 33c349dbc7Sjsg #define cfgPSWUSCFG0_PROG_INTERFACE 0x0009 34c349dbc7Sjsg #define cfgPSWUSCFG0_SUB_CLASS 0x000a 35c349dbc7Sjsg #define cfgPSWUSCFG0_BASE_CLASS 0x000b 36c349dbc7Sjsg #define cfgPSWUSCFG0_CACHE_LINE 0x000c 37c349dbc7Sjsg #define cfgPSWUSCFG0_LATENCY 0x000d 38c349dbc7Sjsg #define cfgPSWUSCFG0_HEADER 0x000e 39c349dbc7Sjsg #define cfgPSWUSCFG0_BIST 0x000f 40c349dbc7Sjsg #define cfgPSWUSCFG0_SUB_BUS_NUMBER_LATENCY 0x0018 41c349dbc7Sjsg #define cfgPSWUSCFG0_IO_BASE_LIMIT 0x001c 42c349dbc7Sjsg #define cfgPSWUSCFG0_SECONDARY_STATUS 0x001e 43c349dbc7Sjsg #define cfgPSWUSCFG0_MEM_BASE_LIMIT 0x0020 44c349dbc7Sjsg #define cfgPSWUSCFG0_PREF_BASE_LIMIT 0x0024 45c349dbc7Sjsg #define cfgPSWUSCFG0_PREF_BASE_UPPER 0x0028 46c349dbc7Sjsg #define cfgPSWUSCFG0_PREF_LIMIT_UPPER 0x002c 47c349dbc7Sjsg #define cfgPSWUSCFG0_IO_BASE_LIMIT_HI 0x0030 48c349dbc7Sjsg #define cfgPSWUSCFG0_CAP_PTR 0x0034 49c349dbc7Sjsg #define cfgPSWUSCFG0_INTERRUPT_LINE 0x003c 50c349dbc7Sjsg #define cfgPSWUSCFG0_INTERRUPT_PIN 0x003d 51c349dbc7Sjsg #define cfgPSWUSCFG0_IRQ_BRIDGE_CNTL 0x003e 52c349dbc7Sjsg #define cfgEXT_BRIDGE_CNTL 0x0040 53c349dbc7Sjsg #define cfgPSWUSCFG0_VENDOR_CAP_LIST 0x0048 54c349dbc7Sjsg #define cfgPSWUSCFG0_ADAPTER_ID_W 0x004c 55c349dbc7Sjsg #define cfgPSWUSCFG0_PMI_CAP_LIST 0x0050 56c349dbc7Sjsg #define cfgPSWUSCFG0_PMI_CAP 0x0052 57c349dbc7Sjsg #define cfgPSWUSCFG0_PMI_STATUS_CNTL 0x0054 58c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_CAP_LIST 0x0058 59c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_CAP 0x005a 60c349dbc7Sjsg #define cfgPSWUSCFG0_DEVICE_CAP 0x005c 61c349dbc7Sjsg #define cfgPSWUSCFG0_DEVICE_CNTL 0x0060 62c349dbc7Sjsg #define cfgPSWUSCFG0_DEVICE_STATUS 0x0062 63c349dbc7Sjsg #define cfgPSWUSCFG0_LINK_CAP 0x0064 64c349dbc7Sjsg #define cfgPSWUSCFG0_LINK_CNTL 0x0068 65c349dbc7Sjsg #define cfgPSWUSCFG0_LINK_STATUS 0x006a 66c349dbc7Sjsg #define cfgPSWUSCFG0_DEVICE_CAP2 0x007c 67c349dbc7Sjsg #define cfgPSWUSCFG0_DEVICE_CNTL2 0x0080 68c349dbc7Sjsg #define cfgPSWUSCFG0_DEVICE_STATUS2 0x0082 69c349dbc7Sjsg #define cfgPSWUSCFG0_LINK_CAP2 0x0084 70c349dbc7Sjsg #define cfgPSWUSCFG0_LINK_CNTL2 0x0088 71c349dbc7Sjsg #define cfgPSWUSCFG0_LINK_STATUS2 0x008a 72c349dbc7Sjsg #define cfgPSWUSCFG0_MSI_CAP_LIST 0x00a0 73c349dbc7Sjsg #define cfgPSWUSCFG0_MSI_MSG_CNTL 0x00a2 74c349dbc7Sjsg #define cfgPSWUSCFG0_MSI_MSG_ADDR_LO 0x00a4 75c349dbc7Sjsg #define cfgPSWUSCFG0_MSI_MSG_ADDR_HI 0x00a8 76c349dbc7Sjsg #define cfgPSWUSCFG0_MSI_MSG_DATA 0x00a8 77c349dbc7Sjsg #define cfgPSWUSCFG0_MSI_MSG_DATA_64 0x00ac 78c349dbc7Sjsg #define cfgPSWUSCFG0_SSID_CAP_LIST 0x00c0 79c349dbc7Sjsg #define cfgPSWUSCFG0_SSID_CAP 0x00c4 80c349dbc7Sjsg #define cfgMSI_MAP_CAP_LIST 0x00c8 81c349dbc7Sjsg #define cfgMSI_MAP_CAP 0x00ca 82c349dbc7Sjsg #define cfgMSI_MAP_ADDR_LO 0x00cc 83c349dbc7Sjsg #define cfgMSI_MAP_ADDR_HI 0x00d0 84c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 85c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 86c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC1 0x0108 87c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC2 0x010c 88c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_VC_ENH_CAP_LIST 0x0110 89c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG1 0x0114 90c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG2 0x0118 91c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_PORT_VC_CNTL 0x011c 92c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_PORT_VC_STATUS 0x011e 93c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CAP 0x0120 94c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CNTL 0x0124 95c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_STATUS 0x012a 96c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CAP 0x012c 97c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CNTL 0x0130 98c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_STATUS 0x0136 99c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 100c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 101c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 102c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 103c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_STATUS 0x0154 104c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_MASK 0x0158 105c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY 0x015c 106c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_CORR_ERR_STATUS 0x0160 107c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_CORR_ERR_MASK 0x0164 108c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL 0x0168 109c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_HDR_LOG0 0x016c 110c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_HDR_LOG1 0x0170 111c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_HDR_LOG2 0x0174 112c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_HDR_LOG3 0x0178 113c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG0 0x0188 114c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG1 0x018c 115c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG2 0x0190 116c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG3 0x0194 117c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 118c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LINK_CNTL3 0x0274 119c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_ERROR_STATUS 0x0278 120c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 121c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 122c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 123c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 124c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 125c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 126c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 127c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 128c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 129c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 130c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 131c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 132c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 133c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 134c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 135c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 136c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_ACS_ENH_CAP_LIST 0x02a0 137c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_ACS_CAP 0x02a4 138c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_ACS_CNTL 0x02a6 139c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_MC_ENH_CAP_LIST 0x02f0 140c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_MC_CAP 0x02f4 141c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_MC_CNTL 0x02f6 142c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_MC_ADDR0 0x02f8 143c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_MC_ADDR1 0x02fc 144c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_MC_RCV0 0x0300 145c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_MC_RCV1 0x0304 146c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL0 0x0308 147c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL1 0x030c 148c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 149c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 150c349dbc7Sjsg #define cfgPCIE_MC_OVERLAY_BAR0 0x0318 151c349dbc7Sjsg #define cfgPCIE_MC_OVERLAY_BAR1 0x031c 152c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LTR_ENH_CAP_LIST 0x0320 153c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_LTR_CAP 0x0324 154c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_ARI_ENH_CAP_LIST 0x0328 155c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_ARI_CAP 0x032c 156c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_ARI_CNTL 0x032e 157c349dbc7Sjsg #define cfgPCIE_L1_PM_SUB_CAP_LIST 0x0370 158c349dbc7Sjsg #define cfgPCIE_L1_PM_SUB_CAP 0x0374 159c349dbc7Sjsg #define cfgPCIE_L1_PM_SUB_CNTL 0x0378 160c349dbc7Sjsg #define cfgPCIE_L1_PM_SUB_CNTL2 0x037c 161c349dbc7Sjsg #define cfgPCIE_ESM_CAP_LIST 0x03c4 162c349dbc7Sjsg #define cfgPCIE_ESM_HEADER_1 0x03c8 163c349dbc7Sjsg #define cfgPCIE_ESM_HEADER_2 0x03cc 164c349dbc7Sjsg #define cfgPCIE_ESM_STATUS 0x03ce 165c349dbc7Sjsg #define cfgPCIE_ESM_CTRL 0x03d0 166c349dbc7Sjsg #define cfgPCIE_ESM_CAP_1 0x03d4 167c349dbc7Sjsg #define cfgPCIE_ESM_CAP_2 0x03d8 168c349dbc7Sjsg #define cfgPCIE_ESM_CAP_3 0x03dc 169c349dbc7Sjsg #define cfgPCIE_ESM_CAP_4 0x03e0 170c349dbc7Sjsg #define cfgPCIE_ESM_CAP_5 0x03e4 171c349dbc7Sjsg #define cfgPCIE_ESM_CAP_6 0x03e8 172c349dbc7Sjsg #define cfgPCIE_ESM_CAP_7 0x03ec 173c349dbc7Sjsg #define cfgPSWUSCFG0_PCIE_DLF_ENH_CAP_LIST 0x0400 174c349dbc7Sjsg #define cfgPSWUSCFG0_DATA_LINK_FEATURE_CAP 0x0404 175c349dbc7Sjsg #define cfgPSWUSCFG0_DATA_LINK_FEATURE_STATUS 0x0408 176c349dbc7Sjsg #define cfgPCIE_PHY_16GT_ENH_CAP_LIST 0x0410 177c349dbc7Sjsg #define cfgPSWUSCFG0_LINK_CAP_16GT 0x0414 178c349dbc7Sjsg #define cfgPSWUSCFG0_LINK_CNTL_16GT 0x0418 179c349dbc7Sjsg #define cfgPSWUSCFG0_LINK_STATUS_16GT 0x041c 180c349dbc7Sjsg #define cfgPSWUSCFG0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 181c349dbc7Sjsg #define cfgPSWUSCFG0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 182c349dbc7Sjsg #define cfgPSWUSCFG0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 183c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 184c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 185c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 186c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 187c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 188c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 189c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 190c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 191c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 192c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 193c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 194c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 195c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 196c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 197c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 198c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 199c349dbc7Sjsg #define cfgPCIE_MARGINING_ENH_CAP_LIST 0x0440 200c349dbc7Sjsg #define cfgPSWUSCFG0_MARGINING_PORT_CAP 0x0444 201c349dbc7Sjsg #define cfgPSWUSCFG0_MARGINING_PORT_STATUS 0x0446 202c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_0_MARGINING_LANE_CNTL 0x0448 203c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_0_MARGINING_LANE_STATUS 0x044a 204c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_1_MARGINING_LANE_CNTL 0x044c 205c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_1_MARGINING_LANE_STATUS 0x044e 206c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_2_MARGINING_LANE_CNTL 0x0450 207c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_2_MARGINING_LANE_STATUS 0x0452 208c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_3_MARGINING_LANE_CNTL 0x0454 209c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_3_MARGINING_LANE_STATUS 0x0456 210c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_4_MARGINING_LANE_CNTL 0x0458 211c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_4_MARGINING_LANE_STATUS 0x045a 212c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_5_MARGINING_LANE_CNTL 0x045c 213c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_5_MARGINING_LANE_STATUS 0x045e 214c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_6_MARGINING_LANE_CNTL 0x0460 215c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_6_MARGINING_LANE_STATUS 0x0462 216c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_7_MARGINING_LANE_CNTL 0x0464 217c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_7_MARGINING_LANE_STATUS 0x0466 218c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_8_MARGINING_LANE_CNTL 0x0468 219c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_8_MARGINING_LANE_STATUS 0x046a 220c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_9_MARGINING_LANE_CNTL 0x046c 221c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_9_MARGINING_LANE_STATUS 0x046e 222c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_10_MARGINING_LANE_CNTL 0x0470 223c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_10_MARGINING_LANE_STATUS 0x0472 224c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_11_MARGINING_LANE_CNTL 0x0474 225c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_11_MARGINING_LANE_STATUS 0x0476 226c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_12_MARGINING_LANE_CNTL 0x0478 227c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_12_MARGINING_LANE_STATUS 0x047a 228c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_13_MARGINING_LANE_CNTL 0x047c 229c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_13_MARGINING_LANE_STATUS 0x047e 230c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_14_MARGINING_LANE_CNTL 0x0480 231c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_14_MARGINING_LANE_STATUS 0x0482 232c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_15_MARGINING_LANE_CNTL 0x0484 233c349dbc7Sjsg #define cfgPSWUSCFG0_LANE_15_MARGINING_LANE_STATUS 0x0486 234c349dbc7Sjsg 235c349dbc7Sjsg 236c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp 237c349dbc7Sjsg // base address: 0x0 238c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x0000 239c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x0002 240c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_COMMAND 0x0004 241c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_STATUS 0x0006 242c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x0008 243c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x0009 244c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x000a 245c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x000b 246c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x000c 247c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LATENCY 0x000d 248c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_HEADER 0x000e 249c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_BIST 0x000f 250c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x0010 251c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x0014 252c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x0018 253c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x001c 254c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x0020 255c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x0024 256c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x002c 257c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x0030 258c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x0034 259c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x003c 260c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x003d 261c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x003e 262c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x003f 263c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x0048 264c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x004c 265c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x0050 266c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x0052 267c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x0054 268c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x0064 269c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x0066 270c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x0068 271c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x006c 272c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x006e 273c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x0070 274c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x0074 275c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x0076 276c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x0088 277c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x008c 278c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x008e 279c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x0090 280c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x0094 281c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x0096 282c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CAP2 0x0098 283c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CNTL2 0x009c 284c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_STATUS2 0x009e 285c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x00a0 286c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x00a2 287c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x00a4 288c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x00a8 289c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x00a8 290c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x00ac 291c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x00ac 292c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x00b0 293c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x00b0 294c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x00b4 295c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x00c0 296c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x00c2 297c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x00c4 298c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x00c8 299c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 300c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 301c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 302c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x010c 303c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x0110 304c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x0114 305c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x0118 306c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x011c 307c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x011e 308c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x0120 309c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 310c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x012a 311c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x012c 312c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 313c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 314c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 315c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 316c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 317c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 318c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 319c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x0158 320c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 321c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x0160 322c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x0164 323c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 324c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x016c 325c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x0170 326c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x0174 327c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x0178 328c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 329c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x018c 330c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 331c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 332c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x0200 333c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x0204 334c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x0208 335c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x020c 336c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x0210 337c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x0214 338c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x0218 339c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x021c 340c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x0220 341c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x0224 342c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x0228 343c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x022c 344c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x0230 345c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 346c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 347c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x0248 348c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x024c 349c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x0250 350c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x0254 351c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 352c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x025c 353c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x025e 354c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 355c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 356c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 357c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 358c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 359c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 360c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 361c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 362c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 363c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x0274 364c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x0278 365c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 366c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 367c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 368c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 369c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 370c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 371c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 372c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 373c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 374c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 375c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 376c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 377c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 378c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 379c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 380c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 381c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 382c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x02a4 383c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x02a6 384c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 385c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x02b4 386c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x02b6 387c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 388c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x02c4 389c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x02c6 390c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 391c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc 392c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 393c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x02d4 394c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x02d6 395c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x02f0 396c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x02f4 397c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x02f6 398c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x02f8 399c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x02fc 400c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x0300 401c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x0304 402c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x0308 403c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x030c 404c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 405c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 406c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x0320 407c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x0324 408c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 409c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x032c 410c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x032e 411c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 412c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x0334 413c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x0338 414c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x033a 415c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x033c 416c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x033e 417c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x0340 418c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 419c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 420c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x0346 421c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a 422c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 423c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 424c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 425c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 426c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 427c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 428c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 429c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 430c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 431c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370 432c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP 0x0374 433c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL 0x0378 434c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x0400 435c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0x0404 436c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0x0408 437c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PHY_16GT_ENH_CAP_LIST 0x0410 438c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0x0414 439c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0x0418 440c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0x041c 441c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 442c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 443c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 444c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 445c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 446c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 447c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 448c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 449c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 450c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 451c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 452c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 453c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 454c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 455c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 456c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 457c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 458c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 459c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 460c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_ENH_CAP_LIST 0x0440 461c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0x0444 462c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0x0446 463c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x0448 464c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x044a 465c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x044c 466c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x044e 467c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x0450 468c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x0452 469c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x0454 470c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x0456 471c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x0458 472c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x045a 473c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x045c 474c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x045e 475c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x0460 476c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x0462 477c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x0464 478c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x0466 479c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x0468 480c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x046a 481c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x046c 482c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x046e 483c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x0470 484c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x0472 485c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x0474 486c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x0476 487c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x0478 488c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x047a 489c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x047c 490c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x047e 491c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x0480 492c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x0482 493c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x0484 494c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x0486 495c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 496c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 497c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 498c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc 499c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 500c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 501c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 502c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc 503c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 504c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 505c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 506c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec 507c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 508c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0500 509c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0504 510c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0508 511c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x050c 512c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0510 513c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0514 514c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0518 515c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x051c 516c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0520 517c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0524 518c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0528 519c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x052c 520c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x0530 521c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0534 522c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0538 523c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x053c 524c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0540 525c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0544 526c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0548 527c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x054c 528c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0550 529c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0554 530c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0558 531c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x055c 532c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0560 533c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0564 534c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0568 535c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x056c 536c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0570 537c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0574 538c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x0578 539c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x057c 540c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0580 541c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0584 542c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x0588 543c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x058c 544c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0590 545c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0594 546c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x0598 547c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x059c 548c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x05a0 549c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x05a4 550c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x05a8 551c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x05ac 552c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x05b0 553c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x05b4 554c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x05b8 555c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x05bc 556c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x05c0 557c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x05c4 558c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x05c8 559c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x05cc 560c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x05d0 561c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x05e0 562c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x05e4 563c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x05e8 564c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x05ec 565c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x05f0 566c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x05f4 567c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x05f8 568c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x05fc 569c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x0600 570c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x0610 571c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x0614 572c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x0618 573c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x061c 574c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x0620 575c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x0624 576c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x0628 577c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x062c 578c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x0630 579c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x0640 580c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x0644 581c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x0648 582c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x064c 583c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x0650 584c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x0654 585c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x0658 586c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x065c 587c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x0660 588c349dbc7Sjsg 589c349dbc7Sjsg 590c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp 591c349dbc7Sjsg // base address: 0x0 592c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x0000 593c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x0002 594c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0x0004 595c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0x0006 596c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x0008 597c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x0009 598c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x000a 599c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x000b 600c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x000c 601c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0x000d 602c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0x000e 603c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_BIST 0x000f 604c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x0010 605c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x0014 606c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x0018 607c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x001c 608c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x0020 609c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x0024 610c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x002c 611c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x0030 612c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x0034 613c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x003c 614c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x003d 615c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x003e 616c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x003f 617c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x0048 618c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x004c 619c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x0050 620c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x0052 621c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x0054 622c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x0064 623c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x0066 624c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x0068 625c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x006c 626c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x006e 627c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x0070 628c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x0074 629c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x0076 630c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x0088 631c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x008c 632c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x008e 633c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x0090 634c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x0094 635c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x0096 636c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2 0x0098 637c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2 0x009c 638c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2 0x009e 639c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x00a0 640c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x00a2 641c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x00a4 642c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x00a8 643c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x00a8 644c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x00ac 645c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x00ac 646c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x00b0 647c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x00b0 648c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x00b4 649c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x00c0 650c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x00c2 651c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x00c4 652c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x00c8 653c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 654c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 655c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 656c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c 657c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 0x0110 658c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 0x0114 659c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 0x0118 660c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 0x011c 661c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 0x011e 662c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 0x0120 663c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 0x0124 664c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 0x012a 665c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 0x012c 666c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 0x0130 667c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 0x0136 668c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 669c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 670c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 671c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 672c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 673c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158 674c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 675c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160 676c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x0164 677c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 678c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x016c 679c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x0170 680c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x0174 681c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x0178 682c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 683c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c 684c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 685c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 686c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200 687c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x0204 688c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x0208 689c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x020c 690c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x0210 691c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x0214 692c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x0218 693c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x021c 694c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x0220 695c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x0224 696c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x0228 697c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x022c 698c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x0230 699c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 700c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 701c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248 702c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c 703c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250 704c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x0254 705c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 706c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x025c 707c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x025e 708c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 709c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 710c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 711c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 712c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 713c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 714c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 715c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 716c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 717c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0x0274 718c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0x0278 719c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 720c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 721c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 722c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 723c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 724c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 725c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 726c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 727c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 728c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 729c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 730c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 731c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 732c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 733c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 734c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 735c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 736c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x02a4 737c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x02a6 738c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 739c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0x02b4 740c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0x02b6 741c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 742c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0x02c4 743c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0x02c6 744c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 745c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc 746c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 747c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x02d4 748c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x02d6 749c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0x02f0 750c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0x02f4 751c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0x02f6 752c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0x02f8 753c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0x02fc 754c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0x0300 755c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0x0304 756c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0x0308 757c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0x030c 758c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 759c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 760c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0x0320 761c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0x0324 762c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 763c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x032c 764c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x032e 765c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 766c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0x0334 767c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0x0338 768c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0x033a 769c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0x033c 770c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0x033e 771c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0x0340 772c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 773c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 774c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0x0346 775c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a 776c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 777c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 778c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 779c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 780c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 781c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 782c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 783c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 784c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 785c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370 786c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 0x0374 787c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 0x0378 788c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST 0x0400 789c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP 0x0404 790c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS 0x0408 791c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PHY_16GT_ENH_CAP_LIST 0x0410 792c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT 0x0414 793c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT 0x0418 794c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT 0x041c 795c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 796c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 797c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 798c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 799c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 800c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 801c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 802c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 803c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 804c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 805c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 806c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 807c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 808c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 809c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 810c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 811c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 812c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 813c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 814c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_ENH_CAP_LIST 0x0440 815c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP 0x0444 816c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS 0x0446 817c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL 0x0448 818c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS 0x044a 819c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL 0x044c 820c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS 0x044e 821c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL 0x0450 822c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS 0x0452 823c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL 0x0454 824c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS 0x0456 825c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL 0x0458 826c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS 0x045a 827c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL 0x045c 828c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS 0x045e 829c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL 0x0460 830c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS 0x0462 831c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL 0x0464 832c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS 0x0466 833c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL 0x0468 834c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS 0x046a 835c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL 0x046c 836c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS 0x046e 837c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL 0x0470 838c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS 0x0472 839c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL 0x0474 840c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS 0x0476 841c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL 0x0478 842c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS 0x047a 843c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL 0x047c 844c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS 0x047e 845c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL 0x0480 846c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS 0x0482 847c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL 0x0484 848c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS 0x0486 849c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 850c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 851c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 852c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc 853c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 854c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 855c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 856c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc 857c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 858c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 859c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 860c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec 861c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 862c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0500 863c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0504 864c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0508 865c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x050c 866c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0510 867c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0514 868c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0518 869c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x051c 870c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0520 871c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0524 872c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0528 873c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x052c 874c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x0530 875c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0534 876c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0538 877c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x053c 878c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0540 879c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0544 880c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0548 881c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x054c 882c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0550 883c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0554 884c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0558 885c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x055c 886c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0560 887c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0564 888c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0568 889c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x056c 890c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0570 891c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0574 892c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x0578 893c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x057c 894c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0580 895c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0584 896c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x0588 897c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x058c 898c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0590 899c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0594 900c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x0598 901c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x059c 902c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x05a0 903c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x05a4 904c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x05a8 905c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x05ac 906c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x05b0 907c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x05b4 908c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x05b8 909c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x05bc 910c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x05c0 911c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x05c4 912c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x05c8 913c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x05cc 914c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x05d0 915c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x05e0 916c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x05e4 917c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x05e8 918c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x05ec 919c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x05f0 920c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x05f4 921c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x05f8 922c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x05fc 923c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x0600 924c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x0610 925c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x0614 926c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x0618 927c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x061c 928c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x0620 929c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x0624 930c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x0628 931c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x062c 932c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x0630 933c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x0640 934c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x0644 935c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x0648 936c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x064c 937c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x0650 938c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x0654 939c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x0658 940c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x065c 941c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x0660 942c349dbc7Sjsg 943c349dbc7Sjsg 944c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp 945c349dbc7Sjsg // base address: 0x0 946c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID 0x0000 947c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID 0x0002 948c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_COMMAND 0x0004 949c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_STATUS 0x0006 950c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID 0x0008 951c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE 0x0009 952c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS 0x000a 953c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS 0x000b 954c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE 0x000c 955c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LATENCY 0x000d 956c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_HEADER 0x000e 957c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_BIST 0x000f 958c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1 0x0010 959c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY 0x0018 960c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT 0x001c 961c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS 0x001e 962c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT 0x0020 963c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT 0x0024 964c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER 0x0028 965c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER 0x002c 966c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI 0x0030 967c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR 0x0034 968c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE 0x003c 969c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN 0x003d 970c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL 0x003e 971c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST 0x0050 972c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP 0x0052 973c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL 0x0054 974c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST 0x0058 975c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP 0x005a 976c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP 0x005c 977c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL 0x0060 978c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS 0x0062 979c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP 0x0064 980c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL 0x0068 981c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS 0x006a 982c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP 0x006c 983c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL 0x0070 984c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS 0x0072 985c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2 0x007c 986c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2 0x0080 987c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2 0x0082 988c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2 0x0084 989c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2 0x0088 990c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2 0x008a 991c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2 0x008c 992c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2 0x0090 993c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2 0x0092 994c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST 0x00a0 995c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL 0x00a2 996c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO 0x00a4 997c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI 0x00a8 998c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA 0x00a8 999c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64 0x00ac 1000c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST 0x00c0 1001c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP 0x00c4 1002c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1003c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1004c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1 0x0108 1005c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2 0x010c 1006c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST 0x0110 1007c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1 0x0114 1008c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2 0x0118 1009c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL 0x011c 1010c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS 0x011e 1011c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP 0x0120 1012c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL 0x0124 1013c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS 0x012a 1014c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP 0x012c 1015c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL 0x0130 1016c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS 0x0136 1017c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 1018c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 1019c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 1020c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1021c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS 0x0154 1022c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK 0x0158 1023c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1024c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS 0x0160 1025c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK 0x0164 1026c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1027c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0 0x016c 1028c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1 0x0170 1029c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2 0x0174 1030c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3 0x0178 1031c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0 0x0188 1032c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1 0x018c 1033c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2 0x0190 1034c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3 0x0194 1035c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 1036c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3 0x0274 1037c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS 0x0278 1038c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 1039c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 1040c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 1041c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 1042c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 1043c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 1044c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 1045c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 1046c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 1047c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 1048c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 1049c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 1050c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 1051c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 1052c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 1053c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 1054c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST 0x02a0 1055c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP 0x02a4 1056c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL 0x02a6 1057c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST 0x0400 1058c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP 0x0404 1059c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS 0x0408 1060c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_PHY_16GT_ENH_CAP_LIST 0x0410 1061c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_16GT 0x0414 1062c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT 0x0418 1063c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT 0x041c 1064c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 1065c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 1066c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 1067c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 1068c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 1069c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 1070c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 1071c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 1072c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 1073c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 1074c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 1075c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 1076c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 1077c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 1078c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 1079c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 1080c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 1081c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 1082c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 1083c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_ENH_CAP_LIST 0x0440 1084c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP 0x0444 1085c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS 0x0446 1086c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL 0x0448 1087c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS 0x044a 1088c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL 0x044c 1089c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS 0x044e 1090c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL 0x0450 1091c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS 0x0452 1092c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL 0x0454 1093c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS 0x0456 1094c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL 0x0458 1095c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS 0x045a 1096c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL 0x045c 1097c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS 0x045e 1098c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL 0x0460 1099c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS 0x0462 1100c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL 0x0464 1101c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS 0x0466 1102c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL 0x0468 1103c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS 0x046a 1104c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL 0x046c 1105c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS 0x046e 1106c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL 0x0470 1107c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS 0x0472 1108c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL 0x0474 1109c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS 0x0476 1110c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL 0x0478 1111c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS 0x047a 1112c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL 0x047c 1113c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS 0x047e 1114c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL 0x0480 1115c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS 0x0482 1116c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL 0x0484 1117c349dbc7Sjsg #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS 0x0486 1118c349dbc7Sjsg 1119c349dbc7Sjsg 1120c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp 1121c349dbc7Sjsg // base address: 0x0 1122c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID 0x0000 1123c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID 0x0002 1124c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND 0x0004 1125c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS 0x0006 1126c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID 0x0008 1127c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE 0x0009 1128c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS 0x000a 1129c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS 0x000b 1130c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE 0x000c 1131c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY 0x000d 1132c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER 0x000e 1133c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST 0x000f 1134c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 0x0010 1135c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 0x0014 1136c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 0x0018 1137c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 0x001c 1138c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 0x0020 1139c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 0x0024 1140c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID 0x002c 1141c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR 0x0030 1142c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR 0x0034 1143c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE 0x003c 1144c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN 0x003d 1145c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST 0x0064 1146c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP 0x0066 1147c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP 0x0068 1148c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL 0x006c 1149c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS 0x006e 1150c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP 0x0070 1151c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL 0x0074 1152c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS 0x0076 1153c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 0x0088 1154c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 0x008c 1155c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 0x008e 1156c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 0x0090 1157c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 0x0094 1158c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 0x0096 1159c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2 0x0098 1160c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2 0x009c 1161c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2 0x009e 1162c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST 0x00a0 1163c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL 0x00a2 1164c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO 0x00a4 1165c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI 0x00a8 1166c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA 0x00a8 1167c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK 0x00ac 1168c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 0x00ac 1169c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 0x00b0 1170c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING 0x00b0 1171c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 0x00b4 1172c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST 0x00c0 1173c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL 0x00c2 1174c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE 0x00c4 1175c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA 0x00c8 1176c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1177c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1178c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 1179c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 0x010c 1180c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1181c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 1182c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK 0x0158 1183c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1184c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS 0x0160 1185c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK 0x0164 1186c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1187c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 0x016c 1188c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 0x0170 1189c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 0x0174 1190c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 0x0178 1191c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 1192c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 0x018c 1193c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 1194c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 1195c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1196c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP 0x02b4 1197c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL 0x02b6 1198c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1199c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP 0x032c 1200c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL 0x032e 1201c349dbc7Sjsg 1202c349dbc7Sjsg 1203c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp 1204c349dbc7Sjsg // base address: 0x0 1205c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID 0x0000 1206c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID 0x0002 1207c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND 0x0004 1208c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS 0x0006 1209c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID 0x0008 1210c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE 0x0009 1211c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS 0x000a 1212c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS 0x000b 1213c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE 0x000c 1214c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY 0x000d 1215c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER 0x000e 1216c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST 0x000f 1217c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 0x0010 1218c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 0x0014 1219c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 0x0018 1220c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 0x001c 1221c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 0x0020 1222c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 0x0024 1223c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID 0x002c 1224c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR 0x0030 1225c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR 0x0034 1226c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE 0x003c 1227c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN 0x003d 1228c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST 0x0064 1229c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP 0x0066 1230c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP 0x0068 1231c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL 0x006c 1232c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS 0x006e 1233c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP 0x0070 1234c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL 0x0074 1235c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS 0x0076 1236c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 0x0088 1237c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 0x008c 1238c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 0x008e 1239c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 0x0090 1240c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 0x0094 1241c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 0x0096 1242c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2 0x0098 1243c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2 0x009c 1244c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2 0x009e 1245c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST 0x00a0 1246c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL 0x00a2 1247c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO 0x00a4 1248c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI 0x00a8 1249c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA 0x00a8 1250c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK 0x00ac 1251c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 0x00ac 1252c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 0x00b0 1253c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING 0x00b0 1254c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 0x00b4 1255c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST 0x00c0 1256c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL 0x00c2 1257c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE 0x00c4 1258c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA 0x00c8 1259c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1260c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1261c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 1262c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 0x010c 1263c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1264c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 1265c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK 0x0158 1266c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1267c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS 0x0160 1268c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK 0x0164 1269c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1270c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 0x016c 1271c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 0x0170 1272c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 0x0174 1273c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 0x0178 1274c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 1275c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 0x018c 1276c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 1277c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 1278c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1279c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP 0x02b4 1280c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL 0x02b6 1281c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1282c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP 0x032c 1283c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL 0x032e 1284c349dbc7Sjsg 1285c349dbc7Sjsg 1286c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp 1287c349dbc7Sjsg // base address: 0x0 1288c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID 0x0000 1289c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID 0x0002 1290c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND 0x0004 1291c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS 0x0006 1292c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID 0x0008 1293c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE 0x0009 1294c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS 0x000a 1295c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS 0x000b 1296c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE 0x000c 1297c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY 0x000d 1298c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER 0x000e 1299c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST 0x000f 1300c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 0x0010 1301c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 0x0014 1302c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 0x0018 1303c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 0x001c 1304c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 0x0020 1305c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 0x0024 1306c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID 0x002c 1307c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR 0x0030 1308c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR 0x0034 1309c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE 0x003c 1310c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN 0x003d 1311c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST 0x0064 1312c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP 0x0066 1313c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP 0x0068 1314c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL 0x006c 1315c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS 0x006e 1316c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP 0x0070 1317c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL 0x0074 1318c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS 0x0076 1319c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 0x0088 1320c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 0x008c 1321c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 0x008e 1322c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 0x0090 1323c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 0x0094 1324c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 0x0096 1325c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2 0x0098 1326c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2 0x009c 1327c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2 0x009e 1328c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST 0x00a0 1329c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL 0x00a2 1330c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO 0x00a4 1331c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI 0x00a8 1332c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA 0x00a8 1333c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK 0x00ac 1334c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 0x00ac 1335c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 0x00b0 1336c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING 0x00b0 1337c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 0x00b4 1338c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST 0x00c0 1339c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL 0x00c2 1340c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE 0x00c4 1341c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA 0x00c8 1342c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1343c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1344c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 1345c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 0x010c 1346c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1347c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 1348c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK 0x0158 1349c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1350c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS 0x0160 1351c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK 0x0164 1352c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1353c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 0x016c 1354c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 0x0170 1355c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 0x0174 1356c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 0x0178 1357c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 1358c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 0x018c 1359c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 1360c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 1361c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1362c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP 0x02b4 1363c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL 0x02b6 1364c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1365c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP 0x032c 1366c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL 0x032e 1367c349dbc7Sjsg 1368c349dbc7Sjsg 1369c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp 1370c349dbc7Sjsg // base address: 0x0 1371c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID 0x0000 1372c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID 0x0002 1373c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND 0x0004 1374c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS 0x0006 1375c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID 0x0008 1376c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE 0x0009 1377c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS 0x000a 1378c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS 0x000b 1379c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE 0x000c 1380c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY 0x000d 1381c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER 0x000e 1382c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST 0x000f 1383c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 0x0010 1384c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 0x0014 1385c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 0x0018 1386c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 0x001c 1387c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 0x0020 1388c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 0x0024 1389c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID 0x002c 1390c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR 0x0030 1391c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR 0x0034 1392c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE 0x003c 1393c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN 0x003d 1394c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST 0x0064 1395c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP 0x0066 1396c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP 0x0068 1397c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL 0x006c 1398c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS 0x006e 1399c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP 0x0070 1400c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL 0x0074 1401c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS 0x0076 1402c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 0x0088 1403c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 0x008c 1404c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 0x008e 1405c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 0x0090 1406c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 0x0094 1407c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 0x0096 1408c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2 0x0098 1409c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2 0x009c 1410c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2 0x009e 1411c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST 0x00a0 1412c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL 0x00a2 1413c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO 0x00a4 1414c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI 0x00a8 1415c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA 0x00a8 1416c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK 0x00ac 1417c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 0x00ac 1418c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 0x00b0 1419c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING 0x00b0 1420c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 0x00b4 1421c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST 0x00c0 1422c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL 0x00c2 1423c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE 0x00c4 1424c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA 0x00c8 1425c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1426c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1427c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 0x0108 1428c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 0x010c 1429c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1430c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS 0x0154 1431c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK 0x0158 1432c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1433c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS 0x0160 1434c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK 0x0164 1435c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1436c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 0x016c 1437c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 0x0170 1438c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 0x0174 1439c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 0x0178 1440c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 0x0188 1441c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 0x018c 1442c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 0x0190 1443c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 0x0194 1444c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1445c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP 0x02b4 1446c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL 0x02b6 1447c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1448c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP 0x032c 1449c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL 0x032e 1450c349dbc7Sjsg 1451c349dbc7Sjsg 1452c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp 1453c349dbc7Sjsg // base address: 0x0 1454c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID 0x0000 1455c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID 0x0002 1456c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND 0x0004 1457c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS 0x0006 1458c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID 0x0008 1459c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE 0x0009 1460c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS 0x000a 1461c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS 0x000b 1462c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE 0x000c 1463c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY 0x000d 1464c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER 0x000e 1465c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST 0x000f 1466c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 0x0010 1467c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 0x0014 1468c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 0x0018 1469c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 0x001c 1470c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 0x0020 1471c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 0x0024 1472c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID 0x002c 1473c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR 0x0030 1474c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR 0x0034 1475c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE 0x003c 1476c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN 0x003d 1477c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST 0x0064 1478c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP 0x0066 1479c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP 0x0068 1480c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL 0x006c 1481c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS 0x006e 1482c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP 0x0070 1483c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL 0x0074 1484c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS 0x0076 1485c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 0x0088 1486c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 0x008c 1487c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 0x008e 1488c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 0x0090 1489c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 0x0094 1490c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 0x0096 1491c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2 0x0098 1492c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2 0x009c 1493c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2 0x009e 1494c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST 0x00a0 1495c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL 0x00a2 1496c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO 0x00a4 1497c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI 0x00a8 1498c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA 0x00a8 1499c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK 0x00ac 1500c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 0x00ac 1501c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 0x00b0 1502c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING 0x00b0 1503c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 0x00b4 1504c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST 0x00c0 1505c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL 0x00c2 1506c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE 0x00c4 1507c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA 0x00c8 1508c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1509c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1510c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 0x0108 1511c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 0x010c 1512c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1513c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS 0x0154 1514c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK 0x0158 1515c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1516c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS 0x0160 1517c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK 0x0164 1518c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1519c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 0x016c 1520c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 0x0170 1521c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 0x0174 1522c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 0x0178 1523c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 0x0188 1524c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 0x018c 1525c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 0x0190 1526c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 0x0194 1527c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1528c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP 0x02b4 1529c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL 0x02b6 1530c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1531c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP 0x032c 1532c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL 0x032e 1533c349dbc7Sjsg 1534c349dbc7Sjsg 1535c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp 1536c349dbc7Sjsg // base address: 0x0 1537c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID 0x0000 1538c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID 0x0002 1539c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND 0x0004 1540c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS 0x0006 1541c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID 0x0008 1542c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE 0x0009 1543c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS 0x000a 1544c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS 0x000b 1545c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE 0x000c 1546c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY 0x000d 1547c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER 0x000e 1548c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST 0x000f 1549c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 0x0010 1550c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 0x0014 1551c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 0x0018 1552c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 0x001c 1553c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 0x0020 1554c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 0x0024 1555c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID 0x002c 1556c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR 0x0030 1557c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR 0x0034 1558c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE 0x003c 1559c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN 0x003d 1560c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST 0x0064 1561c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP 0x0066 1562c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP 0x0068 1563c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL 0x006c 1564c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS 0x006e 1565c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP 0x0070 1566c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL 0x0074 1567c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS 0x0076 1568c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 0x0088 1569c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 0x008c 1570c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 0x008e 1571c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 0x0090 1572c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 0x0094 1573c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 0x0096 1574c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2 0x0098 1575c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2 0x009c 1576c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2 0x009e 1577c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST 0x00a0 1578c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL 0x00a2 1579c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO 0x00a4 1580c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI 0x00a8 1581c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA 0x00a8 1582c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK 0x00ac 1583c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 0x00ac 1584c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 0x00b0 1585c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING 0x00b0 1586c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 0x00b4 1587c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST 0x00c0 1588c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL 0x00c2 1589c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE 0x00c4 1590c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA 0x00c8 1591c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1592c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1593c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 0x0108 1594c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 0x010c 1595c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1596c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS 0x0154 1597c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK 0x0158 1598c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1599c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS 0x0160 1600c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK 0x0164 1601c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1602c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 0x016c 1603c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 0x0170 1604c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 0x0174 1605c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 0x0178 1606c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 0x0188 1607c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 0x018c 1608c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 0x0190 1609c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 0x0194 1610c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1611c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP 0x02b4 1612c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL 0x02b6 1613c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1614c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP 0x032c 1615c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL 0x032e 1616c349dbc7Sjsg 1617c349dbc7Sjsg 1618c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp 1619c349dbc7Sjsg // base address: 0x0 1620c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID 0x0000 1621c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID 0x0002 1622c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND 0x0004 1623c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS 0x0006 1624c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID 0x0008 1625c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE 0x0009 1626c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS 0x000a 1627c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS 0x000b 1628c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE 0x000c 1629c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY 0x000d 1630c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER 0x000e 1631c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST 0x000f 1632c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 0x0010 1633c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 0x0014 1634c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 0x0018 1635c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 0x001c 1636c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 0x0020 1637c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 0x0024 1638c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID 0x002c 1639c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR 0x0030 1640c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR 0x0034 1641c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE 0x003c 1642c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN 0x003d 1643c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST 0x0064 1644c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP 0x0066 1645c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP 0x0068 1646c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL 0x006c 1647c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS 0x006e 1648c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP 0x0070 1649c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL 0x0074 1650c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS 0x0076 1651c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 0x0088 1652c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 0x008c 1653c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 0x008e 1654c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 0x0090 1655c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 0x0094 1656c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 0x0096 1657c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2 0x0098 1658c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2 0x009c 1659c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2 0x009e 1660c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST 0x00a0 1661c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL 0x00a2 1662c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO 0x00a4 1663c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI 0x00a8 1664c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA 0x00a8 1665c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK 0x00ac 1666c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 0x00ac 1667c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 0x00b0 1668c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING 0x00b0 1669c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 0x00b4 1670c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST 0x00c0 1671c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL 0x00c2 1672c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE 0x00c4 1673c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA 0x00c8 1674c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1675c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1676c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 0x0108 1677c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 0x010c 1678c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1679c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS 0x0154 1680c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK 0x0158 1681c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1682c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS 0x0160 1683c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK 0x0164 1684c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1685c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 0x016c 1686c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 0x0170 1687c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 0x0174 1688c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 0x0178 1689c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 0x0188 1690c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 0x018c 1691c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 0x0190 1692c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 0x0194 1693c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1694c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP 0x02b4 1695c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL 0x02b6 1696c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1697c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP 0x032c 1698c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL 0x032e 1699c349dbc7Sjsg 1700c349dbc7Sjsg 1701c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp 1702c349dbc7Sjsg // base address: 0x0 1703c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID 0x0000 1704c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID 0x0002 1705c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND 0x0004 1706c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS 0x0006 1707c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID 0x0008 1708c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE 0x0009 1709c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS 0x000a 1710c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS 0x000b 1711c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE 0x000c 1712c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY 0x000d 1713c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER 0x000e 1714c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST 0x000f 1715c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 0x0010 1716c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 0x0014 1717c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 0x0018 1718c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 0x001c 1719c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 0x0020 1720c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 0x0024 1721c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID 0x002c 1722c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR 0x0030 1723c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR 0x0034 1724c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE 0x003c 1725c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN 0x003d 1726c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST 0x0064 1727c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP 0x0066 1728c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP 0x0068 1729c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL 0x006c 1730c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS 0x006e 1731c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP 0x0070 1732c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL 0x0074 1733c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS 0x0076 1734c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 0x0088 1735c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 0x008c 1736c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 0x008e 1737c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 0x0090 1738c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 0x0094 1739c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 0x0096 1740c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2 0x0098 1741c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2 0x009c 1742c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2 0x009e 1743c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST 0x00a0 1744c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL 0x00a2 1745c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO 0x00a4 1746c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI 0x00a8 1747c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA 0x00a8 1748c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK 0x00ac 1749c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 0x00ac 1750c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 0x00b0 1751c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING 0x00b0 1752c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 0x00b4 1753c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST 0x00c0 1754c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL 0x00c2 1755c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE 0x00c4 1756c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA 0x00c8 1757c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1758c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1759c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 0x0108 1760c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 0x010c 1761c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1762c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS 0x0154 1763c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK 0x0158 1764c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1765c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS 0x0160 1766c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK 0x0164 1767c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1768c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 0x016c 1769c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 0x0170 1770c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 0x0174 1771c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 0x0178 1772c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 0x0188 1773c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 0x018c 1774c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 0x0190 1775c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 0x0194 1776c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1777c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP 0x02b4 1778c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL 0x02b6 1779c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1780c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP 0x032c 1781c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL 0x032e 1782c349dbc7Sjsg 1783c349dbc7Sjsg 1784c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp 1785c349dbc7Sjsg // base address: 0x0 1786c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID 0x0000 1787c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID 0x0002 1788c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND 0x0004 1789c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS 0x0006 1790c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID 0x0008 1791c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE 0x0009 1792c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS 0x000a 1793c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS 0x000b 1794c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE 0x000c 1795c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY 0x000d 1796c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER 0x000e 1797c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST 0x000f 1798c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 0x0010 1799c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 0x0014 1800c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 0x0018 1801c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 0x001c 1802c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 0x0020 1803c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 0x0024 1804c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID 0x002c 1805c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR 0x0030 1806c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR 0x0034 1807c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE 0x003c 1808c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN 0x003d 1809c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST 0x0064 1810c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP 0x0066 1811c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP 0x0068 1812c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL 0x006c 1813c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS 0x006e 1814c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP 0x0070 1815c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL 0x0074 1816c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS 0x0076 1817c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 0x0088 1818c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 0x008c 1819c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 0x008e 1820c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 0x0090 1821c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 0x0094 1822c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 0x0096 1823c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2 0x0098 1824c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2 0x009c 1825c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2 0x009e 1826c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST 0x00a0 1827c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL 0x00a2 1828c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO 0x00a4 1829c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI 0x00a8 1830c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA 0x00a8 1831c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK 0x00ac 1832c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 0x00ac 1833c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 0x00b0 1834c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING 0x00b0 1835c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 0x00b4 1836c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST 0x00c0 1837c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL 0x00c2 1838c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE 0x00c4 1839c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA 0x00c8 1840c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1841c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1842c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 0x0108 1843c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 0x010c 1844c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1845c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS 0x0154 1846c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK 0x0158 1847c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1848c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS 0x0160 1849c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK 0x0164 1850c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1851c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 0x016c 1852c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 0x0170 1853c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 0x0174 1854c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 0x0178 1855c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 0x0188 1856c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 0x018c 1857c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 0x0190 1858c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 0x0194 1859c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1860c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP 0x02b4 1861c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL 0x02b6 1862c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1863c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP 0x032c 1864c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL 0x032e 1865c349dbc7Sjsg 1866c349dbc7Sjsg 1867c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp 1868c349dbc7Sjsg // base address: 0x0 1869c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID 0x0000 1870c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID 0x0002 1871c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND 0x0004 1872c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS 0x0006 1873c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID 0x0008 1874c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE 0x0009 1875c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS 0x000a 1876c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS 0x000b 1877c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE 0x000c 1878c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY 0x000d 1879c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER 0x000e 1880c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST 0x000f 1881c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 0x0010 1882c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 0x0014 1883c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 0x0018 1884c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 0x001c 1885c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 0x0020 1886c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 0x0024 1887c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID 0x002c 1888c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR 0x0030 1889c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR 0x0034 1890c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE 0x003c 1891c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN 0x003d 1892c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST 0x0064 1893c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP 0x0066 1894c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP 0x0068 1895c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL 0x006c 1896c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS 0x006e 1897c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP 0x0070 1898c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL 0x0074 1899c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS 0x0076 1900c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 0x0088 1901c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 0x008c 1902c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 0x008e 1903c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 0x0090 1904c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 0x0094 1905c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 0x0096 1906c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2 0x0098 1907c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2 0x009c 1908c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2 0x009e 1909c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST 0x00a0 1910c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL 0x00a2 1911c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO 0x00a4 1912c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI 0x00a8 1913c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA 0x00a8 1914c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK 0x00ac 1915c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 0x00ac 1916c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 0x00b0 1917c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING 0x00b0 1918c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 0x00b4 1919c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST 0x00c0 1920c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL 0x00c2 1921c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE 0x00c4 1922c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA 0x00c8 1923c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1924c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1925c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 0x0108 1926c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 0x010c 1927c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1928c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS 0x0154 1929c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK 0x0158 1930c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1931c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS 0x0160 1932c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK 0x0164 1933c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1934c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 0x016c 1935c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 0x0170 1936c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 0x0174 1937c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 0x0178 1938c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 0x0188 1939c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 0x018c 1940c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 0x0190 1941c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 0x0194 1942c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1943c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP 0x02b4 1944c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL 0x02b6 1945c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1946c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP 0x032c 1947c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL 0x032e 1948c349dbc7Sjsg 1949c349dbc7Sjsg 1950c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp 1951c349dbc7Sjsg // base address: 0x0 1952c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID 0x0000 1953c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID 0x0002 1954c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND 0x0004 1955c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS 0x0006 1956c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID 0x0008 1957c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE 0x0009 1958c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS 0x000a 1959c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS 0x000b 1960c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE 0x000c 1961c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY 0x000d 1962c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER 0x000e 1963c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST 0x000f 1964c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 0x0010 1965c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 0x0014 1966c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 0x0018 1967c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 0x001c 1968c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 0x0020 1969c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 0x0024 1970c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID 0x002c 1971c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR 0x0030 1972c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR 0x0034 1973c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE 0x003c 1974c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN 0x003d 1975c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST 0x0064 1976c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP 0x0066 1977c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP 0x0068 1978c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL 0x006c 1979c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS 0x006e 1980c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP 0x0070 1981c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL 0x0074 1982c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS 0x0076 1983c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 0x0088 1984c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 0x008c 1985c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 0x008e 1986c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 0x0090 1987c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 0x0094 1988c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 0x0096 1989c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2 0x0098 1990c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2 0x009c 1991c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2 0x009e 1992c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST 0x00a0 1993c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL 0x00a2 1994c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO 0x00a4 1995c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI 0x00a8 1996c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA 0x00a8 1997c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK 0x00ac 1998c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 0x00ac 1999c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 0x00b0 2000c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING 0x00b0 2001c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 0x00b4 2002c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST 0x00c0 2003c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL 0x00c2 2004c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE 0x00c4 2005c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA 0x00c8 2006c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2007c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2008c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 0x0108 2009c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 0x010c 2010c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2011c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS 0x0154 2012c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK 0x0158 2013c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2014c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS 0x0160 2015c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK 0x0164 2016c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2017c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 0x016c 2018c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 0x0170 2019c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 0x0174 2020c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 0x0178 2021c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 0x0188 2022c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 0x018c 2023c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 0x0190 2024c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 0x0194 2025c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2026c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP 0x02b4 2027c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL 0x02b6 2028c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2029c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP 0x032c 2030c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL 0x032e 2031c349dbc7Sjsg 2032c349dbc7Sjsg 2033c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp 2034c349dbc7Sjsg // base address: 0x0 2035c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID 0x0000 2036c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID 0x0002 2037c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND 0x0004 2038c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS 0x0006 2039c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID 0x0008 2040c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE 0x0009 2041c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS 0x000a 2042c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS 0x000b 2043c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE 0x000c 2044c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY 0x000d 2045c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER 0x000e 2046c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST 0x000f 2047c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 0x0010 2048c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 0x0014 2049c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 0x0018 2050c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 0x001c 2051c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 0x0020 2052c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 0x0024 2053c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID 0x002c 2054c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR 0x0030 2055c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR 0x0034 2056c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE 0x003c 2057c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN 0x003d 2058c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST 0x0064 2059c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP 0x0066 2060c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP 0x0068 2061c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL 0x006c 2062c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS 0x006e 2063c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP 0x0070 2064c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL 0x0074 2065c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS 0x0076 2066c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 0x0088 2067c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 0x008c 2068c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 0x008e 2069c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 0x0090 2070c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 0x0094 2071c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 0x0096 2072c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2 0x0098 2073c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2 0x009c 2074c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2 0x009e 2075c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST 0x00a0 2076c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL 0x00a2 2077c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO 0x00a4 2078c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI 0x00a8 2079c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA 0x00a8 2080c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK 0x00ac 2081c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 0x00ac 2082c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 0x00b0 2083c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING 0x00b0 2084c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 0x00b4 2085c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST 0x00c0 2086c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL 0x00c2 2087c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE 0x00c4 2088c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA 0x00c8 2089c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2090c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2091c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 0x0108 2092c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 0x010c 2093c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2094c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS 0x0154 2095c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK 0x0158 2096c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2097c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS 0x0160 2098c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK 0x0164 2099c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2100c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 0x016c 2101c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 0x0170 2102c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 0x0174 2103c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 0x0178 2104c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 0x0188 2105c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 0x018c 2106c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 0x0190 2107c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 0x0194 2108c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2109c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP 0x02b4 2110c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL 0x02b6 2111c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2112c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP 0x032c 2113c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL 0x032e 2114c349dbc7Sjsg 2115c349dbc7Sjsg 2116c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp 2117c349dbc7Sjsg // base address: 0x0 2118c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID 0x0000 2119c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID 0x0002 2120c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND 0x0004 2121c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS 0x0006 2122c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID 0x0008 2123c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE 0x0009 2124c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS 0x000a 2125c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS 0x000b 2126c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE 0x000c 2127c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY 0x000d 2128c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER 0x000e 2129c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST 0x000f 2130c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 0x0010 2131c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 0x0014 2132c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 0x0018 2133c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 0x001c 2134c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 0x0020 2135c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 0x0024 2136c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID 0x002c 2137c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR 0x0030 2138c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR 0x0034 2139c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE 0x003c 2140c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN 0x003d 2141c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST 0x0064 2142c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP 0x0066 2143c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP 0x0068 2144c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL 0x006c 2145c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS 0x006e 2146c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP 0x0070 2147c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL 0x0074 2148c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS 0x0076 2149c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 0x0088 2150c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 0x008c 2151c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 0x008e 2152c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 0x0090 2153c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 0x0094 2154c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 0x0096 2155c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2 0x0098 2156c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2 0x009c 2157c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2 0x009e 2158c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST 0x00a0 2159c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL 0x00a2 2160c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO 0x00a4 2161c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI 0x00a8 2162c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA 0x00a8 2163c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK 0x00ac 2164c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 0x00ac 2165c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 0x00b0 2166c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING 0x00b0 2167c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 0x00b4 2168c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST 0x00c0 2169c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL 0x00c2 2170c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE 0x00c4 2171c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA 0x00c8 2172c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2173c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2174c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 0x0108 2175c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 0x010c 2176c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2177c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS 0x0154 2178c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK 0x0158 2179c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2180c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS 0x0160 2181c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK 0x0164 2182c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2183c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 0x016c 2184c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 0x0170 2185c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 0x0174 2186c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 0x0178 2187c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 0x0188 2188c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 0x018c 2189c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 0x0190 2190c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 0x0194 2191c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2192c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP 0x02b4 2193c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL 0x02b6 2194c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2195c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP 0x032c 2196c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL 0x032e 2197c349dbc7Sjsg 2198c349dbc7Sjsg 2199c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp 2200c349dbc7Sjsg // base address: 0x0 2201c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID 0x0000 2202c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID 0x0002 2203c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND 0x0004 2204c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS 0x0006 2205c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID 0x0008 2206c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE 0x0009 2207c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS 0x000a 2208c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS 0x000b 2209c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE 0x000c 2210c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY 0x000d 2211c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER 0x000e 2212c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST 0x000f 2213c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 0x0010 2214c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 0x0014 2215c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 0x0018 2216c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 0x001c 2217c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 0x0020 2218c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 0x0024 2219c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID 0x002c 2220c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR 0x0030 2221c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR 0x0034 2222c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE 0x003c 2223c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN 0x003d 2224c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST 0x0064 2225c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP 0x0066 2226c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP 0x0068 2227c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL 0x006c 2228c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS 0x006e 2229c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP 0x0070 2230c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL 0x0074 2231c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS 0x0076 2232c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 0x0088 2233c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 0x008c 2234c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 0x008e 2235c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 0x0090 2236c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 0x0094 2237c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 0x0096 2238c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2 0x0098 2239c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2 0x009c 2240c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2 0x009e 2241c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST 0x00a0 2242c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL 0x00a2 2243c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO 0x00a4 2244c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI 0x00a8 2245c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA 0x00a8 2246c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK 0x00ac 2247c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 0x00ac 2248c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 0x00b0 2249c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING 0x00b0 2250c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 0x00b4 2251c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST 0x00c0 2252c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL 0x00c2 2253c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE 0x00c4 2254c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA 0x00c8 2255c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2256c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2257c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 0x0108 2258c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 0x010c 2259c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2260c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS 0x0154 2261c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK 0x0158 2262c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2263c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS 0x0160 2264c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK 0x0164 2265c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2266c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 0x016c 2267c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 0x0170 2268c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 0x0174 2269c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 0x0178 2270c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 0x0188 2271c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 0x018c 2272c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 0x0190 2273c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 0x0194 2274c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2275c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP 0x02b4 2276c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL 0x02b6 2277c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2278c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP 0x032c 2279c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL 0x032e 2280c349dbc7Sjsg 2281c349dbc7Sjsg 2282c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp 2283c349dbc7Sjsg // base address: 0x0 2284c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID 0x0000 2285c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID 0x0002 2286c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND 0x0004 2287c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS 0x0006 2288c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID 0x0008 2289c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE 0x0009 2290c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS 0x000a 2291c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS 0x000b 2292c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE 0x000c 2293c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY 0x000d 2294c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER 0x000e 2295c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST 0x000f 2296c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 0x0010 2297c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 0x0014 2298c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 0x0018 2299c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 0x001c 2300c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 0x0020 2301c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 0x0024 2302c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID 0x002c 2303c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR 0x0030 2304c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR 0x0034 2305c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE 0x003c 2306c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN 0x003d 2307c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST 0x0064 2308c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP 0x0066 2309c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP 0x0068 2310c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL 0x006c 2311c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS 0x006e 2312c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP 0x0070 2313c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL 0x0074 2314c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS 0x0076 2315c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 0x0088 2316c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 0x008c 2317c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 0x008e 2318c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 0x0090 2319c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 0x0094 2320c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 0x0096 2321c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2 0x0098 2322c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2 0x009c 2323c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2 0x009e 2324c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST 0x00a0 2325c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL 0x00a2 2326c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO 0x00a4 2327c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI 0x00a8 2328c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA 0x00a8 2329c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK 0x00ac 2330c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 0x00ac 2331c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 0x00b0 2332c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING 0x00b0 2333c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 0x00b4 2334c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST 0x00c0 2335c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL 0x00c2 2336c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE 0x00c4 2337c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA 0x00c8 2338c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2339c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2340c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 0x0108 2341c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 0x010c 2342c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2343c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS 0x0154 2344c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK 0x0158 2345c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2346c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS 0x0160 2347c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK 0x0164 2348c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2349c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 0x016c 2350c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 0x0170 2351c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 0x0174 2352c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 0x0178 2353c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 0x0188 2354c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 0x018c 2355c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 0x0190 2356c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 0x0194 2357c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2358c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP 0x02b4 2359c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL 0x02b6 2360c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2361c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP 0x032c 2362c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL 0x032e 2363c349dbc7Sjsg 2364c349dbc7Sjsg 2365c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp 2366c349dbc7Sjsg // base address: 0x0 2367c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID 0x0000 2368c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID 0x0002 2369c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND 0x0004 2370c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS 0x0006 2371c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID 0x0008 2372c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE 0x0009 2373c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS 0x000a 2374c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS 0x000b 2375c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE 0x000c 2376c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY 0x000d 2377c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER 0x000e 2378c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST 0x000f 2379c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 0x0010 2380c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 0x0014 2381c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 0x0018 2382c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 0x001c 2383c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 0x0020 2384c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 0x0024 2385c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID 0x002c 2386c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR 0x0030 2387c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR 0x0034 2388c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE 0x003c 2389c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN 0x003d 2390c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST 0x0064 2391c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP 0x0066 2392c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP 0x0068 2393c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL 0x006c 2394c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS 0x006e 2395c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP 0x0070 2396c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL 0x0074 2397c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS 0x0076 2398c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 0x0088 2399c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 0x008c 2400c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 0x008e 2401c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 0x0090 2402c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 0x0094 2403c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 0x0096 2404c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2 0x0098 2405c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2 0x009c 2406c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2 0x009e 2407c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST 0x00a0 2408c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL 0x00a2 2409c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO 0x00a4 2410c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI 0x00a8 2411c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA 0x00a8 2412c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK 0x00ac 2413c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 0x00ac 2414c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 0x00b0 2415c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING 0x00b0 2416c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 0x00b4 2417c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST 0x00c0 2418c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL 0x00c2 2419c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE 0x00c4 2420c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA 0x00c8 2421c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2422c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2423c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 0x0108 2424c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 0x010c 2425c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2426c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS 0x0154 2427c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK 0x0158 2428c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2429c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS 0x0160 2430c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK 0x0164 2431c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2432c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 0x016c 2433c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 0x0170 2434c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 0x0174 2435c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 0x0178 2436c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 0x0188 2437c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 0x018c 2438c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 0x0190 2439c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 0x0194 2440c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2441c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP 0x02b4 2442c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL 0x02b6 2443c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2444c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP 0x032c 2445c349dbc7Sjsg #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL 0x032e 2446c349dbc7Sjsg 2447c349dbc7Sjsg 2448c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC 2449c349dbc7Sjsg // base address: 0x0 2450c349dbc7Sjsg #define mmMM_INDEX 0x0000 2451c349dbc7Sjsg #define mmMM_INDEX_BASE_IDX 0 2452c349dbc7Sjsg #define mmMM_DATA 0x0001 2453c349dbc7Sjsg #define mmMM_DATA_BASE_IDX 0 2454c349dbc7Sjsg #define mmMM_INDEX_HI 0x0006 2455c349dbc7Sjsg #define mmMM_INDEX_HI_BASE_IDX 0 2456c349dbc7Sjsg 2457c349dbc7Sjsg 2458c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_SYSDEC 2459c349dbc7Sjsg // base address: 0x0 2460c349dbc7Sjsg #define mmSYSHUB_INDEX_OVLP 0x0008 2461c349dbc7Sjsg #define mmSYSHUB_INDEX_OVLP_BASE_IDX 0 2462c349dbc7Sjsg #define mmSYSHUB_DATA_OVLP 0x0009 2463c349dbc7Sjsg #define mmSYSHUB_DATA_OVLP_BASE_IDX 0 2464c349dbc7Sjsg #define mmPCIE_INDEX 0x000c 2465c349dbc7Sjsg #define mmPCIE_INDEX_BASE_IDX 0 2466c349dbc7Sjsg #define mmPCIE_DATA 0x000d 2467c349dbc7Sjsg #define mmPCIE_DATA_BASE_IDX 0 2468c349dbc7Sjsg #define mmPCIE_INDEX2 0x000e 2469c349dbc7Sjsg #define mmPCIE_INDEX2_BASE_IDX 0 2470c349dbc7Sjsg #define mmPCIE_DATA2 0x000f 2471c349dbc7Sjsg #define mmPCIE_DATA2_BASE_IDX 0 2472c349dbc7Sjsg #define mmSBIOS_SCRATCH_0 0x0034 2473c349dbc7Sjsg #define mmSBIOS_SCRATCH_0_BASE_IDX 1 2474c349dbc7Sjsg #define mmSBIOS_SCRATCH_1 0x0035 2475c349dbc7Sjsg #define mmSBIOS_SCRATCH_1_BASE_IDX 1 2476c349dbc7Sjsg #define mmSBIOS_SCRATCH_2 0x0036 2477c349dbc7Sjsg #define mmSBIOS_SCRATCH_2_BASE_IDX 1 2478c349dbc7Sjsg #define mmSBIOS_SCRATCH_3 0x0037 2479c349dbc7Sjsg #define mmSBIOS_SCRATCH_3_BASE_IDX 1 2480c349dbc7Sjsg #define mmBIOS_SCRATCH_0 0x0038 2481c349dbc7Sjsg #define mmBIOS_SCRATCH_0_BASE_IDX 1 2482c349dbc7Sjsg #define mmBIOS_SCRATCH_1 0x0039 2483c349dbc7Sjsg #define mmBIOS_SCRATCH_1_BASE_IDX 1 2484c349dbc7Sjsg #define mmBIOS_SCRATCH_2 0x003a 2485c349dbc7Sjsg #define mmBIOS_SCRATCH_2_BASE_IDX 1 2486c349dbc7Sjsg #define mmBIOS_SCRATCH_3 0x003b 2487c349dbc7Sjsg #define mmBIOS_SCRATCH_3_BASE_IDX 1 2488c349dbc7Sjsg #define mmBIOS_SCRATCH_4 0x003c 2489c349dbc7Sjsg #define mmBIOS_SCRATCH_4_BASE_IDX 1 2490c349dbc7Sjsg #define mmBIOS_SCRATCH_5 0x003d 2491c349dbc7Sjsg #define mmBIOS_SCRATCH_5_BASE_IDX 1 2492c349dbc7Sjsg #define mmBIOS_SCRATCH_6 0x003e 2493c349dbc7Sjsg #define mmBIOS_SCRATCH_6_BASE_IDX 1 2494c349dbc7Sjsg #define mmBIOS_SCRATCH_7 0x003f 2495c349dbc7Sjsg #define mmBIOS_SCRATCH_7_BASE_IDX 1 2496c349dbc7Sjsg #define mmBIOS_SCRATCH_8 0x0040 2497c349dbc7Sjsg #define mmBIOS_SCRATCH_8_BASE_IDX 1 2498c349dbc7Sjsg #define mmBIOS_SCRATCH_9 0x0041 2499c349dbc7Sjsg #define mmBIOS_SCRATCH_9_BASE_IDX 1 2500c349dbc7Sjsg #define mmBIOS_SCRATCH_10 0x0042 2501c349dbc7Sjsg #define mmBIOS_SCRATCH_10_BASE_IDX 1 2502c349dbc7Sjsg #define mmBIOS_SCRATCH_11 0x0043 2503c349dbc7Sjsg #define mmBIOS_SCRATCH_11_BASE_IDX 1 2504c349dbc7Sjsg #define mmBIOS_SCRATCH_12 0x0044 2505c349dbc7Sjsg #define mmBIOS_SCRATCH_12_BASE_IDX 1 2506c349dbc7Sjsg #define mmBIOS_SCRATCH_13 0x0045 2507c349dbc7Sjsg #define mmBIOS_SCRATCH_13_BASE_IDX 1 2508c349dbc7Sjsg #define mmBIOS_SCRATCH_14 0x0046 2509c349dbc7Sjsg #define mmBIOS_SCRATCH_14_BASE_IDX 1 2510c349dbc7Sjsg #define mmBIOS_SCRATCH_15 0x0047 2511c349dbc7Sjsg #define mmBIOS_SCRATCH_15_BASE_IDX 1 2512c349dbc7Sjsg #define mmBIF_RLC_INTR_CNTL 0x004c 2513c349dbc7Sjsg #define mmBIF_RLC_INTR_CNTL_BASE_IDX 1 2514c349dbc7Sjsg #define mmBIF_VCE_INTR_CNTL 0x004d 2515c349dbc7Sjsg #define mmBIF_VCE_INTR_CNTL_BASE_IDX 1 2516c349dbc7Sjsg #define mmBIF_UVD_INTR_CNTL 0x004e 2517c349dbc7Sjsg #define mmBIF_UVD_INTR_CNTL_BASE_IDX 1 2518c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR0 0x006c 2519c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 2520c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x006d 2521c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 2522c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR1 0x006e 2523c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 2524c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x006f 2525c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 2526c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR2 0x0070 2527c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 2528c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 2529c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 2530c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR3 0x0072 2531c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 2532c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 2533c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 2534c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR4 0x0074 2535c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 2536c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 2537c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 2538c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR5 0x0076 2539c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 2540c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 2541c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 2542c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR6 0x0078 2543c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 2544c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 2545c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 2546c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR7 0x007a 2547c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 2548c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x007b 2549c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 2550c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_CNTL 0x007c 2551c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 1 2552c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ZERO_CPL 0x007d 2553c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 2554c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ONE_CPL 0x007e 2555c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 2556c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f 2557c349dbc7Sjsg #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 2558c349dbc7Sjsg 2559c349dbc7Sjsg 2560c349dbc7Sjsg // addressBlock: nbio_nbif0_syshub_mmreg_syshubdec 2561c349dbc7Sjsg // base address: 0x0 2562c349dbc7Sjsg #define mmSYSHUB_INDEX 0x0008 2563c349dbc7Sjsg #define mmSYSHUB_INDEX_BASE_IDX 0 2564c349dbc7Sjsg #define mmSYSHUB_DATA 0x0009 2565c349dbc7Sjsg #define mmSYSHUB_DATA_BASE_IDX 0 2566c349dbc7Sjsg 2567c349dbc7Sjsg 2568c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 2569c349dbc7Sjsg // base address: 0x0 2570c349dbc7Sjsg #define mmRCC_BIF_STRAP0 0x0000 2571c349dbc7Sjsg #define mmRCC_BIF_STRAP0_BASE_IDX 2 2572c349dbc7Sjsg #define mmRCC_DEV0_EPF0_STRAP0 0x0011 2573c349dbc7Sjsg #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 2 2574c349dbc7Sjsg 2575c349dbc7Sjsg 2576c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 2577c349dbc7Sjsg // base address: 0x0 2578c349dbc7Sjsg #define mmEP_PCIE_SCRATCH 0x0025 2579c349dbc7Sjsg #define mmEP_PCIE_SCRATCH_BASE_IDX 2 2580c349dbc7Sjsg #define mmEP_PCIE_CNTL 0x0027 2581c349dbc7Sjsg #define mmEP_PCIE_CNTL_BASE_IDX 2 2582c349dbc7Sjsg #define mmEP_PCIE_INT_CNTL 0x0028 2583c349dbc7Sjsg #define mmEP_PCIE_INT_CNTL_BASE_IDX 2 2584c349dbc7Sjsg #define mmEP_PCIE_INT_STATUS 0x0029 2585c349dbc7Sjsg #define mmEP_PCIE_INT_STATUS_BASE_IDX 2 2586c349dbc7Sjsg #define mmEP_PCIE_RX_CNTL2 0x002a 2587c349dbc7Sjsg #define mmEP_PCIE_RX_CNTL2_BASE_IDX 2 2588c349dbc7Sjsg #define mmEP_PCIE_BUS_CNTL 0x002b 2589c349dbc7Sjsg #define mmEP_PCIE_BUS_CNTL_BASE_IDX 2 2590c349dbc7Sjsg #define mmEP_PCIE_CFG_CNTL 0x002c 2591c349dbc7Sjsg #define mmEP_PCIE_CFG_CNTL_BASE_IDX 2 2592c349dbc7Sjsg #define mmEP_PCIE_TX_LTR_CNTL 0x002e 2593c349dbc7Sjsg #define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 2 2594c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x002f 2595c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 2596c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x002f 2597c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 2598c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x002f 2599c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 2600c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x002f 2601c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 2602c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x0030 2603c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 2604c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x0030 2605c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 2606c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x0030 2607c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 2608c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x0030 2609c349dbc7Sjsg #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 2610c349dbc7Sjsg #define mmEP_PCIE_F0_DPA_CAP 0x0034 2611c349dbc7Sjsg #define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 2 2612c349dbc7Sjsg #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0035 2613c349dbc7Sjsg #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 2614c349dbc7Sjsg #define mmEP_PCIE_F0_DPA_CNTL 0x0035 2615c349dbc7Sjsg #define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 2 2616c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0035 2617c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 2618c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0036 2619c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 2620c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0036 2621c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 2622c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0036 2623c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 2624c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0036 2625c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 2626c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0037 2627c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 2628c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0037 2629c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 2630c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0037 2631c349dbc7Sjsg #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 2632c349dbc7Sjsg #define mmEP_PCIE_PME_CONTROL 0x0037 2633c349dbc7Sjsg #define mmEP_PCIE_PME_CONTROL_BASE_IDX 2 2634c349dbc7Sjsg #define mmEP_PCIEP_RESERVED 0x0038 2635c349dbc7Sjsg #define mmEP_PCIEP_RESERVED_BASE_IDX 2 2636c349dbc7Sjsg #define mmEP_PCIE_TX_CNTL 0x003a 2637c349dbc7Sjsg #define mmEP_PCIE_TX_CNTL_BASE_IDX 2 2638c349dbc7Sjsg #define mmEP_PCIE_TX_REQUESTER_ID 0x003b 2639c349dbc7Sjsg #define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 2640c349dbc7Sjsg #define mmEP_PCIE_ERR_CNTL 0x003c 2641c349dbc7Sjsg #define mmEP_PCIE_ERR_CNTL_BASE_IDX 2 2642c349dbc7Sjsg #define mmEP_PCIE_RX_CNTL 0x003d 2643c349dbc7Sjsg #define mmEP_PCIE_RX_CNTL_BASE_IDX 2 2644c349dbc7Sjsg #define mmEP_PCIE_LC_SPEED_CNTL 0x003e 2645c349dbc7Sjsg #define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 2646c349dbc7Sjsg 2647c349dbc7Sjsg 2648c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 2649c349dbc7Sjsg // base address: 0x0 2650c349dbc7Sjsg #define mmDN_PCIE_RESERVED 0x0040 2651c349dbc7Sjsg #define mmDN_PCIE_RESERVED_BASE_IDX 2 2652c349dbc7Sjsg #define mmDN_PCIE_SCRATCH 0x0041 2653c349dbc7Sjsg #define mmDN_PCIE_SCRATCH_BASE_IDX 2 2654c349dbc7Sjsg #define mmDN_PCIE_CNTL 0x0043 2655c349dbc7Sjsg #define mmDN_PCIE_CNTL_BASE_IDX 2 2656c349dbc7Sjsg #define mmDN_PCIE_CONFIG_CNTL 0x0044 2657c349dbc7Sjsg #define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 2 2658c349dbc7Sjsg #define mmDN_PCIE_RX_CNTL2 0x0045 2659c349dbc7Sjsg #define mmDN_PCIE_RX_CNTL2_BASE_IDX 2 2660c349dbc7Sjsg #define mmDN_PCIE_BUS_CNTL 0x0046 2661c349dbc7Sjsg #define mmDN_PCIE_BUS_CNTL_BASE_IDX 2 2662c349dbc7Sjsg #define mmDN_PCIE_CFG_CNTL 0x0047 2663c349dbc7Sjsg #define mmDN_PCIE_CFG_CNTL_BASE_IDX 2 2664c349dbc7Sjsg 2665c349dbc7Sjsg 2666c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 2667c349dbc7Sjsg // base address: 0x0 2668c349dbc7Sjsg #define mmPCIE_ERR_CNTL 0x004f 2669c349dbc7Sjsg #define mmPCIE_ERR_CNTL_BASE_IDX 2 2670c349dbc7Sjsg #define mmPCIE_RX_CNTL 0x0050 2671c349dbc7Sjsg #define mmPCIE_RX_CNTL_BASE_IDX 2 2672c349dbc7Sjsg #define mmPCIE_LC_SPEED_CNTL 0x0051 2673c349dbc7Sjsg #define mmPCIE_LC_SPEED_CNTL_BASE_IDX 2 2674c349dbc7Sjsg #define mmPCIE_LC_CNTL2 0x0052 2675c349dbc7Sjsg #define mmPCIE_LC_CNTL2_BASE_IDX 2 2676c349dbc7Sjsg #define mmLTR_MSG_INFO_FROM_EP 0x0054 2677c349dbc7Sjsg #define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 2 2678c349dbc7Sjsg 2679c349dbc7Sjsg 2680c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] 2681c349dbc7Sjsg // base address: 0x3480 2682c349dbc7Sjsg #define mmRCC_ERR_LOG 0x0085 2683c349dbc7Sjsg #define mmRCC_ERR_LOG_BASE_IDX 2 2684c349dbc7Sjsg #define mmRCC_DOORBELL_APER_EN 0x00c0 2685c349dbc7Sjsg #define mmRCC_DOORBELL_APER_EN_BASE_IDX 2 2686c349dbc7Sjsg #define mmRCC_CONFIG_MEMSIZE 0x00c3 2687c349dbc7Sjsg #define mmRCC_CONFIG_MEMSIZE_BASE_IDX 2 2688c349dbc7Sjsg #define mmRCC_CONFIG_RESERVED 0x00c4 2689c349dbc7Sjsg #define mmRCC_CONFIG_RESERVED_BASE_IDX 2 2690*ad8b1aafSjsg #ifndef mmRCC_IOV_FUNC_IDENTIFIER 2691c349dbc7Sjsg #define mmRCC_IOV_FUNC_IDENTIFIER 0x00c5 2692c349dbc7Sjsg #define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 2693*ad8b1aafSjsg #endif 2694c349dbc7Sjsg 2695c349dbc7Sjsg 2696c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 2697c349dbc7Sjsg // base address: 0x0 2698c349dbc7Sjsg #define mmRCC_ERR_INT_CNTL 0x0086 2699c349dbc7Sjsg #define mmRCC_ERR_INT_CNTL_BASE_IDX 2 2700c349dbc7Sjsg #define mmRCC_BACO_CNTL_MISC 0x0087 2701c349dbc7Sjsg #define mmRCC_BACO_CNTL_MISC_BASE_IDX 2 2702c349dbc7Sjsg #define mmRCC_RESET_EN 0x0088 2703c349dbc7Sjsg #define mmRCC_RESET_EN_BASE_IDX 2 2704c349dbc7Sjsg #define mmRCC_VDM_SUPPORT 0x0089 2705c349dbc7Sjsg #define mmRCC_VDM_SUPPORT_BASE_IDX 2 2706c349dbc7Sjsg #define mmRCC_MARGIN_PARAM_CNTL0 0x008a 2707c349dbc7Sjsg #define mmRCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 2708c349dbc7Sjsg #define mmRCC_MARGIN_PARAM_CNTL1 0x008b 2709c349dbc7Sjsg #define mmRCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 2710c349dbc7Sjsg #define mmRCC_PEER_REG_RANGE0 0x00be 2711c349dbc7Sjsg #define mmRCC_PEER_REG_RANGE0_BASE_IDX 2 2712c349dbc7Sjsg #define mmRCC_PEER_REG_RANGE1 0x00bf 2713c349dbc7Sjsg #define mmRCC_PEER_REG_RANGE1_BASE_IDX 2 2714c349dbc7Sjsg #define mmRCC_BUS_CNTL 0x00c1 2715c349dbc7Sjsg #define mmRCC_BUS_CNTL_BASE_IDX 2 2716c349dbc7Sjsg #define mmRCC_CONFIG_CNTL 0x00c2 2717c349dbc7Sjsg #define mmRCC_CONFIG_CNTL_BASE_IDX 2 2718c349dbc7Sjsg #define mmRCC_CONFIG_F0_BASE 0x00c6 2719c349dbc7Sjsg #define mmRCC_CONFIG_F0_BASE_BASE_IDX 2 2720c349dbc7Sjsg #define mmRCC_CONFIG_APER_SIZE 0x00c7 2721c349dbc7Sjsg #define mmRCC_CONFIG_APER_SIZE_BASE_IDX 2 2722c349dbc7Sjsg #define mmRCC_CONFIG_REG_APER_SIZE 0x00c8 2723c349dbc7Sjsg #define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 2724c349dbc7Sjsg #define mmRCC_XDMA_LO 0x00c9 2725c349dbc7Sjsg #define mmRCC_XDMA_LO_BASE_IDX 2 2726c349dbc7Sjsg #define mmRCC_XDMA_HI 0x00ca 2727c349dbc7Sjsg #define mmRCC_XDMA_HI_BASE_IDX 2 2728c349dbc7Sjsg #define mmRCC_FEATURES_CONTROL_MISC 0x00cb 2729c349dbc7Sjsg #define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 2 2730c349dbc7Sjsg #define mmRCC_BUSNUM_CNTL1 0x00cc 2731c349dbc7Sjsg #define mmRCC_BUSNUM_CNTL1_BASE_IDX 2 2732c349dbc7Sjsg #define mmRCC_BUSNUM_LIST0 0x00cd 2733c349dbc7Sjsg #define mmRCC_BUSNUM_LIST0_BASE_IDX 2 2734c349dbc7Sjsg #define mmRCC_BUSNUM_LIST1 0x00ce 2735c349dbc7Sjsg #define mmRCC_BUSNUM_LIST1_BASE_IDX 2 2736c349dbc7Sjsg #define mmRCC_BUSNUM_CNTL2 0x00cf 2737c349dbc7Sjsg #define mmRCC_BUSNUM_CNTL2_BASE_IDX 2 2738c349dbc7Sjsg #define mmRCC_CAPTURE_HOST_BUSNUM 0x00d0 2739c349dbc7Sjsg #define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 2740c349dbc7Sjsg #define mmRCC_HOST_BUSNUM 0x00d1 2741c349dbc7Sjsg #define mmRCC_HOST_BUSNUM_BASE_IDX 2 2742c349dbc7Sjsg #define mmRCC_PEER0_FB_OFFSET_HI 0x00d2 2743c349dbc7Sjsg #define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 2744c349dbc7Sjsg #define mmRCC_PEER0_FB_OFFSET_LO 0x00d3 2745c349dbc7Sjsg #define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 2746c349dbc7Sjsg #define mmRCC_PEER1_FB_OFFSET_HI 0x00d4 2747c349dbc7Sjsg #define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 2748c349dbc7Sjsg #define mmRCC_PEER1_FB_OFFSET_LO 0x00d5 2749c349dbc7Sjsg #define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 2750c349dbc7Sjsg #define mmRCC_PEER2_FB_OFFSET_HI 0x00d6 2751c349dbc7Sjsg #define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 2752c349dbc7Sjsg #define mmRCC_PEER2_FB_OFFSET_LO 0x00d7 2753c349dbc7Sjsg #define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 2754c349dbc7Sjsg #define mmRCC_PEER3_FB_OFFSET_HI 0x00d8 2755c349dbc7Sjsg #define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 2756c349dbc7Sjsg #define mmRCC_PEER3_FB_OFFSET_LO 0x00d9 2757c349dbc7Sjsg #define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 2758c349dbc7Sjsg #define mmRCC_CMN_LINK_CNTL 0x00de 2759c349dbc7Sjsg #define mmRCC_CMN_LINK_CNTL_BASE_IDX 2 2760c349dbc7Sjsg #define mmRCC_EP_REQUESTERID_RESTORE 0x00df 2761c349dbc7Sjsg #define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 2762c349dbc7Sjsg #define mmRCC_LTR_LSWITCH_CNTL 0x00e0 2763c349dbc7Sjsg #define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 2 2764c349dbc7Sjsg #define mmRCC_MH_ARB_CNTL 0x00e1 2765c349dbc7Sjsg #define mmRCC_MH_ARB_CNTL_BASE_IDX 2 2766c349dbc7Sjsg 2767c349dbc7Sjsg 2768c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 2769c349dbc7Sjsg // base address: 0x0 2770c349dbc7Sjsg #define mmBIF_MM_INDACCESS_CNTL 0x00e6 2771c349dbc7Sjsg #define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 2 2772c349dbc7Sjsg #define mmBUS_CNTL 0x00e7 2773c349dbc7Sjsg #define mmBUS_CNTL_BASE_IDX 2 2774c349dbc7Sjsg #define mmBIF_SCRATCH0 0x00e8 2775c349dbc7Sjsg #define mmBIF_SCRATCH0_BASE_IDX 2 2776c349dbc7Sjsg #define mmBIF_SCRATCH1 0x00e9 2777c349dbc7Sjsg #define mmBIF_SCRATCH1_BASE_IDX 2 2778c349dbc7Sjsg #define mmBX_RESET_EN 0x00ed 2779c349dbc7Sjsg #define mmBX_RESET_EN_BASE_IDX 2 2780c349dbc7Sjsg #define mmMM_CFGREGS_CNTL 0x00ee 2781c349dbc7Sjsg #define mmMM_CFGREGS_CNTL_BASE_IDX 2 2782c349dbc7Sjsg #define mmBX_RESET_CNTL 0x00f0 2783c349dbc7Sjsg #define mmBX_RESET_CNTL_BASE_IDX 2 2784c349dbc7Sjsg #define mmINTERRUPT_CNTL 0x00f1 2785c349dbc7Sjsg #define mmINTERRUPT_CNTL_BASE_IDX 2 2786c349dbc7Sjsg #define mmINTERRUPT_CNTL2 0x00f2 2787c349dbc7Sjsg #define mmINTERRUPT_CNTL2_BASE_IDX 2 2788c349dbc7Sjsg #define mmCLKREQB_PAD_CNTL 0x00f8 2789c349dbc7Sjsg #define mmCLKREQB_PAD_CNTL_BASE_IDX 2 2790c349dbc7Sjsg #define mmBIF_FEATURES_CONTROL_MISC 0x00fb 2791c349dbc7Sjsg #define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 2 2792c349dbc7Sjsg #define mmBIF_DOORBELL_CNTL 0x00fc 2793c349dbc7Sjsg #define mmBIF_DOORBELL_CNTL_BASE_IDX 2 2794c349dbc7Sjsg #define mmBIF_DOORBELL_INT_CNTL 0x00fd 2795c349dbc7Sjsg #define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2 2796c349dbc7Sjsg #define mmBIF_FB_EN 0x00ff 2797c349dbc7Sjsg #define mmBIF_FB_EN_BASE_IDX 2 2798c349dbc7Sjsg #define mmBIF_INTR_CNTL 0x0100 2799c349dbc7Sjsg #define mmBIF_INTR_CNTL_BASE_IDX 2 2800c349dbc7Sjsg #define mmBIF_MST_TRANS_PENDING_VF 0x0109 2801c349dbc7Sjsg #define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2 2802c349dbc7Sjsg #define mmBIF_SLV_TRANS_PENDING_VF 0x010a 2803c349dbc7Sjsg #define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 2804c349dbc7Sjsg #define mmBACO_CNTL 0x010b 2805c349dbc7Sjsg #define mmBACO_CNTL_BASE_IDX 2 2806c349dbc7Sjsg #define mmBIF_BACO_EXIT_TIME0 0x010c 2807c349dbc7Sjsg #define mmBIF_BACO_EXIT_TIME0_BASE_IDX 2 2808c349dbc7Sjsg #define mmBIF_BACO_EXIT_TIMER1 0x010d 2809c349dbc7Sjsg #define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 2 2810c349dbc7Sjsg #define mmBIF_BACO_EXIT_TIMER2 0x010e 2811c349dbc7Sjsg #define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 2 2812c349dbc7Sjsg #define mmBIF_BACO_EXIT_TIMER3 0x010f 2813c349dbc7Sjsg #define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 2 2814c349dbc7Sjsg #define mmBIF_BACO_EXIT_TIMER4 0x0110 2815c349dbc7Sjsg #define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 2 2816c349dbc7Sjsg #define mmMEM_TYPE_CNTL 0x0111 2817c349dbc7Sjsg #define mmMEM_TYPE_CNTL_BASE_IDX 2 2818c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_CNTL 0x0113 2819c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 2820c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_0 0x0114 2821c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_0_BASE_IDX 2 2822c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_1 0x0115 2823c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_1_BASE_IDX 2 2824c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_2 0x0116 2825c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_2_BASE_IDX 2 2826c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_3 0x0117 2827c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_3_BASE_IDX 2 2828c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_4 0x0118 2829c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_4_BASE_IDX 2 2830c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_5 0x0119 2831c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_5_BASE_IDX 2 2832c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_6 0x011a 2833c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_6_BASE_IDX 2 2834c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_7 0x011b 2835c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_7_BASE_IDX 2 2836c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_8 0x011c 2837c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_8_BASE_IDX 2 2838c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_9 0x011d 2839c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_9_BASE_IDX 2 2840c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_10 0x011e 2841c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_10_BASE_IDX 2 2842c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_11 0x011f 2843c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_11_BASE_IDX 2 2844c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_12 0x0120 2845c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_12_BASE_IDX 2 2846c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_13 0x0121 2847c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_13_BASE_IDX 2 2848c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_14 0x0122 2849c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_14_BASE_IDX 2 2850c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_15 0x0123 2851c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_15_BASE_IDX 2 2852c349dbc7Sjsg #define mmREMAP_HDP_MEM_FLUSH_CNTL 0x012d 2853c349dbc7Sjsg #define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 2854c349dbc7Sjsg #define mmREMAP_HDP_REG_FLUSH_CNTL 0x012e 2855c349dbc7Sjsg #define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 2856c349dbc7Sjsg #define mmBIF_RB_CNTL 0x012f 2857c349dbc7Sjsg #define mmBIF_RB_CNTL_BASE_IDX 2 2858c349dbc7Sjsg #define mmBIF_RB_BASE 0x0130 2859c349dbc7Sjsg #define mmBIF_RB_BASE_BASE_IDX 2 2860c349dbc7Sjsg #define mmBIF_RB_RPTR 0x0131 2861c349dbc7Sjsg #define mmBIF_RB_RPTR_BASE_IDX 2 2862c349dbc7Sjsg #define mmBIF_RB_WPTR 0x0132 2863c349dbc7Sjsg #define mmBIF_RB_WPTR_BASE_IDX 2 2864c349dbc7Sjsg #define mmBIF_RB_WPTR_ADDR_HI 0x0133 2865c349dbc7Sjsg #define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 2 2866c349dbc7Sjsg #define mmBIF_RB_WPTR_ADDR_LO 0x0134 2867c349dbc7Sjsg #define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 2 2868c349dbc7Sjsg #define mmMAILBOX_INDEX 0x0135 2869c349dbc7Sjsg #define mmMAILBOX_INDEX_BASE_IDX 2 2870c349dbc7Sjsg #define mmBIF_MP1_INTR_CTRL 0x0142 2871c349dbc7Sjsg #define mmBIF_MP1_INTR_CTRL_BASE_IDX 2 2872c349dbc7Sjsg #define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0143 2873c349dbc7Sjsg #define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 2 2874c349dbc7Sjsg #define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0144 2875c349dbc7Sjsg #define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 2 2876c349dbc7Sjsg #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0145 2877c349dbc7Sjsg #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 2 2878c349dbc7Sjsg #define mmBIF_PERSTB_PAD_CNTL 0x0148 2879c349dbc7Sjsg #define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 2 2880c349dbc7Sjsg #define mmBIF_PX_EN_PAD_CNTL 0x0149 2881c349dbc7Sjsg #define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 2 2882c349dbc7Sjsg #define mmBIF_REFPADKIN_PAD_CNTL 0x014a 2883c349dbc7Sjsg #define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 2884c349dbc7Sjsg #define mmBIF_CLKREQB_PAD_CNTL 0x014b 2885c349dbc7Sjsg #define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 2 2886c349dbc7Sjsg #define mmBIF_PWRBRK_PAD_CNTL 0x014c 2887c349dbc7Sjsg #define mmBIF_PWRBRK_PAD_CNTL_BASE_IDX 2 2888c349dbc7Sjsg #define mmBIF_WAKEB_PAD_CNTL 0x014d 2889c349dbc7Sjsg #define mmBIF_WAKEB_PAD_CNTL_BASE_IDX 2 2890c349dbc7Sjsg 2891c349dbc7Sjsg 2892c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 2893c349dbc7Sjsg // base address: 0x0 2894c349dbc7Sjsg #define mmBIF_BME_STATUS 0x00eb 2895c349dbc7Sjsg #define mmBIF_BME_STATUS_BASE_IDX 2 2896c349dbc7Sjsg #define mmBIF_ATOMIC_ERR_LOG 0x00ec 2897c349dbc7Sjsg #define mmBIF_ATOMIC_ERR_LOG_BASE_IDX 2 2898c349dbc7Sjsg #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2899c349dbc7Sjsg #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2900c349dbc7Sjsg #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2901c349dbc7Sjsg #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2902c349dbc7Sjsg #define mmDOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2903c349dbc7Sjsg #define mmDOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2904c349dbc7Sjsg #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2905c349dbc7Sjsg #define mmHDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2906c349dbc7Sjsg #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2907c349dbc7Sjsg #define mmHDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2908c349dbc7Sjsg #define mmGPU_HDP_FLUSH_REQ 0x0106 2909c349dbc7Sjsg #define mmGPU_HDP_FLUSH_REQ_BASE_IDX 2 2910c349dbc7Sjsg #define mmGPU_HDP_FLUSH_DONE 0x0107 2911c349dbc7Sjsg #define mmGPU_HDP_FLUSH_DONE_BASE_IDX 2 2912c349dbc7Sjsg #define mmBIF_TRANS_PENDING 0x0108 2913c349dbc7Sjsg #define mmBIF_TRANS_PENDING_BASE_IDX 2 2914c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_BYPASS 0x0112 2915c349dbc7Sjsg #define mmNBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 2916c349dbc7Sjsg #define mmMAILBOX_MSGBUF_TRN_DW0 0x0136 2917c349dbc7Sjsg #define mmMAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2918c349dbc7Sjsg #define mmMAILBOX_MSGBUF_TRN_DW1 0x0137 2919c349dbc7Sjsg #define mmMAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2920c349dbc7Sjsg #define mmMAILBOX_MSGBUF_TRN_DW2 0x0138 2921c349dbc7Sjsg #define mmMAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2922c349dbc7Sjsg #define mmMAILBOX_MSGBUF_TRN_DW3 0x0139 2923c349dbc7Sjsg #define mmMAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2924c349dbc7Sjsg #define mmMAILBOX_MSGBUF_RCV_DW0 0x013a 2925c349dbc7Sjsg #define mmMAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2926c349dbc7Sjsg #define mmMAILBOX_MSGBUF_RCV_DW1 0x013b 2927c349dbc7Sjsg #define mmMAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2928c349dbc7Sjsg #define mmMAILBOX_MSGBUF_RCV_DW2 0x013c 2929c349dbc7Sjsg #define mmMAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2930c349dbc7Sjsg #define mmMAILBOX_MSGBUF_RCV_DW3 0x013d 2931c349dbc7Sjsg #define mmMAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2932c349dbc7Sjsg #define mmMAILBOX_CONTROL 0x013e 2933c349dbc7Sjsg #define mmMAILBOX_CONTROL_BASE_IDX 2 2934c349dbc7Sjsg #define mmMAILBOX_INT_CNTL 0x013f 2935c349dbc7Sjsg #define mmMAILBOX_INT_CNTL_BASE_IDX 2 2936c349dbc7Sjsg #define mmBIF_VMHV_MAILBOX 0x0140 2937c349dbc7Sjsg #define mmBIF_VMHV_MAILBOX_BASE_IDX 2 2938c349dbc7Sjsg 2939c349dbc7Sjsg 2940c349dbc7Sjsg // addressBlock: nbio_nbif0_gdc_GDCDEC 2941c349dbc7Sjsg // base address: 0x0 2942c349dbc7Sjsg #define mmNGDC_SDP_PORT_CTRL 0x01c2 2943c349dbc7Sjsg #define mmNGDC_SDP_PORT_CTRL_BASE_IDX 2 2944c349dbc7Sjsg #define mmSHUB_REGS_IF_CTL 0x01c3 2945c349dbc7Sjsg #define mmSHUB_REGS_IF_CTL_BASE_IDX 2 2946c349dbc7Sjsg #define mmNGDC_MGCG_CTRL 0x01ca 2947c349dbc7Sjsg #define mmNGDC_MGCG_CTRL_BASE_IDX 2 2948c349dbc7Sjsg #define mmNGDC_RESERVED_0 0x01cb 2949c349dbc7Sjsg #define mmNGDC_RESERVED_0_BASE_IDX 2 2950c349dbc7Sjsg #define mmNGDC_RESERVED_1 0x01cc 2951c349dbc7Sjsg #define mmNGDC_RESERVED_1_BASE_IDX 2 2952c349dbc7Sjsg #define mmNGDC_SDP_PORT_CTRL_SOCCLK 0x01cd 2953c349dbc7Sjsg #define mmNGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 2 2954c349dbc7Sjsg #define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0 2955c349dbc7Sjsg #define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 2 2956c349dbc7Sjsg #define mmBIF_SDMA1_DOORBELL_RANGE 0x01d1 2957c349dbc7Sjsg #define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 2 2958c349dbc7Sjsg #define mmBIF_IH_DOORBELL_RANGE 0x01d2 2959c349dbc7Sjsg #define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 2 2960c349dbc7Sjsg #define mmBIF_MMSCH0_DOORBELL_RANGE 0x01d3 2961c349dbc7Sjsg #define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 2 2962c349dbc7Sjsg #define mmBIF_ACV_DOORBELL_RANGE 0x01d4 2963c349dbc7Sjsg #define mmBIF_ACV_DOORBELL_RANGE_BASE_IDX 2 2964c349dbc7Sjsg #define mmBIF_DOORBELL_FENCE_CNTL 0x01de 2965c349dbc7Sjsg #define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 2 2966c349dbc7Sjsg #define mmS2A_MISC_CNTL 0x01df 2967c349dbc7Sjsg #define mmS2A_MISC_CNTL_BASE_IDX 2 2968c349dbc7Sjsg 2969c349dbc7Sjsg 2970c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 2971c349dbc7Sjsg // base address: 0x0 2972c349dbc7Sjsg #define mmGFXMSIX_VECT0_ADDR_LO 0x0400 2973c349dbc7Sjsg #define mmGFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 2974c349dbc7Sjsg #define mmGFXMSIX_VECT0_ADDR_HI 0x0401 2975c349dbc7Sjsg #define mmGFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 2976c349dbc7Sjsg #define mmGFXMSIX_VECT0_MSG_DATA 0x0402 2977c349dbc7Sjsg #define mmGFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 2978c349dbc7Sjsg #define mmGFXMSIX_VECT0_CONTROL 0x0403 2979c349dbc7Sjsg #define mmGFXMSIX_VECT0_CONTROL_BASE_IDX 3 2980c349dbc7Sjsg #define mmGFXMSIX_VECT1_ADDR_LO 0x0404 2981c349dbc7Sjsg #define mmGFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 2982c349dbc7Sjsg #define mmGFXMSIX_VECT1_ADDR_HI 0x0405 2983c349dbc7Sjsg #define mmGFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 2984c349dbc7Sjsg #define mmGFXMSIX_VECT1_MSG_DATA 0x0406 2985c349dbc7Sjsg #define mmGFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 2986c349dbc7Sjsg #define mmGFXMSIX_VECT1_CONTROL 0x0407 2987c349dbc7Sjsg #define mmGFXMSIX_VECT1_CONTROL_BASE_IDX 3 2988c349dbc7Sjsg #define mmGFXMSIX_VECT2_ADDR_LO 0x0408 2989c349dbc7Sjsg #define mmGFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 2990c349dbc7Sjsg #define mmGFXMSIX_VECT2_ADDR_HI 0x0409 2991c349dbc7Sjsg #define mmGFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 2992c349dbc7Sjsg #define mmGFXMSIX_VECT2_MSG_DATA 0x040a 2993c349dbc7Sjsg #define mmGFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 2994c349dbc7Sjsg #define mmGFXMSIX_VECT2_CONTROL 0x040b 2995c349dbc7Sjsg #define mmGFXMSIX_VECT2_CONTROL_BASE_IDX 3 2996c349dbc7Sjsg #define mmGFXMSIX_PBA 0x0800 2997c349dbc7Sjsg #define mmGFXMSIX_PBA_BASE_IDX 3 2998c349dbc7Sjsg 2999c349dbc7Sjsg 3000c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC 3001c349dbc7Sjsg // base address: 0x0 3002c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 3003c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 3004c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 3005c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 3006c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 3007c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 3008c349dbc7Sjsg 3009c349dbc7Sjsg 3010c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 3011c349dbc7Sjsg // base address: 0x0 3012c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 3013c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 3014c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 3015c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 3016c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 3017c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3018c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 3019c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 3020c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3021c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3022c349dbc7Sjsg 3023c349dbc7Sjsg 3024c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 3025c349dbc7Sjsg // base address: 0x0 3026c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb 3027c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 3028c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec 3029c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3030c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3031c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3032c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3033c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3034c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3035c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3036c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3037c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3038c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3039c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3040c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 3041c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3042c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 3043c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3044c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 3045c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 3046c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3047c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3048c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 3049c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3050c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 3051c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3052c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 3053c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3054c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 3055c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3056c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a 3057c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3058c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b 3059c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3060c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c 3061c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3062c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d 3063c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3064c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e 3065c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 3066c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f 3067c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 3068c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 3069c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 3070c349dbc7Sjsg 3071c349dbc7Sjsg 3072c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 3073c349dbc7Sjsg // base address: 0x0 3074c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 3075c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3076c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 3077c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3078c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 3079c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3080c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 3081c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3082c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 3083c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3084c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 3085c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3086c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 3087c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3088c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 3089c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3090c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 3091c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3092c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 3093c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3094c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a 3095c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3096c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b 3097c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3098c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 3099c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 3 3100c349dbc7Sjsg 3101c349dbc7Sjsg 3102c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC 3103c349dbc7Sjsg // base address: 0x0 3104c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 3105c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 3106c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 3107c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 3108c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 3109c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 3110c349dbc7Sjsg 3111c349dbc7Sjsg 3112c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 3113c349dbc7Sjsg // base address: 0x0 3114c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 3115c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 3116c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 3117c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 3118c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 3119c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3120c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 3121c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 3122c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3123c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3124c349dbc7Sjsg 3125c349dbc7Sjsg 3126c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 3127c349dbc7Sjsg // base address: 0x0 3128c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb 3129c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 3130c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec 3131c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3132c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3133c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3134c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3135c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3136c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3137c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3138c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3139c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3140c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3141c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3142c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 3143c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3144c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 3145c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3146c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 3147c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 3148c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3149c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3150c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 3151c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3152c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 3153c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3154c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 3155c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3156c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 3157c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3158c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a 3159c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3160c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b 3161c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3162c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c 3163c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3164c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d 3165c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3166c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e 3167c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 3168c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f 3169c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 3170c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 3171c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 3172c349dbc7Sjsg 3173c349dbc7Sjsg 3174c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 3175c349dbc7Sjsg // base address: 0x0 3176c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 3177c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3178c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 3179c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3180c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 3181c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3182c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 3183c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3184c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 3185c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3186c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 3187c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3188c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 3189c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3190c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 3191c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3192c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 3193c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3194c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 3195c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3196c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a 3197c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3198c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b 3199c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3200c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 3201c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 3 3202c349dbc7Sjsg 3203c349dbc7Sjsg 3204c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC 3205c349dbc7Sjsg // base address: 0x0 3206c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 3207c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 3208c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 3209c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 3210c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 3211c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 3212c349dbc7Sjsg 3213c349dbc7Sjsg 3214c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 3215c349dbc7Sjsg // base address: 0x0 3216c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 3217c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 3218c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 3219c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 3220c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 3221c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3222c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 3223c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 3224c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3225c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3226c349dbc7Sjsg 3227c349dbc7Sjsg 3228c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 3229c349dbc7Sjsg // base address: 0x0 3230c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb 3231c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 3232c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec 3233c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3234c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3235c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3236c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3237c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3238c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3239c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3240c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3241c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3242c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3243c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3244c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 3245c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3246c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 3247c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3248c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 3249c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 3250c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3251c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3252c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 3253c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3254c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 3255c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3256c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 3257c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3258c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 3259c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3260c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a 3261c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3262c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b 3263c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3264c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c 3265c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3266c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d 3267c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3268c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e 3269c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 3270c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f 3271c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 3272c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 3273c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 3274c349dbc7Sjsg 3275c349dbc7Sjsg 3276c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 3277c349dbc7Sjsg // base address: 0x0 3278c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 3279c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3280c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 3281c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3282c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 3283c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3284c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 3285c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3286c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 3287c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3288c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 3289c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3290c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 3291c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3292c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 3293c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3294c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 3295c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3296c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 3297c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3298c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a 3299c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3300c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b 3301c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3302c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 3303c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 3 3304c349dbc7Sjsg 3305c349dbc7Sjsg 3306c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC 3307c349dbc7Sjsg // base address: 0x0 3308c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 3309c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 3310c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 3311c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 3312c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 3313c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 3314c349dbc7Sjsg 3315c349dbc7Sjsg 3316c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 3317c349dbc7Sjsg // base address: 0x0 3318c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 3319c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 3320c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 3321c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 3322c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 3323c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3324c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 3325c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 3326c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3327c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3328c349dbc7Sjsg 3329c349dbc7Sjsg 3330c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 3331c349dbc7Sjsg // base address: 0x0 3332c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb 3333c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 3334c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec 3335c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3336c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3337c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3338c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3339c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3340c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3341c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3342c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3343c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3344c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3345c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3346c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 3347c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3348c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 3349c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3350c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 3351c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 3352c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3353c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3354c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 3355c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3356c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 3357c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3358c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 3359c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3360c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 3361c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3362c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a 3363c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3364c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b 3365c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3366c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c 3367c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3368c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d 3369c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3370c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e 3371c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 3372c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f 3373c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 3374c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 3375c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 3376c349dbc7Sjsg 3377c349dbc7Sjsg 3378c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 3379c349dbc7Sjsg // base address: 0x0 3380c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 3381c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3382c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 3383c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3384c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 3385c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3386c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 3387c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3388c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 3389c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3390c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 3391c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3392c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 3393c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3394c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 3395c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3396c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 3397c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3398c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 3399c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3400c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a 3401c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3402c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b 3403c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3404c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 3405c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 3 3406c349dbc7Sjsg 3407c349dbc7Sjsg 3408c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC 3409c349dbc7Sjsg // base address: 0x0 3410c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 3411c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 3412c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 3413c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 3414c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 3415c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 3416c349dbc7Sjsg 3417c349dbc7Sjsg 3418c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 3419c349dbc7Sjsg // base address: 0x0 3420c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 3421c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 3422c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 3423c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 3424c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 3425c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3426c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 3427c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 3428c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3429c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3430c349dbc7Sjsg 3431c349dbc7Sjsg 3432c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 3433c349dbc7Sjsg // base address: 0x0 3434c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb 3435c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 3436c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec 3437c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3438c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3439c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3440c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3441c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3442c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3443c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3444c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3445c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3446c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3447c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3448c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 3449c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3450c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 3451c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3452c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 3453c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 3454c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3455c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3456c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 3457c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3458c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 3459c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3460c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 3461c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3462c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 3463c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3464c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a 3465c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3466c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b 3467c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3468c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c 3469c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3470c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d 3471c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3472c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e 3473c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 3474c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f 3475c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 3476c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 3477c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 3478c349dbc7Sjsg 3479c349dbc7Sjsg 3480c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 3481c349dbc7Sjsg // base address: 0x0 3482c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 3483c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3484c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 3485c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3486c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 3487c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3488c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 3489c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3490c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 3491c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3492c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 3493c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3494c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 3495c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3496c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 3497c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3498c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 3499c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3500c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 3501c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3502c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a 3503c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3504c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b 3505c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3506c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 3507c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 3 3508c349dbc7Sjsg 3509c349dbc7Sjsg 3510c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC 3511c349dbc7Sjsg // base address: 0x0 3512c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 3513c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 3514c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 3515c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 3516c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 3517c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 3518c349dbc7Sjsg 3519c349dbc7Sjsg 3520c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 3521c349dbc7Sjsg // base address: 0x0 3522c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 3523c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 3524c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 3525c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 3526c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 3527c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3528c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 3529c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 3530c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3531c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3532c349dbc7Sjsg 3533c349dbc7Sjsg 3534c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 3535c349dbc7Sjsg // base address: 0x0 3536c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb 3537c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 3538c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec 3539c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3540c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3541c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3542c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3543c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3544c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3545c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3546c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3547c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3548c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3549c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3550c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 3551c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3552c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 3553c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3554c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 3555c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 3556c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3557c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3558c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 3559c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3560c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 3561c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3562c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 3563c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3564c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 3565c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3566c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a 3567c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3568c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b 3569c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3570c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c 3571c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3572c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d 3573c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3574c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e 3575c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 3576c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f 3577c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 3578c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 3579c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 3580c349dbc7Sjsg 3581c349dbc7Sjsg 3582c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 3583c349dbc7Sjsg // base address: 0x0 3584c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 3585c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3586c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 3587c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3588c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 3589c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3590c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 3591c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3592c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 3593c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3594c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 3595c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3596c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 3597c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3598c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 3599c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3600c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 3601c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3602c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 3603c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3604c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a 3605c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3606c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b 3607c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3608c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 3609c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 3 3610c349dbc7Sjsg 3611c349dbc7Sjsg 3612c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC 3613c349dbc7Sjsg // base address: 0x0 3614c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 3615c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 3616c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 3617c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 3618c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 3619c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 3620c349dbc7Sjsg 3621c349dbc7Sjsg 3622c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 3623c349dbc7Sjsg // base address: 0x0 3624c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 3625c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 3626c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 3627c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 3628c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 3629c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3630c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 3631c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 3632c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3633c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3634c349dbc7Sjsg 3635c349dbc7Sjsg 3636c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 3637c349dbc7Sjsg // base address: 0x0 3638c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb 3639c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 3640c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec 3641c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3642c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3643c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3644c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3645c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3646c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3647c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3648c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3649c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3650c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3651c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3652c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 3653c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3654c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 3655c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3656c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 3657c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 3658c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3659c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3660c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 3661c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3662c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 3663c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3664c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 3665c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3666c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 3667c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3668c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a 3669c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3670c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b 3671c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3672c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c 3673c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3674c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d 3675c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3676c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e 3677c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 3678c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f 3679c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 3680c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 3681c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 3682c349dbc7Sjsg 3683c349dbc7Sjsg 3684c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 3685c349dbc7Sjsg // base address: 0x0 3686c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 3687c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3688c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 3689c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3690c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 3691c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3692c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 3693c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3694c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 3695c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3696c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 3697c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3698c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 3699c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3700c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 3701c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3702c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 3703c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3704c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 3705c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3706c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a 3707c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3708c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b 3709c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3710c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 3711c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 3 3712c349dbc7Sjsg 3713c349dbc7Sjsg 3714c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC 3715c349dbc7Sjsg // base address: 0x0 3716c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 3717c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 3718c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 3719c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 3720c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 3721c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 3722c349dbc7Sjsg 3723c349dbc7Sjsg 3724c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 3725c349dbc7Sjsg // base address: 0x0 3726c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 3727c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 3728c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 3729c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 3730c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 3731c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3732c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 3733c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 3734c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3735c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3736c349dbc7Sjsg 3737c349dbc7Sjsg 3738c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 3739c349dbc7Sjsg // base address: 0x0 3740c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb 3741c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 3742c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec 3743c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3744c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3745c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3746c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3747c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3748c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3749c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3750c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3751c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3752c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3753c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3754c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 3755c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3756c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 3757c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3758c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 3759c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 3760c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3761c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3762c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 3763c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3764c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 3765c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3766c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 3767c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3768c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 3769c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3770c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a 3771c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3772c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b 3773c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3774c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c 3775c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3776c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d 3777c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3778c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e 3779c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 3780c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f 3781c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 3782c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 3783c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 3784c349dbc7Sjsg 3785c349dbc7Sjsg 3786c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 3787c349dbc7Sjsg // base address: 0x0 3788c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 3789c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3790c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 3791c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3792c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 3793c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3794c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 3795c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3796c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 3797c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3798c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 3799c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3800c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 3801c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3802c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 3803c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3804c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 3805c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3806c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 3807c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3808c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a 3809c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3810c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b 3811c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3812c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 3813c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 3 3814c349dbc7Sjsg 3815c349dbc7Sjsg 3816c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC 3817c349dbc7Sjsg // base address: 0x0 3818c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000 3819c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0 3820c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001 3821c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0 3822c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006 3823c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0 3824c349dbc7Sjsg 3825c349dbc7Sjsg 3826c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 3827c349dbc7Sjsg // base address: 0x0 3828c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0x0085 3829c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_BASE_IDX 2 3830c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0x00c0 3831c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_BASE_IDX 2 3832c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0x00c3 3833c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3834c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0x00c4 3835c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_BASE_IDX 2 3836c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3837c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3838c349dbc7Sjsg 3839c349dbc7Sjsg 3840c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 3841c349dbc7Sjsg // base address: 0x0 3842c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb 3843c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2 3844c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec 3845c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3846c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3847c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3848c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3849c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3850c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3851c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3852c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3853c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3854c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3855c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3856c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106 3857c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3858c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107 3859c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3860c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108 3861c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2 3862c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3863c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3864c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136 3865c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3866c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137 3867c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3868c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138 3869c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3870c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139 3871c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3872c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a 3873c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3874c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b 3875c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3876c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c 3877c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3878c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d 3879c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3880c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e 3881c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2 3882c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f 3883c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2 3884c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140 3885c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2 3886c349dbc7Sjsg 3887c349dbc7Sjsg 3888c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 3889c349dbc7Sjsg // base address: 0x0 3890c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0x0400 3891c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3892c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0x0401 3893c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3894c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0x0402 3895c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3896c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0x0403 3897c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 3898c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0x0404 3899c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 3900c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0x0405 3901c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 3902c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0x0406 3903c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 3904c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0x0407 3905c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 3906c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0x0408 3907c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 3908c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0x0409 3909c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 3910c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0x040a 3911c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 3912c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0x040b 3913c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 3914c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0x0800 3915c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_BASE_IDX 3 3916c349dbc7Sjsg 3917c349dbc7Sjsg 3918c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC 3919c349dbc7Sjsg // base address: 0x0 3920c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000 3921c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0 3922c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001 3923c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0 3924c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006 3925c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0 3926c349dbc7Sjsg 3927c349dbc7Sjsg 3928c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 3929c349dbc7Sjsg // base address: 0x0 3930c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0x0085 3931c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_BASE_IDX 2 3932c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0x00c0 3933c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_BASE_IDX 2 3934c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0x00c3 3935c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_BASE_IDX 2 3936c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0x00c4 3937c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_BASE_IDX 2 3938c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0x00c5 3939c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 3940c349dbc7Sjsg 3941c349dbc7Sjsg 3942c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 3943c349dbc7Sjsg // base address: 0x0 3944c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb 3945c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2 3946c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec 3947c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3948c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3949c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3950c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3951c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3952c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3953c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3954c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3955c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3956c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3957c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3958c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106 3959c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3960c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107 3961c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3962c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108 3963c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2 3964c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 3965c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 3966c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136 3967c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3968c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137 3969c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3970c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138 3971c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3972c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139 3973c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3974c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a 3975c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3976c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b 3977c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3978c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c 3979c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3980c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d 3981c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3982c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e 3983c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2 3984c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f 3985c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2 3986c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140 3987c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2 3988c349dbc7Sjsg 3989c349dbc7Sjsg 3990c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 3991c349dbc7Sjsg // base address: 0x0 3992c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0x0400 3993c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 3994c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0x0401 3995c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 3996c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0x0402 3997c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 3998c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0x0403 3999c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 4000c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0x0404 4001c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 4002c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0x0405 4003c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 4004c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0x0406 4005c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 4006c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0x0407 4007c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 4008c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0x0408 4009c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 4010c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0x0409 4011c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 4012c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0x040a 4013c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 4014c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0x040b 4015c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 4016c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0x0800 4017c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_BASE_IDX 3 4018c349dbc7Sjsg 4019c349dbc7Sjsg 4020c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC 4021c349dbc7Sjsg // base address: 0x0 4022c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000 4023c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0 4024c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001 4025c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0 4026c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006 4027c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0 4028c349dbc7Sjsg 4029c349dbc7Sjsg 4030c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 4031c349dbc7Sjsg // base address: 0x0 4032c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0x0085 4033c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_BASE_IDX 2 4034c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0x00c0 4035c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_BASE_IDX 2 4036c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0x00c3 4037c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_BASE_IDX 2 4038c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0x00c4 4039c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_BASE_IDX 2 4040c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0x00c5 4041c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 4042c349dbc7Sjsg 4043c349dbc7Sjsg 4044c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 4045c349dbc7Sjsg // base address: 0x0 4046c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb 4047c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2 4048c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec 4049c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 4050c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 4051c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 4052c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 4053c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 4054c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 4055c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 4056c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 4057c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4058c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 4059c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4060c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106 4061c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2 4062c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107 4063c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2 4064c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108 4065c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2 4066c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 4067c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 4068c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136 4069c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 4070c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137 4071c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 4072c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138 4073c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 4074c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139 4075c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 4076c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a 4077c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 4078c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b 4079c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 4080c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c 4081c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 4082c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d 4083c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 4084c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e 4085c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2 4086c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f 4087c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2 4088c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140 4089c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2 4090c349dbc7Sjsg 4091c349dbc7Sjsg 4092c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 4093c349dbc7Sjsg // base address: 0x0 4094c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0x0400 4095c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 4096c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0x0401 4097c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 4098c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0x0402 4099c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 4100c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0x0403 4101c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 4102c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0x0404 4103c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 4104c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0x0405 4105c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 4106c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0x0406 4107c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 4108c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0x0407 4109c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 4110c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0x0408 4111c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 4112c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0x0409 4113c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 4114c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0x040a 4115c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 4116c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0x040b 4117c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 4118c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0x0800 4119c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_BASE_IDX 3 4120c349dbc7Sjsg 4121c349dbc7Sjsg 4122c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC 4123c349dbc7Sjsg // base address: 0x0 4124c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000 4125c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0 4126c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001 4127c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0 4128c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006 4129c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0 4130c349dbc7Sjsg 4131c349dbc7Sjsg 4132c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 4133c349dbc7Sjsg // base address: 0x0 4134c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0x0085 4135c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_BASE_IDX 2 4136c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0x00c0 4137c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_BASE_IDX 2 4138c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0x00c3 4139c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_BASE_IDX 2 4140c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0x00c4 4141c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_BASE_IDX 2 4142c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0x00c5 4143c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 4144c349dbc7Sjsg 4145c349dbc7Sjsg 4146c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 4147c349dbc7Sjsg // base address: 0x0 4148c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb 4149c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2 4150c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec 4151c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 4152c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 4153c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 4154c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 4155c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 4156c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 4157c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 4158c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 4159c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4160c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 4161c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4162c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106 4163c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2 4164c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107 4165c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2 4166c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108 4167c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2 4168c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 4169c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 4170c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136 4171c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 4172c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137 4173c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 4174c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138 4175c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 4176c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139 4177c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 4178c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a 4179c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 4180c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b 4181c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 4182c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c 4183c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 4184c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d 4185c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 4186c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e 4187c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2 4188c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f 4189c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2 4190c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140 4191c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2 4192c349dbc7Sjsg 4193c349dbc7Sjsg 4194c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 4195c349dbc7Sjsg // base address: 0x0 4196c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0x0400 4197c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 4198c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0x0401 4199c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 4200c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0x0402 4201c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 4202c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0x0403 4203c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 4204c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0x0404 4205c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 4206c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0x0405 4207c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 4208c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0x0406 4209c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 4210c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0x0407 4211c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 4212c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0x0408 4213c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 4214c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0x0409 4215c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 4216c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0x040a 4217c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 4218c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0x040b 4219c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 4220c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0x0800 4221c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_BASE_IDX 3 4222c349dbc7Sjsg 4223c349dbc7Sjsg 4224c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC 4225c349dbc7Sjsg // base address: 0x0 4226c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000 4227c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0 4228c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001 4229c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0 4230c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006 4231c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0 4232c349dbc7Sjsg 4233c349dbc7Sjsg 4234c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 4235c349dbc7Sjsg // base address: 0x0 4236c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0x0085 4237c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_BASE_IDX 2 4238c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0x00c0 4239c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_BASE_IDX 2 4240c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0x00c3 4241c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_BASE_IDX 2 4242c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0x00c4 4243c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_BASE_IDX 2 4244c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0x00c5 4245c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 4246c349dbc7Sjsg 4247c349dbc7Sjsg 4248c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 4249c349dbc7Sjsg // base address: 0x0 4250c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb 4251c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2 4252c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec 4253c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 4254c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 4255c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 4256c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 4257c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 4258c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 4259c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 4260c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 4261c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4262c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 4263c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4264c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106 4265c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2 4266c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107 4267c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2 4268c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108 4269c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2 4270c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 4271c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 4272c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136 4273c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 4274c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137 4275c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 4276c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138 4277c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 4278c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139 4279c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 4280c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a 4281c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 4282c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b 4283c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 4284c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c 4285c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 4286c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d 4287c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 4288c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e 4289c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2 4290c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f 4291c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2 4292c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140 4293c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2 4294c349dbc7Sjsg 4295c349dbc7Sjsg 4296c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 4297c349dbc7Sjsg // base address: 0x0 4298c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0x0400 4299c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 4300c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0x0401 4301c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 4302c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0x0402 4303c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 4304c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0x0403 4305c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 4306c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0x0404 4307c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 4308c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0x0405 4309c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 4310c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0x0406 4311c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 4312c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0x0407 4313c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 4314c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0x0408 4315c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 4316c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0x0409 4317c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 4318c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0x040a 4319c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 4320c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0x040b 4321c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 4322c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0x0800 4323c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_BASE_IDX 3 4324c349dbc7Sjsg 4325c349dbc7Sjsg 4326c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC 4327c349dbc7Sjsg // base address: 0x0 4328c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000 4329c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0 4330c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001 4331c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0 4332c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006 4333c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0 4334c349dbc7Sjsg 4335c349dbc7Sjsg 4336c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 4337c349dbc7Sjsg // base address: 0x0 4338c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0x0085 4339c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_BASE_IDX 2 4340c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0x00c0 4341c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_BASE_IDX 2 4342c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0x00c3 4343c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_BASE_IDX 2 4344c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0x00c4 4345c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_BASE_IDX 2 4346c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0x00c5 4347c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 4348c349dbc7Sjsg 4349c349dbc7Sjsg 4350c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 4351c349dbc7Sjsg // base address: 0x0 4352c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb 4353c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2 4354c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec 4355c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 4356c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 4357c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 4358c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 4359c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 4360c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 4361c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 4362c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 4363c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4364c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 4365c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4366c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106 4367c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2 4368c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107 4369c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2 4370c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108 4371c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2 4372c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 4373c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 4374c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136 4375c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 4376c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137 4377c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 4378c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138 4379c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 4380c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139 4381c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 4382c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a 4383c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 4384c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b 4385c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 4386c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c 4387c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 4388c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d 4389c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 4390c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e 4391c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2 4392c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f 4393c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2 4394c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140 4395c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2 4396c349dbc7Sjsg 4397c349dbc7Sjsg 4398c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 4399c349dbc7Sjsg // base address: 0x0 4400c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0x0400 4401c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 4402c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0x0401 4403c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 4404c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0x0402 4405c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 4406c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0x0403 4407c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 4408c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0x0404 4409c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 4410c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0x0405 4411c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 4412c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0x0406 4413c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 4414c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0x0407 4415c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 4416c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0x0408 4417c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 4418c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0x0409 4419c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 4420c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0x040a 4421c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 4422c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0x040b 4423c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 4424c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0x0800 4425c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_BASE_IDX 3 4426c349dbc7Sjsg 4427c349dbc7Sjsg 4428c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC 4429c349dbc7Sjsg // base address: 0x0 4430c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000 4431c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0 4432c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001 4433c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0 4434c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006 4435c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0 4436c349dbc7Sjsg 4437c349dbc7Sjsg 4438c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 4439c349dbc7Sjsg // base address: 0x0 4440c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0x0085 4441c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_BASE_IDX 2 4442c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0x00c0 4443c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_BASE_IDX 2 4444c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0x00c3 4445c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_BASE_IDX 2 4446c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0x00c4 4447c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_BASE_IDX 2 4448c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0x00c5 4449c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 4450c349dbc7Sjsg 4451c349dbc7Sjsg 4452c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 4453c349dbc7Sjsg // base address: 0x0 4454c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb 4455c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2 4456c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec 4457c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 4458c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 4459c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 4460c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 4461c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 4462c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 4463c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 4464c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 4465c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4466c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 4467c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4468c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106 4469c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2 4470c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107 4471c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2 4472c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108 4473c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2 4474c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 4475c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 4476c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136 4477c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 4478c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137 4479c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 4480c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138 4481c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 4482c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139 4483c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 4484c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a 4485c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 4486c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b 4487c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 4488c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c 4489c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 4490c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d 4491c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 4492c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e 4493c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2 4494c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f 4495c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2 4496c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140 4497c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2 4498c349dbc7Sjsg 4499c349dbc7Sjsg 4500c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 4501c349dbc7Sjsg // base address: 0x0 4502c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0x0400 4503c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 4504c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0x0401 4505c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 4506c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0x0402 4507c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 4508c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0x0403 4509c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 4510c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0x0404 4511c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 4512c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0x0405 4513c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 4514c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0x0406 4515c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 4516c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0x0407 4517c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 4518c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0x0408 4519c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 4520c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0x0409 4521c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 4522c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0x040a 4523c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 4524c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0x040b 4525c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 4526c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0x0800 4527c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_BASE_IDX 3 4528c349dbc7Sjsg 4529c349dbc7Sjsg 4530c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC 4531c349dbc7Sjsg // base address: 0x0 4532c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000 4533c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0 4534c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001 4535c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0 4536c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006 4537c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0 4538c349dbc7Sjsg 4539c349dbc7Sjsg 4540c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 4541c349dbc7Sjsg // base address: 0x0 4542c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0x0085 4543c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_BASE_IDX 2 4544c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0x00c0 4545c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_BASE_IDX 2 4546c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0x00c3 4547c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_BASE_IDX 2 4548c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0x00c4 4549c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_BASE_IDX 2 4550c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0x00c5 4551c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 4552c349dbc7Sjsg 4553c349dbc7Sjsg 4554c349dbc7Sjsg // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 4555c349dbc7Sjsg // base address: 0x0 4556c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb 4557c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2 4558c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec 4559c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 4560c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 4561c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 4562c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 4563c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 4564c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 4565c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 4566c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 4567c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4568c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 4569c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 4570c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106 4571c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2 4572c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107 4573c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2 4574c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108 4575c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2 4576c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 4577c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 4578c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136 4579c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 4580c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137 4581c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 4582c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138 4583c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 4584c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139 4585c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 4586c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a 4587c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 4588c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b 4589c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 4590c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c 4591c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 4592c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d 4593c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 4594c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e 4595c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2 4596c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f 4597c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2 4598c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140 4599c349dbc7Sjsg #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2 4600c349dbc7Sjsg 4601c349dbc7Sjsg 4602c349dbc7Sjsg // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 4603c349dbc7Sjsg // base address: 0x0 4604c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0x0400 4605c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 4606c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0x0401 4607c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 4608c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0x0402 4609c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 4610c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0x0403 4611c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 4612c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0x0404 4613c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 4614c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0x0405 4615c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 4616c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0x0406 4617c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 4618c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0x0407 4619c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 4620c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0x0408 4621c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 4622c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0x0409 4623c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 4624c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0x040a 4625c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 4626c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0x040b 4627c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 4628c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0x0800 4629c349dbc7Sjsg #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_BASE_IDX 3 4630c349dbc7Sjsg 4631c349dbc7Sjsg #endif 4632