1*c349dbc7Sjsg /* 2*c349dbc7Sjsg * Copyright (C) 2018 Advanced Micro Devices, Inc. 3*c349dbc7Sjsg * 4*c349dbc7Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*c349dbc7Sjsg * copy of this software and associated documentation files (the "Software"), 6*c349dbc7Sjsg * to deal in the Software without restriction, including without limitation 7*c349dbc7Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*c349dbc7Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9*c349dbc7Sjsg * Software is furnished to do so, subject to the following conditions: 10*c349dbc7Sjsg * 11*c349dbc7Sjsg * The above copyright notice and this permission notice shall be included 12*c349dbc7Sjsg * in all copies or substantial portions of the Software. 13*c349dbc7Sjsg * 14*c349dbc7Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15*c349dbc7Sjsg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*c349dbc7Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*c349dbc7Sjsg * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18*c349dbc7Sjsg * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19*c349dbc7Sjsg * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20*c349dbc7Sjsg */ 21*c349dbc7Sjsg #ifndef _sdma0_4_2_0_OFFSET_HEADER 22*c349dbc7Sjsg #define _sdma0_4_2_0_OFFSET_HEADER 23*c349dbc7Sjsg 24*c349dbc7Sjsg 25*c349dbc7Sjsg 26*c349dbc7Sjsg // addressBlock: sdma0_sdma0dec 27*c349dbc7Sjsg // base address: 0x4980 28*c349dbc7Sjsg #define mmSDMA0_UCODE_ADDR 0x0000 29*c349dbc7Sjsg #define mmSDMA0_UCODE_ADDR_BASE_IDX 0 30*c349dbc7Sjsg #define mmSDMA0_UCODE_DATA 0x0001 31*c349dbc7Sjsg #define mmSDMA0_UCODE_DATA_BASE_IDX 0 32*c349dbc7Sjsg #define mmSDMA0_VM_CNTL 0x0004 33*c349dbc7Sjsg #define mmSDMA0_VM_CNTL_BASE_IDX 0 34*c349dbc7Sjsg #define mmSDMA0_VM_CTX_LO 0x0005 35*c349dbc7Sjsg #define mmSDMA0_VM_CTX_LO_BASE_IDX 0 36*c349dbc7Sjsg #define mmSDMA0_VM_CTX_HI 0x0006 37*c349dbc7Sjsg #define mmSDMA0_VM_CTX_HI_BASE_IDX 0 38*c349dbc7Sjsg #define mmSDMA0_ACTIVE_FCN_ID 0x0007 39*c349dbc7Sjsg #define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0 40*c349dbc7Sjsg #define mmSDMA0_VM_CTX_CNTL 0x0008 41*c349dbc7Sjsg #define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0 42*c349dbc7Sjsg #define mmSDMA0_VIRT_RESET_REQ 0x0009 43*c349dbc7Sjsg #define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0 44*c349dbc7Sjsg #define mmSDMA0_VF_ENABLE 0x000a 45*c349dbc7Sjsg #define mmSDMA0_VF_ENABLE_BASE_IDX 0 46*c349dbc7Sjsg #define mmSDMA0_CONTEXT_REG_TYPE0 0x000b 47*c349dbc7Sjsg #define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0 48*c349dbc7Sjsg #define mmSDMA0_CONTEXT_REG_TYPE1 0x000c 49*c349dbc7Sjsg #define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0 50*c349dbc7Sjsg #define mmSDMA0_CONTEXT_REG_TYPE2 0x000d 51*c349dbc7Sjsg #define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0 52*c349dbc7Sjsg #define mmSDMA0_CONTEXT_REG_TYPE3 0x000e 53*c349dbc7Sjsg #define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0 54*c349dbc7Sjsg #define mmSDMA0_PUB_REG_TYPE0 0x000f 55*c349dbc7Sjsg #define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0 56*c349dbc7Sjsg #define mmSDMA0_PUB_REG_TYPE1 0x0010 57*c349dbc7Sjsg #define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0 58*c349dbc7Sjsg #define mmSDMA0_PUB_REG_TYPE2 0x0011 59*c349dbc7Sjsg #define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0 60*c349dbc7Sjsg #define mmSDMA0_PUB_REG_TYPE3 0x0012 61*c349dbc7Sjsg #define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0 62*c349dbc7Sjsg #define mmSDMA0_MMHUB_CNTL 0x0013 63*c349dbc7Sjsg #define mmSDMA0_MMHUB_CNTL_BASE_IDX 0 64*c349dbc7Sjsg #define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 65*c349dbc7Sjsg #define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 66*c349dbc7Sjsg #define mmSDMA0_POWER_CNTL 0x001a 67*c349dbc7Sjsg #define mmSDMA0_POWER_CNTL_BASE_IDX 0 68*c349dbc7Sjsg #define mmSDMA0_CLK_CTRL 0x001b 69*c349dbc7Sjsg #define mmSDMA0_CLK_CTRL_BASE_IDX 0 70*c349dbc7Sjsg #define mmSDMA0_CNTL 0x001c 71*c349dbc7Sjsg #define mmSDMA0_CNTL_BASE_IDX 0 72*c349dbc7Sjsg #define mmSDMA0_CHICKEN_BITS 0x001d 73*c349dbc7Sjsg #define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 74*c349dbc7Sjsg #define mmSDMA0_GB_ADDR_CONFIG 0x001e 75*c349dbc7Sjsg #define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 76*c349dbc7Sjsg #define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f 77*c349dbc7Sjsg #define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 78*c349dbc7Sjsg #define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 79*c349dbc7Sjsg #define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 80*c349dbc7Sjsg #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 81*c349dbc7Sjsg #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 82*c349dbc7Sjsg #define mmSDMA0_RB_RPTR_FETCH 0x0022 83*c349dbc7Sjsg #define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 84*c349dbc7Sjsg #define mmSDMA0_IB_OFFSET_FETCH 0x0023 85*c349dbc7Sjsg #define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 86*c349dbc7Sjsg #define mmSDMA0_PROGRAM 0x0024 87*c349dbc7Sjsg #define mmSDMA0_PROGRAM_BASE_IDX 0 88*c349dbc7Sjsg #define mmSDMA0_STATUS_REG 0x0025 89*c349dbc7Sjsg #define mmSDMA0_STATUS_REG_BASE_IDX 0 90*c349dbc7Sjsg #define mmSDMA0_STATUS1_REG 0x0026 91*c349dbc7Sjsg #define mmSDMA0_STATUS1_REG_BASE_IDX 0 92*c349dbc7Sjsg #define mmSDMA0_RD_BURST_CNTL 0x0027 93*c349dbc7Sjsg #define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 94*c349dbc7Sjsg #define mmSDMA0_HBM_PAGE_CONFIG 0x0028 95*c349dbc7Sjsg #define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 96*c349dbc7Sjsg #define mmSDMA0_UCODE_CHECKSUM 0x0029 97*c349dbc7Sjsg #define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 98*c349dbc7Sjsg #define mmSDMA0_F32_CNTL 0x002a 99*c349dbc7Sjsg #define mmSDMA0_F32_CNTL_BASE_IDX 0 100*c349dbc7Sjsg #define mmSDMA0_FREEZE 0x002b 101*c349dbc7Sjsg #define mmSDMA0_FREEZE_BASE_IDX 0 102*c349dbc7Sjsg #define mmSDMA0_PHASE0_QUANTUM 0x002c 103*c349dbc7Sjsg #define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 104*c349dbc7Sjsg #define mmSDMA0_PHASE1_QUANTUM 0x002d 105*c349dbc7Sjsg #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 106*c349dbc7Sjsg #define mmSDMA_POWER_GATING 0x002e 107*c349dbc7Sjsg #define mmSDMA_POWER_GATING_BASE_IDX 0 108*c349dbc7Sjsg #define mmSDMA_PGFSM_CONFIG 0x002f 109*c349dbc7Sjsg #define mmSDMA_PGFSM_CONFIG_BASE_IDX 0 110*c349dbc7Sjsg #define mmSDMA_PGFSM_WRITE 0x0030 111*c349dbc7Sjsg #define mmSDMA_PGFSM_WRITE_BASE_IDX 0 112*c349dbc7Sjsg #define mmSDMA_PGFSM_READ 0x0031 113*c349dbc7Sjsg #define mmSDMA_PGFSM_READ_BASE_IDX 0 114*c349dbc7Sjsg #define mmSDMA0_EDC_CONFIG 0x0032 115*c349dbc7Sjsg #define mmSDMA0_EDC_CONFIG_BASE_IDX 0 116*c349dbc7Sjsg #define mmSDMA0_BA_THRESHOLD 0x0033 117*c349dbc7Sjsg #define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 118*c349dbc7Sjsg #define mmSDMA0_ID 0x0034 119*c349dbc7Sjsg #define mmSDMA0_ID_BASE_IDX 0 120*c349dbc7Sjsg #define mmSDMA0_VERSION 0x0035 121*c349dbc7Sjsg #define mmSDMA0_VERSION_BASE_IDX 0 122*c349dbc7Sjsg #define mmSDMA0_EDC_COUNTER 0x0036 123*c349dbc7Sjsg #define mmSDMA0_EDC_COUNTER_BASE_IDX 0 124*c349dbc7Sjsg #define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 125*c349dbc7Sjsg #define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 126*c349dbc7Sjsg #define mmSDMA0_STATUS2_REG 0x0038 127*c349dbc7Sjsg #define mmSDMA0_STATUS2_REG_BASE_IDX 0 128*c349dbc7Sjsg #define mmSDMA0_ATOMIC_CNTL 0x0039 129*c349dbc7Sjsg #define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 130*c349dbc7Sjsg #define mmSDMA0_ATOMIC_PREOP_LO 0x003a 131*c349dbc7Sjsg #define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 132*c349dbc7Sjsg #define mmSDMA0_ATOMIC_PREOP_HI 0x003b 133*c349dbc7Sjsg #define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 134*c349dbc7Sjsg #define mmSDMA0_UTCL1_CNTL 0x003c 135*c349dbc7Sjsg #define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 136*c349dbc7Sjsg #define mmSDMA0_UTCL1_WATERMK 0x003d 137*c349dbc7Sjsg #define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 138*c349dbc7Sjsg #define mmSDMA0_UTCL1_RD_STATUS 0x003e 139*c349dbc7Sjsg #define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 140*c349dbc7Sjsg #define mmSDMA0_UTCL1_WR_STATUS 0x003f 141*c349dbc7Sjsg #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 142*c349dbc7Sjsg #define mmSDMA0_UTCL1_INV0 0x0040 143*c349dbc7Sjsg #define mmSDMA0_UTCL1_INV0_BASE_IDX 0 144*c349dbc7Sjsg #define mmSDMA0_UTCL1_INV1 0x0041 145*c349dbc7Sjsg #define mmSDMA0_UTCL1_INV1_BASE_IDX 0 146*c349dbc7Sjsg #define mmSDMA0_UTCL1_INV2 0x0042 147*c349dbc7Sjsg #define mmSDMA0_UTCL1_INV2_BASE_IDX 0 148*c349dbc7Sjsg #define mmSDMA0_UTCL1_RD_XNACK0 0x0043 149*c349dbc7Sjsg #define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 150*c349dbc7Sjsg #define mmSDMA0_UTCL1_RD_XNACK1 0x0044 151*c349dbc7Sjsg #define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 152*c349dbc7Sjsg #define mmSDMA0_UTCL1_WR_XNACK0 0x0045 153*c349dbc7Sjsg #define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 154*c349dbc7Sjsg #define mmSDMA0_UTCL1_WR_XNACK1 0x0046 155*c349dbc7Sjsg #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 156*c349dbc7Sjsg #define mmSDMA0_UTCL1_TIMEOUT 0x0047 157*c349dbc7Sjsg #define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 158*c349dbc7Sjsg #define mmSDMA0_UTCL1_PAGE 0x0048 159*c349dbc7Sjsg #define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 160*c349dbc7Sjsg #define mmSDMA0_POWER_CNTL_IDLE 0x0049 161*c349dbc7Sjsg #define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 162*c349dbc7Sjsg #define mmSDMA0_RELAX_ORDERING_LUT 0x004a 163*c349dbc7Sjsg #define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 164*c349dbc7Sjsg #define mmSDMA0_CHICKEN_BITS_2 0x004b 165*c349dbc7Sjsg #define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 166*c349dbc7Sjsg #define mmSDMA0_STATUS3_REG 0x004c 167*c349dbc7Sjsg #define mmSDMA0_STATUS3_REG_BASE_IDX 0 168*c349dbc7Sjsg #define mmSDMA0_PHYSICAL_ADDR_LO 0x004d 169*c349dbc7Sjsg #define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 170*c349dbc7Sjsg #define mmSDMA0_PHYSICAL_ADDR_HI 0x004e 171*c349dbc7Sjsg #define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 172*c349dbc7Sjsg #define mmSDMA0_PHASE2_QUANTUM 0x004f 173*c349dbc7Sjsg #define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0 174*c349dbc7Sjsg #define mmSDMA0_ERROR_LOG 0x0050 175*c349dbc7Sjsg #define mmSDMA0_ERROR_LOG_BASE_IDX 0 176*c349dbc7Sjsg #define mmSDMA0_PUB_DUMMY_REG0 0x0051 177*c349dbc7Sjsg #define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 178*c349dbc7Sjsg #define mmSDMA0_PUB_DUMMY_REG1 0x0052 179*c349dbc7Sjsg #define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 180*c349dbc7Sjsg #define mmSDMA0_PUB_DUMMY_REG2 0x0053 181*c349dbc7Sjsg #define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 182*c349dbc7Sjsg #define mmSDMA0_PUB_DUMMY_REG3 0x0054 183*c349dbc7Sjsg #define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 184*c349dbc7Sjsg #define mmSDMA0_F32_COUNTER 0x0055 185*c349dbc7Sjsg #define mmSDMA0_F32_COUNTER_BASE_IDX 0 186*c349dbc7Sjsg #define mmSDMA0_PERFMON_CNTL 0x0057 187*c349dbc7Sjsg #define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 188*c349dbc7Sjsg #define mmSDMA0_PERFCOUNTER0_RESULT 0x0058 189*c349dbc7Sjsg #define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0 190*c349dbc7Sjsg #define mmSDMA0_PERFCOUNTER1_RESULT 0x0059 191*c349dbc7Sjsg #define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0 192*c349dbc7Sjsg #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a 193*c349dbc7Sjsg #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 194*c349dbc7Sjsg #define mmSDMA0_CRD_CNTL 0x005b 195*c349dbc7Sjsg #define mmSDMA0_CRD_CNTL_BASE_IDX 0 196*c349dbc7Sjsg #define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d 197*c349dbc7Sjsg #define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 198*c349dbc7Sjsg #define mmSDMA0_ULV_CNTL 0x005e 199*c349dbc7Sjsg #define mmSDMA0_ULV_CNTL_BASE_IDX 0 200*c349dbc7Sjsg #define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 201*c349dbc7Sjsg #define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 202*c349dbc7Sjsg #define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 203*c349dbc7Sjsg #define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 204*c349dbc7Sjsg #define mmSDMA0_GFX_RB_CNTL 0x0080 205*c349dbc7Sjsg #define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 206*c349dbc7Sjsg #define mmSDMA0_GFX_RB_BASE 0x0081 207*c349dbc7Sjsg #define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 208*c349dbc7Sjsg #define mmSDMA0_GFX_RB_BASE_HI 0x0082 209*c349dbc7Sjsg #define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 210*c349dbc7Sjsg #define mmSDMA0_GFX_RB_RPTR 0x0083 211*c349dbc7Sjsg #define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 212*c349dbc7Sjsg #define mmSDMA0_GFX_RB_RPTR_HI 0x0084 213*c349dbc7Sjsg #define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 214*c349dbc7Sjsg #define mmSDMA0_GFX_RB_WPTR 0x0085 215*c349dbc7Sjsg #define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 216*c349dbc7Sjsg #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 217*c349dbc7Sjsg #define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 218*c349dbc7Sjsg #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 219*c349dbc7Sjsg #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 220*c349dbc7Sjsg #define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 221*c349dbc7Sjsg #define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 222*c349dbc7Sjsg #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 223*c349dbc7Sjsg #define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 224*c349dbc7Sjsg #define mmSDMA0_GFX_IB_CNTL 0x008a 225*c349dbc7Sjsg #define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 226*c349dbc7Sjsg #define mmSDMA0_GFX_IB_RPTR 0x008b 227*c349dbc7Sjsg #define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 228*c349dbc7Sjsg #define mmSDMA0_GFX_IB_OFFSET 0x008c 229*c349dbc7Sjsg #define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 230*c349dbc7Sjsg #define mmSDMA0_GFX_IB_BASE_LO 0x008d 231*c349dbc7Sjsg #define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 232*c349dbc7Sjsg #define mmSDMA0_GFX_IB_BASE_HI 0x008e 233*c349dbc7Sjsg #define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 234*c349dbc7Sjsg #define mmSDMA0_GFX_IB_SIZE 0x008f 235*c349dbc7Sjsg #define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 236*c349dbc7Sjsg #define mmSDMA0_GFX_SKIP_CNTL 0x0090 237*c349dbc7Sjsg #define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 238*c349dbc7Sjsg #define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 239*c349dbc7Sjsg #define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 240*c349dbc7Sjsg #define mmSDMA0_GFX_DOORBELL 0x0092 241*c349dbc7Sjsg #define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 242*c349dbc7Sjsg #define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 243*c349dbc7Sjsg #define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 244*c349dbc7Sjsg #define mmSDMA0_GFX_STATUS 0x00a8 245*c349dbc7Sjsg #define mmSDMA0_GFX_STATUS_BASE_IDX 0 246*c349dbc7Sjsg #define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 247*c349dbc7Sjsg #define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 248*c349dbc7Sjsg #define mmSDMA0_GFX_WATERMARK 0x00aa 249*c349dbc7Sjsg #define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 250*c349dbc7Sjsg #define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab 251*c349dbc7Sjsg #define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 252*c349dbc7Sjsg #define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac 253*c349dbc7Sjsg #define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 254*c349dbc7Sjsg #define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad 255*c349dbc7Sjsg #define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 256*c349dbc7Sjsg #define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af 257*c349dbc7Sjsg #define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 258*c349dbc7Sjsg #define mmSDMA0_GFX_PREEMPT 0x00b0 259*c349dbc7Sjsg #define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 260*c349dbc7Sjsg #define mmSDMA0_GFX_DUMMY_REG 0x00b1 261*c349dbc7Sjsg #define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 262*c349dbc7Sjsg #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 263*c349dbc7Sjsg #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 264*c349dbc7Sjsg #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 265*c349dbc7Sjsg #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 266*c349dbc7Sjsg #define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 267*c349dbc7Sjsg #define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 268*c349dbc7Sjsg #define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 269*c349dbc7Sjsg #define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 270*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 271*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 272*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 273*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 274*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 275*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 276*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 277*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 278*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 279*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 280*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 281*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 282*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 283*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 284*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 285*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 286*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 287*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 288*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9 289*c349dbc7Sjsg #define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 290*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_CNTL 0x00e0 291*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0 292*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_BASE 0x00e1 293*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0 294*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_BASE_HI 0x00e2 295*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 296*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_RPTR 0x00e3 297*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0 298*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4 299*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 300*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_WPTR 0x00e5 301*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0 302*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6 303*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 304*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7 305*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 306*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e8 307*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 308*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e9 309*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 310*c349dbc7Sjsg #define mmSDMA0_PAGE_IB_CNTL 0x00ea 311*c349dbc7Sjsg #define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0 312*c349dbc7Sjsg #define mmSDMA0_PAGE_IB_RPTR 0x00eb 313*c349dbc7Sjsg #define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0 314*c349dbc7Sjsg #define mmSDMA0_PAGE_IB_OFFSET 0x00ec 315*c349dbc7Sjsg #define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 316*c349dbc7Sjsg #define mmSDMA0_PAGE_IB_BASE_LO 0x00ed 317*c349dbc7Sjsg #define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 318*c349dbc7Sjsg #define mmSDMA0_PAGE_IB_BASE_HI 0x00ee 319*c349dbc7Sjsg #define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 320*c349dbc7Sjsg #define mmSDMA0_PAGE_IB_SIZE 0x00ef 321*c349dbc7Sjsg #define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0 322*c349dbc7Sjsg #define mmSDMA0_PAGE_SKIP_CNTL 0x00f0 323*c349dbc7Sjsg #define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 324*c349dbc7Sjsg #define mmSDMA0_PAGE_CONTEXT_STATUS 0x00f1 325*c349dbc7Sjsg #define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 326*c349dbc7Sjsg #define mmSDMA0_PAGE_DOORBELL 0x00f2 327*c349dbc7Sjsg #define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0 328*c349dbc7Sjsg #define mmSDMA0_PAGE_STATUS 0x0108 329*c349dbc7Sjsg #define mmSDMA0_PAGE_STATUS_BASE_IDX 0 330*c349dbc7Sjsg #define mmSDMA0_PAGE_DOORBELL_LOG 0x0109 331*c349dbc7Sjsg #define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 332*c349dbc7Sjsg #define mmSDMA0_PAGE_WATERMARK 0x010a 333*c349dbc7Sjsg #define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0 334*c349dbc7Sjsg #define mmSDMA0_PAGE_DOORBELL_OFFSET 0x010b 335*c349dbc7Sjsg #define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 336*c349dbc7Sjsg #define mmSDMA0_PAGE_CSA_ADDR_LO 0x010c 337*c349dbc7Sjsg #define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 338*c349dbc7Sjsg #define mmSDMA0_PAGE_CSA_ADDR_HI 0x010d 339*c349dbc7Sjsg #define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 340*c349dbc7Sjsg #define mmSDMA0_PAGE_IB_SUB_REMAIN 0x010f 341*c349dbc7Sjsg #define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 342*c349dbc7Sjsg #define mmSDMA0_PAGE_PREEMPT 0x0110 343*c349dbc7Sjsg #define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0 344*c349dbc7Sjsg #define mmSDMA0_PAGE_DUMMY_REG 0x0111 345*c349dbc7Sjsg #define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 346*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 347*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 348*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 349*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 350*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_AQL_CNTL 0x0114 351*c349dbc7Sjsg #define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 352*c349dbc7Sjsg #define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x0115 353*c349dbc7Sjsg #define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 354*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA0 0x0120 355*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 356*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA1 0x0121 357*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 358*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA2 0x0122 359*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 360*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA3 0x0123 361*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 362*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA4 0x0124 363*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 364*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA5 0x0125 365*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 366*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA6 0x0126 367*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 368*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA7 0x0127 369*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 370*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA8 0x0128 371*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 372*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_CNTL 0x0129 373*c349dbc7Sjsg #define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 374*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_CNTL 0x0140 375*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 376*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_BASE 0x0141 377*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 378*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_BASE_HI 0x0142 379*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 380*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_RPTR 0x0143 381*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 382*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_RPTR_HI 0x0144 383*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 384*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_WPTR 0x0145 385*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 386*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_WPTR_HI 0x0146 387*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 388*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147 389*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 390*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148 391*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 392*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149 393*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 394*c349dbc7Sjsg #define mmSDMA0_RLC0_IB_CNTL 0x014a 395*c349dbc7Sjsg #define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 396*c349dbc7Sjsg #define mmSDMA0_RLC0_IB_RPTR 0x014b 397*c349dbc7Sjsg #define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 398*c349dbc7Sjsg #define mmSDMA0_RLC0_IB_OFFSET 0x014c 399*c349dbc7Sjsg #define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 400*c349dbc7Sjsg #define mmSDMA0_RLC0_IB_BASE_LO 0x014d 401*c349dbc7Sjsg #define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 402*c349dbc7Sjsg #define mmSDMA0_RLC0_IB_BASE_HI 0x014e 403*c349dbc7Sjsg #define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 404*c349dbc7Sjsg #define mmSDMA0_RLC0_IB_SIZE 0x014f 405*c349dbc7Sjsg #define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 406*c349dbc7Sjsg #define mmSDMA0_RLC0_SKIP_CNTL 0x0150 407*c349dbc7Sjsg #define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 408*c349dbc7Sjsg #define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151 409*c349dbc7Sjsg #define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 410*c349dbc7Sjsg #define mmSDMA0_RLC0_DOORBELL 0x0152 411*c349dbc7Sjsg #define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 412*c349dbc7Sjsg #define mmSDMA0_RLC0_STATUS 0x0168 413*c349dbc7Sjsg #define mmSDMA0_RLC0_STATUS_BASE_IDX 0 414*c349dbc7Sjsg #define mmSDMA0_RLC0_DOORBELL_LOG 0x0169 415*c349dbc7Sjsg #define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 416*c349dbc7Sjsg #define mmSDMA0_RLC0_WATERMARK 0x016a 417*c349dbc7Sjsg #define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 418*c349dbc7Sjsg #define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b 419*c349dbc7Sjsg #define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 420*c349dbc7Sjsg #define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c 421*c349dbc7Sjsg #define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 422*c349dbc7Sjsg #define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d 423*c349dbc7Sjsg #define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 424*c349dbc7Sjsg #define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f 425*c349dbc7Sjsg #define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 426*c349dbc7Sjsg #define mmSDMA0_RLC0_PREEMPT 0x0170 427*c349dbc7Sjsg #define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 428*c349dbc7Sjsg #define mmSDMA0_RLC0_DUMMY_REG 0x0171 429*c349dbc7Sjsg #define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 430*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 431*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 432*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 433*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 434*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174 435*c349dbc7Sjsg #define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 436*c349dbc7Sjsg #define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175 437*c349dbc7Sjsg #define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 438*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180 439*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 440*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181 441*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 442*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182 443*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 444*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183 445*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 446*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184 447*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 448*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185 449*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 450*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186 451*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 452*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187 453*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 454*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188 455*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 456*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189 457*c349dbc7Sjsg #define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 458*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_CNTL 0x01a0 459*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 460*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_BASE 0x01a1 461*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 462*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_BASE_HI 0x01a2 463*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 464*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_RPTR 0x01a3 465*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 466*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4 467*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 468*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_WPTR 0x01a5 469*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 470*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6 471*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 472*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7 473*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 474*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8 475*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 476*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9 477*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 478*c349dbc7Sjsg #define mmSDMA0_RLC1_IB_CNTL 0x01aa 479*c349dbc7Sjsg #define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 480*c349dbc7Sjsg #define mmSDMA0_RLC1_IB_RPTR 0x01ab 481*c349dbc7Sjsg #define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 482*c349dbc7Sjsg #define mmSDMA0_RLC1_IB_OFFSET 0x01ac 483*c349dbc7Sjsg #define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 484*c349dbc7Sjsg #define mmSDMA0_RLC1_IB_BASE_LO 0x01ad 485*c349dbc7Sjsg #define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 486*c349dbc7Sjsg #define mmSDMA0_RLC1_IB_BASE_HI 0x01ae 487*c349dbc7Sjsg #define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 488*c349dbc7Sjsg #define mmSDMA0_RLC1_IB_SIZE 0x01af 489*c349dbc7Sjsg #define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 490*c349dbc7Sjsg #define mmSDMA0_RLC1_SKIP_CNTL 0x01b0 491*c349dbc7Sjsg #define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 492*c349dbc7Sjsg #define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1 493*c349dbc7Sjsg #define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 494*c349dbc7Sjsg #define mmSDMA0_RLC1_DOORBELL 0x01b2 495*c349dbc7Sjsg #define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 496*c349dbc7Sjsg #define mmSDMA0_RLC1_STATUS 0x01c8 497*c349dbc7Sjsg #define mmSDMA0_RLC1_STATUS_BASE_IDX 0 498*c349dbc7Sjsg #define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9 499*c349dbc7Sjsg #define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 500*c349dbc7Sjsg #define mmSDMA0_RLC1_WATERMARK 0x01ca 501*c349dbc7Sjsg #define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 502*c349dbc7Sjsg #define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb 503*c349dbc7Sjsg #define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 504*c349dbc7Sjsg #define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc 505*c349dbc7Sjsg #define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 506*c349dbc7Sjsg #define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd 507*c349dbc7Sjsg #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 508*c349dbc7Sjsg #define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf 509*c349dbc7Sjsg #define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 510*c349dbc7Sjsg #define mmSDMA0_RLC1_PREEMPT 0x01d0 511*c349dbc7Sjsg #define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 512*c349dbc7Sjsg #define mmSDMA0_RLC1_DUMMY_REG 0x01d1 513*c349dbc7Sjsg #define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 514*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 515*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 516*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 517*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 518*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4 519*c349dbc7Sjsg #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 520*c349dbc7Sjsg #define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5 521*c349dbc7Sjsg #define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 522*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0 523*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 524*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1 525*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 526*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2 527*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 528*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3 529*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 530*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4 531*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 532*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5 533*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 534*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6 535*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 536*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7 537*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 538*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8 539*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 540*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9 541*c349dbc7Sjsg #define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 542*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_CNTL 0x0200 543*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_CNTL_BASE_IDX 0 544*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_BASE 0x0201 545*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_BASE_BASE_IDX 0 546*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_BASE_HI 0x0202 547*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX 0 548*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_RPTR 0x0203 549*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_RPTR_BASE_IDX 0 550*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_RPTR_HI 0x0204 551*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX 0 552*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_WPTR 0x0205 553*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_WPTR_BASE_IDX 0 554*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_WPTR_HI 0x0206 555*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX 0 556*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x0207 557*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 558*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_RPTR_ADDR_HI 0x0208 559*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 560*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_RPTR_ADDR_LO 0x0209 561*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 562*c349dbc7Sjsg #define mmSDMA0_RLC2_IB_CNTL 0x020a 563*c349dbc7Sjsg #define mmSDMA0_RLC2_IB_CNTL_BASE_IDX 0 564*c349dbc7Sjsg #define mmSDMA0_RLC2_IB_RPTR 0x020b 565*c349dbc7Sjsg #define mmSDMA0_RLC2_IB_RPTR_BASE_IDX 0 566*c349dbc7Sjsg #define mmSDMA0_RLC2_IB_OFFSET 0x020c 567*c349dbc7Sjsg #define mmSDMA0_RLC2_IB_OFFSET_BASE_IDX 0 568*c349dbc7Sjsg #define mmSDMA0_RLC2_IB_BASE_LO 0x020d 569*c349dbc7Sjsg #define mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX 0 570*c349dbc7Sjsg #define mmSDMA0_RLC2_IB_BASE_HI 0x020e 571*c349dbc7Sjsg #define mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX 0 572*c349dbc7Sjsg #define mmSDMA0_RLC2_IB_SIZE 0x020f 573*c349dbc7Sjsg #define mmSDMA0_RLC2_IB_SIZE_BASE_IDX 0 574*c349dbc7Sjsg #define mmSDMA0_RLC2_SKIP_CNTL 0x0210 575*c349dbc7Sjsg #define mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX 0 576*c349dbc7Sjsg #define mmSDMA0_RLC2_CONTEXT_STATUS 0x0211 577*c349dbc7Sjsg #define mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX 0 578*c349dbc7Sjsg #define mmSDMA0_RLC2_DOORBELL 0x0212 579*c349dbc7Sjsg #define mmSDMA0_RLC2_DOORBELL_BASE_IDX 0 580*c349dbc7Sjsg #define mmSDMA0_RLC2_STATUS 0x0228 581*c349dbc7Sjsg #define mmSDMA0_RLC2_STATUS_BASE_IDX 0 582*c349dbc7Sjsg #define mmSDMA0_RLC2_DOORBELL_LOG 0x0229 583*c349dbc7Sjsg #define mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX 0 584*c349dbc7Sjsg #define mmSDMA0_RLC2_WATERMARK 0x022a 585*c349dbc7Sjsg #define mmSDMA0_RLC2_WATERMARK_BASE_IDX 0 586*c349dbc7Sjsg #define mmSDMA0_RLC2_DOORBELL_OFFSET 0x022b 587*c349dbc7Sjsg #define mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX 0 588*c349dbc7Sjsg #define mmSDMA0_RLC2_CSA_ADDR_LO 0x022c 589*c349dbc7Sjsg #define mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX 0 590*c349dbc7Sjsg #define mmSDMA0_RLC2_CSA_ADDR_HI 0x022d 591*c349dbc7Sjsg #define mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX 0 592*c349dbc7Sjsg #define mmSDMA0_RLC2_IB_SUB_REMAIN 0x022f 593*c349dbc7Sjsg #define mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX 0 594*c349dbc7Sjsg #define mmSDMA0_RLC2_PREEMPT 0x0230 595*c349dbc7Sjsg #define mmSDMA0_RLC2_PREEMPT_BASE_IDX 0 596*c349dbc7Sjsg #define mmSDMA0_RLC2_DUMMY_REG 0x0231 597*c349dbc7Sjsg #define mmSDMA0_RLC2_DUMMY_REG_BASE_IDX 0 598*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 0x0232 599*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 600*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 0x0233 601*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 602*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_AQL_CNTL 0x0234 603*c349dbc7Sjsg #define mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX 0 604*c349dbc7Sjsg #define mmSDMA0_RLC2_MINOR_PTR_UPDATE 0x0235 605*c349dbc7Sjsg #define mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 606*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA0 0x0240 607*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX 0 608*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA1 0x0241 609*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX 0 610*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA2 0x0242 611*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX 0 612*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA3 0x0243 613*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX 0 614*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA4 0x0244 615*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX 0 616*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA5 0x0245 617*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX 0 618*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA6 0x0246 619*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX 0 620*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA7 0x0247 621*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX 0 622*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA8 0x0248 623*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX 0 624*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_CNTL 0x0249 625*c349dbc7Sjsg #define mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX 0 626*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_CNTL 0x0260 627*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_CNTL_BASE_IDX 0 628*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_BASE 0x0261 629*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_BASE_BASE_IDX 0 630*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_BASE_HI 0x0262 631*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX 0 632*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_RPTR 0x0263 633*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_RPTR_BASE_IDX 0 634*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_RPTR_HI 0x0264 635*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX 0 636*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_WPTR 0x0265 637*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_WPTR_BASE_IDX 0 638*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_WPTR_HI 0x0266 639*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX 0 640*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x0267 641*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 642*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_RPTR_ADDR_HI 0x0268 643*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 644*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_RPTR_ADDR_LO 0x0269 645*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 646*c349dbc7Sjsg #define mmSDMA0_RLC3_IB_CNTL 0x026a 647*c349dbc7Sjsg #define mmSDMA0_RLC3_IB_CNTL_BASE_IDX 0 648*c349dbc7Sjsg #define mmSDMA0_RLC3_IB_RPTR 0x026b 649*c349dbc7Sjsg #define mmSDMA0_RLC3_IB_RPTR_BASE_IDX 0 650*c349dbc7Sjsg #define mmSDMA0_RLC3_IB_OFFSET 0x026c 651*c349dbc7Sjsg #define mmSDMA0_RLC3_IB_OFFSET_BASE_IDX 0 652*c349dbc7Sjsg #define mmSDMA0_RLC3_IB_BASE_LO 0x026d 653*c349dbc7Sjsg #define mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX 0 654*c349dbc7Sjsg #define mmSDMA0_RLC3_IB_BASE_HI 0x026e 655*c349dbc7Sjsg #define mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX 0 656*c349dbc7Sjsg #define mmSDMA0_RLC3_IB_SIZE 0x026f 657*c349dbc7Sjsg #define mmSDMA0_RLC3_IB_SIZE_BASE_IDX 0 658*c349dbc7Sjsg #define mmSDMA0_RLC3_SKIP_CNTL 0x0270 659*c349dbc7Sjsg #define mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX 0 660*c349dbc7Sjsg #define mmSDMA0_RLC3_CONTEXT_STATUS 0x0271 661*c349dbc7Sjsg #define mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX 0 662*c349dbc7Sjsg #define mmSDMA0_RLC3_DOORBELL 0x0272 663*c349dbc7Sjsg #define mmSDMA0_RLC3_DOORBELL_BASE_IDX 0 664*c349dbc7Sjsg #define mmSDMA0_RLC3_STATUS 0x0288 665*c349dbc7Sjsg #define mmSDMA0_RLC3_STATUS_BASE_IDX 0 666*c349dbc7Sjsg #define mmSDMA0_RLC3_DOORBELL_LOG 0x0289 667*c349dbc7Sjsg #define mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX 0 668*c349dbc7Sjsg #define mmSDMA0_RLC3_WATERMARK 0x028a 669*c349dbc7Sjsg #define mmSDMA0_RLC3_WATERMARK_BASE_IDX 0 670*c349dbc7Sjsg #define mmSDMA0_RLC3_DOORBELL_OFFSET 0x028b 671*c349dbc7Sjsg #define mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX 0 672*c349dbc7Sjsg #define mmSDMA0_RLC3_CSA_ADDR_LO 0x028c 673*c349dbc7Sjsg #define mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX 0 674*c349dbc7Sjsg #define mmSDMA0_RLC3_CSA_ADDR_HI 0x028d 675*c349dbc7Sjsg #define mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX 0 676*c349dbc7Sjsg #define mmSDMA0_RLC3_IB_SUB_REMAIN 0x028f 677*c349dbc7Sjsg #define mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX 0 678*c349dbc7Sjsg #define mmSDMA0_RLC3_PREEMPT 0x0290 679*c349dbc7Sjsg #define mmSDMA0_RLC3_PREEMPT_BASE_IDX 0 680*c349dbc7Sjsg #define mmSDMA0_RLC3_DUMMY_REG 0x0291 681*c349dbc7Sjsg #define mmSDMA0_RLC3_DUMMY_REG_BASE_IDX 0 682*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 0x0292 683*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 684*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 0x0293 685*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 686*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_AQL_CNTL 0x0294 687*c349dbc7Sjsg #define mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX 0 688*c349dbc7Sjsg #define mmSDMA0_RLC3_MINOR_PTR_UPDATE 0x0295 689*c349dbc7Sjsg #define mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 690*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA0 0x02a0 691*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX 0 692*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA1 0x02a1 693*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX 0 694*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA2 0x02a2 695*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX 0 696*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA3 0x02a3 697*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX 0 698*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA4 0x02a4 699*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX 0 700*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA5 0x02a5 701*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX 0 702*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA6 0x02a6 703*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX 0 704*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA7 0x02a7 705*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX 0 706*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA8 0x02a8 707*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX 0 708*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_CNTL 0x02a9 709*c349dbc7Sjsg #define mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX 0 710*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_CNTL 0x02c0 711*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_CNTL_BASE_IDX 0 712*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_BASE 0x02c1 713*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_BASE_BASE_IDX 0 714*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_BASE_HI 0x02c2 715*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX 0 716*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_RPTR 0x02c3 717*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_RPTR_BASE_IDX 0 718*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_RPTR_HI 0x02c4 719*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX 0 720*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_WPTR 0x02c5 721*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_WPTR_BASE_IDX 0 722*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_WPTR_HI 0x02c6 723*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX 0 724*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x02c7 725*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 726*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_RPTR_ADDR_HI 0x02c8 727*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 728*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_RPTR_ADDR_LO 0x02c9 729*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 730*c349dbc7Sjsg #define mmSDMA0_RLC4_IB_CNTL 0x02ca 731*c349dbc7Sjsg #define mmSDMA0_RLC4_IB_CNTL_BASE_IDX 0 732*c349dbc7Sjsg #define mmSDMA0_RLC4_IB_RPTR 0x02cb 733*c349dbc7Sjsg #define mmSDMA0_RLC4_IB_RPTR_BASE_IDX 0 734*c349dbc7Sjsg #define mmSDMA0_RLC4_IB_OFFSET 0x02cc 735*c349dbc7Sjsg #define mmSDMA0_RLC4_IB_OFFSET_BASE_IDX 0 736*c349dbc7Sjsg #define mmSDMA0_RLC4_IB_BASE_LO 0x02cd 737*c349dbc7Sjsg #define mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX 0 738*c349dbc7Sjsg #define mmSDMA0_RLC4_IB_BASE_HI 0x02ce 739*c349dbc7Sjsg #define mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX 0 740*c349dbc7Sjsg #define mmSDMA0_RLC4_IB_SIZE 0x02cf 741*c349dbc7Sjsg #define mmSDMA0_RLC4_IB_SIZE_BASE_IDX 0 742*c349dbc7Sjsg #define mmSDMA0_RLC4_SKIP_CNTL 0x02d0 743*c349dbc7Sjsg #define mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX 0 744*c349dbc7Sjsg #define mmSDMA0_RLC4_CONTEXT_STATUS 0x02d1 745*c349dbc7Sjsg #define mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX 0 746*c349dbc7Sjsg #define mmSDMA0_RLC4_DOORBELL 0x02d2 747*c349dbc7Sjsg #define mmSDMA0_RLC4_DOORBELL_BASE_IDX 0 748*c349dbc7Sjsg #define mmSDMA0_RLC4_STATUS 0x02e8 749*c349dbc7Sjsg #define mmSDMA0_RLC4_STATUS_BASE_IDX 0 750*c349dbc7Sjsg #define mmSDMA0_RLC4_DOORBELL_LOG 0x02e9 751*c349dbc7Sjsg #define mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX 0 752*c349dbc7Sjsg #define mmSDMA0_RLC4_WATERMARK 0x02ea 753*c349dbc7Sjsg #define mmSDMA0_RLC4_WATERMARK_BASE_IDX 0 754*c349dbc7Sjsg #define mmSDMA0_RLC4_DOORBELL_OFFSET 0x02eb 755*c349dbc7Sjsg #define mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX 0 756*c349dbc7Sjsg #define mmSDMA0_RLC4_CSA_ADDR_LO 0x02ec 757*c349dbc7Sjsg #define mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX 0 758*c349dbc7Sjsg #define mmSDMA0_RLC4_CSA_ADDR_HI 0x02ed 759*c349dbc7Sjsg #define mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX 0 760*c349dbc7Sjsg #define mmSDMA0_RLC4_IB_SUB_REMAIN 0x02ef 761*c349dbc7Sjsg #define mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX 0 762*c349dbc7Sjsg #define mmSDMA0_RLC4_PREEMPT 0x02f0 763*c349dbc7Sjsg #define mmSDMA0_RLC4_PREEMPT_BASE_IDX 0 764*c349dbc7Sjsg #define mmSDMA0_RLC4_DUMMY_REG 0x02f1 765*c349dbc7Sjsg #define mmSDMA0_RLC4_DUMMY_REG_BASE_IDX 0 766*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 0x02f2 767*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 768*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 0x02f3 769*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 770*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_AQL_CNTL 0x02f4 771*c349dbc7Sjsg #define mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX 0 772*c349dbc7Sjsg #define mmSDMA0_RLC4_MINOR_PTR_UPDATE 0x02f5 773*c349dbc7Sjsg #define mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 774*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA0 0x0300 775*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX 0 776*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA1 0x0301 777*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX 0 778*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA2 0x0302 779*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX 0 780*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA3 0x0303 781*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX 0 782*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA4 0x0304 783*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX 0 784*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA5 0x0305 785*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX 0 786*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA6 0x0306 787*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX 0 788*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA7 0x0307 789*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX 0 790*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA8 0x0308 791*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX 0 792*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_CNTL 0x0309 793*c349dbc7Sjsg #define mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX 0 794*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_CNTL 0x0320 795*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_CNTL_BASE_IDX 0 796*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_BASE 0x0321 797*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_BASE_BASE_IDX 0 798*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_BASE_HI 0x0322 799*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX 0 800*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_RPTR 0x0323 801*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_RPTR_BASE_IDX 0 802*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_RPTR_HI 0x0324 803*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX 0 804*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_WPTR 0x0325 805*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_WPTR_BASE_IDX 0 806*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_WPTR_HI 0x0326 807*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX 0 808*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x0327 809*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 810*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_RPTR_ADDR_HI 0x0328 811*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 812*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO 0x0329 813*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 814*c349dbc7Sjsg #define mmSDMA0_RLC5_IB_CNTL 0x032a 815*c349dbc7Sjsg #define mmSDMA0_RLC5_IB_CNTL_BASE_IDX 0 816*c349dbc7Sjsg #define mmSDMA0_RLC5_IB_RPTR 0x032b 817*c349dbc7Sjsg #define mmSDMA0_RLC5_IB_RPTR_BASE_IDX 0 818*c349dbc7Sjsg #define mmSDMA0_RLC5_IB_OFFSET 0x032c 819*c349dbc7Sjsg #define mmSDMA0_RLC5_IB_OFFSET_BASE_IDX 0 820*c349dbc7Sjsg #define mmSDMA0_RLC5_IB_BASE_LO 0x032d 821*c349dbc7Sjsg #define mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX 0 822*c349dbc7Sjsg #define mmSDMA0_RLC5_IB_BASE_HI 0x032e 823*c349dbc7Sjsg #define mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX 0 824*c349dbc7Sjsg #define mmSDMA0_RLC5_IB_SIZE 0x032f 825*c349dbc7Sjsg #define mmSDMA0_RLC5_IB_SIZE_BASE_IDX 0 826*c349dbc7Sjsg #define mmSDMA0_RLC5_SKIP_CNTL 0x0330 827*c349dbc7Sjsg #define mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX 0 828*c349dbc7Sjsg #define mmSDMA0_RLC5_CONTEXT_STATUS 0x0331 829*c349dbc7Sjsg #define mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX 0 830*c349dbc7Sjsg #define mmSDMA0_RLC5_DOORBELL 0x0332 831*c349dbc7Sjsg #define mmSDMA0_RLC5_DOORBELL_BASE_IDX 0 832*c349dbc7Sjsg #define mmSDMA0_RLC5_STATUS 0x0348 833*c349dbc7Sjsg #define mmSDMA0_RLC5_STATUS_BASE_IDX 0 834*c349dbc7Sjsg #define mmSDMA0_RLC5_DOORBELL_LOG 0x0349 835*c349dbc7Sjsg #define mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX 0 836*c349dbc7Sjsg #define mmSDMA0_RLC5_WATERMARK 0x034a 837*c349dbc7Sjsg #define mmSDMA0_RLC5_WATERMARK_BASE_IDX 0 838*c349dbc7Sjsg #define mmSDMA0_RLC5_DOORBELL_OFFSET 0x034b 839*c349dbc7Sjsg #define mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX 0 840*c349dbc7Sjsg #define mmSDMA0_RLC5_CSA_ADDR_LO 0x034c 841*c349dbc7Sjsg #define mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX 0 842*c349dbc7Sjsg #define mmSDMA0_RLC5_CSA_ADDR_HI 0x034d 843*c349dbc7Sjsg #define mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX 0 844*c349dbc7Sjsg #define mmSDMA0_RLC5_IB_SUB_REMAIN 0x034f 845*c349dbc7Sjsg #define mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX 0 846*c349dbc7Sjsg #define mmSDMA0_RLC5_PREEMPT 0x0350 847*c349dbc7Sjsg #define mmSDMA0_RLC5_PREEMPT_BASE_IDX 0 848*c349dbc7Sjsg #define mmSDMA0_RLC5_DUMMY_REG 0x0351 849*c349dbc7Sjsg #define mmSDMA0_RLC5_DUMMY_REG_BASE_IDX 0 850*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 0x0352 851*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 852*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 0x0353 853*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 854*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_AQL_CNTL 0x0354 855*c349dbc7Sjsg #define mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX 0 856*c349dbc7Sjsg #define mmSDMA0_RLC5_MINOR_PTR_UPDATE 0x0355 857*c349dbc7Sjsg #define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 858*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA0 0x0360 859*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX 0 860*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA1 0x0361 861*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX 0 862*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA2 0x0362 863*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX 0 864*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA3 0x0363 865*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX 0 866*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA4 0x0364 867*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX 0 868*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA5 0x0365 869*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX 0 870*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA6 0x0366 871*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX 0 872*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA7 0x0367 873*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX 0 874*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA8 0x0368 875*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX 0 876*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_CNTL 0x0369 877*c349dbc7Sjsg #define mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX 0 878*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_CNTL 0x0380 879*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_CNTL_BASE_IDX 0 880*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_BASE 0x0381 881*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_BASE_BASE_IDX 0 882*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_BASE_HI 0x0382 883*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX 0 884*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_RPTR 0x0383 885*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_RPTR_BASE_IDX 0 886*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_RPTR_HI 0x0384 887*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX 0 888*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_WPTR 0x0385 889*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_WPTR_BASE_IDX 0 890*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_WPTR_HI 0x0386 891*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX 0 892*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL 0x0387 893*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 894*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_RPTR_ADDR_HI 0x0388 895*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 896*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_RPTR_ADDR_LO 0x0389 897*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 898*c349dbc7Sjsg #define mmSDMA0_RLC6_IB_CNTL 0x038a 899*c349dbc7Sjsg #define mmSDMA0_RLC6_IB_CNTL_BASE_IDX 0 900*c349dbc7Sjsg #define mmSDMA0_RLC6_IB_RPTR 0x038b 901*c349dbc7Sjsg #define mmSDMA0_RLC6_IB_RPTR_BASE_IDX 0 902*c349dbc7Sjsg #define mmSDMA0_RLC6_IB_OFFSET 0x038c 903*c349dbc7Sjsg #define mmSDMA0_RLC6_IB_OFFSET_BASE_IDX 0 904*c349dbc7Sjsg #define mmSDMA0_RLC6_IB_BASE_LO 0x038d 905*c349dbc7Sjsg #define mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX 0 906*c349dbc7Sjsg #define mmSDMA0_RLC6_IB_BASE_HI 0x038e 907*c349dbc7Sjsg #define mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX 0 908*c349dbc7Sjsg #define mmSDMA0_RLC6_IB_SIZE 0x038f 909*c349dbc7Sjsg #define mmSDMA0_RLC6_IB_SIZE_BASE_IDX 0 910*c349dbc7Sjsg #define mmSDMA0_RLC6_SKIP_CNTL 0x0390 911*c349dbc7Sjsg #define mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX 0 912*c349dbc7Sjsg #define mmSDMA0_RLC6_CONTEXT_STATUS 0x0391 913*c349dbc7Sjsg #define mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX 0 914*c349dbc7Sjsg #define mmSDMA0_RLC6_DOORBELL 0x0392 915*c349dbc7Sjsg #define mmSDMA0_RLC6_DOORBELL_BASE_IDX 0 916*c349dbc7Sjsg #define mmSDMA0_RLC6_STATUS 0x03a8 917*c349dbc7Sjsg #define mmSDMA0_RLC6_STATUS_BASE_IDX 0 918*c349dbc7Sjsg #define mmSDMA0_RLC6_DOORBELL_LOG 0x03a9 919*c349dbc7Sjsg #define mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX 0 920*c349dbc7Sjsg #define mmSDMA0_RLC6_WATERMARK 0x03aa 921*c349dbc7Sjsg #define mmSDMA0_RLC6_WATERMARK_BASE_IDX 0 922*c349dbc7Sjsg #define mmSDMA0_RLC6_DOORBELL_OFFSET 0x03ab 923*c349dbc7Sjsg #define mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX 0 924*c349dbc7Sjsg #define mmSDMA0_RLC6_CSA_ADDR_LO 0x03ac 925*c349dbc7Sjsg #define mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX 0 926*c349dbc7Sjsg #define mmSDMA0_RLC6_CSA_ADDR_HI 0x03ad 927*c349dbc7Sjsg #define mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX 0 928*c349dbc7Sjsg #define mmSDMA0_RLC6_IB_SUB_REMAIN 0x03af 929*c349dbc7Sjsg #define mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX 0 930*c349dbc7Sjsg #define mmSDMA0_RLC6_PREEMPT 0x03b0 931*c349dbc7Sjsg #define mmSDMA0_RLC6_PREEMPT_BASE_IDX 0 932*c349dbc7Sjsg #define mmSDMA0_RLC6_DUMMY_REG 0x03b1 933*c349dbc7Sjsg #define mmSDMA0_RLC6_DUMMY_REG_BASE_IDX 0 934*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 0x03b2 935*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 936*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 0x03b3 937*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 938*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_AQL_CNTL 0x03b4 939*c349dbc7Sjsg #define mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX 0 940*c349dbc7Sjsg #define mmSDMA0_RLC6_MINOR_PTR_UPDATE 0x03b5 941*c349dbc7Sjsg #define mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 942*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA0 0x03c0 943*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX 0 944*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA1 0x03c1 945*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX 0 946*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA2 0x03c2 947*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX 0 948*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA3 0x03c3 949*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX 0 950*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA4 0x03c4 951*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX 0 952*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA5 0x03c5 953*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX 0 954*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA6 0x03c6 955*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX 0 956*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA7 0x03c7 957*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX 0 958*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA8 0x03c8 959*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX 0 960*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_CNTL 0x03c9 961*c349dbc7Sjsg #define mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX 0 962*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_CNTL 0x03e0 963*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_CNTL_BASE_IDX 0 964*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_BASE 0x03e1 965*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_BASE_BASE_IDX 0 966*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_BASE_HI 0x03e2 967*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX 0 968*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_RPTR 0x03e3 969*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_RPTR_BASE_IDX 0 970*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_RPTR_HI 0x03e4 971*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX 0 972*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_WPTR 0x03e5 973*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_WPTR_BASE_IDX 0 974*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_WPTR_HI 0x03e6 975*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX 0 976*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL 0x03e7 977*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 978*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_RPTR_ADDR_HI 0x03e8 979*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 980*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_RPTR_ADDR_LO 0x03e9 981*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 982*c349dbc7Sjsg #define mmSDMA0_RLC7_IB_CNTL 0x03ea 983*c349dbc7Sjsg #define mmSDMA0_RLC7_IB_CNTL_BASE_IDX 0 984*c349dbc7Sjsg #define mmSDMA0_RLC7_IB_RPTR 0x03eb 985*c349dbc7Sjsg #define mmSDMA0_RLC7_IB_RPTR_BASE_IDX 0 986*c349dbc7Sjsg #define mmSDMA0_RLC7_IB_OFFSET 0x03ec 987*c349dbc7Sjsg #define mmSDMA0_RLC7_IB_OFFSET_BASE_IDX 0 988*c349dbc7Sjsg #define mmSDMA0_RLC7_IB_BASE_LO 0x03ed 989*c349dbc7Sjsg #define mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX 0 990*c349dbc7Sjsg #define mmSDMA0_RLC7_IB_BASE_HI 0x03ee 991*c349dbc7Sjsg #define mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX 0 992*c349dbc7Sjsg #define mmSDMA0_RLC7_IB_SIZE 0x03ef 993*c349dbc7Sjsg #define mmSDMA0_RLC7_IB_SIZE_BASE_IDX 0 994*c349dbc7Sjsg #define mmSDMA0_RLC7_SKIP_CNTL 0x03f0 995*c349dbc7Sjsg #define mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX 0 996*c349dbc7Sjsg #define mmSDMA0_RLC7_CONTEXT_STATUS 0x03f1 997*c349dbc7Sjsg #define mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX 0 998*c349dbc7Sjsg #define mmSDMA0_RLC7_DOORBELL 0x03f2 999*c349dbc7Sjsg #define mmSDMA0_RLC7_DOORBELL_BASE_IDX 0 1000*c349dbc7Sjsg #define mmSDMA0_RLC7_STATUS 0x0408 1001*c349dbc7Sjsg #define mmSDMA0_RLC7_STATUS_BASE_IDX 0 1002*c349dbc7Sjsg #define mmSDMA0_RLC7_DOORBELL_LOG 0x0409 1003*c349dbc7Sjsg #define mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX 0 1004*c349dbc7Sjsg #define mmSDMA0_RLC7_WATERMARK 0x040a 1005*c349dbc7Sjsg #define mmSDMA0_RLC7_WATERMARK_BASE_IDX 0 1006*c349dbc7Sjsg #define mmSDMA0_RLC7_DOORBELL_OFFSET 0x040b 1007*c349dbc7Sjsg #define mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX 0 1008*c349dbc7Sjsg #define mmSDMA0_RLC7_CSA_ADDR_LO 0x040c 1009*c349dbc7Sjsg #define mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX 0 1010*c349dbc7Sjsg #define mmSDMA0_RLC7_CSA_ADDR_HI 0x040d 1011*c349dbc7Sjsg #define mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX 0 1012*c349dbc7Sjsg #define mmSDMA0_RLC7_IB_SUB_REMAIN 0x040f 1013*c349dbc7Sjsg #define mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX 0 1014*c349dbc7Sjsg #define mmSDMA0_RLC7_PREEMPT 0x0410 1015*c349dbc7Sjsg #define mmSDMA0_RLC7_PREEMPT_BASE_IDX 0 1016*c349dbc7Sjsg #define mmSDMA0_RLC7_DUMMY_REG 0x0411 1017*c349dbc7Sjsg #define mmSDMA0_RLC7_DUMMY_REG_BASE_IDX 0 1018*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 0x0412 1019*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 1020*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 0x0413 1021*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 1022*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_AQL_CNTL 0x0414 1023*c349dbc7Sjsg #define mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX 0 1024*c349dbc7Sjsg #define mmSDMA0_RLC7_MINOR_PTR_UPDATE 0x0415 1025*c349dbc7Sjsg #define mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 1026*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA0 0x0420 1027*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX 0 1028*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA1 0x0421 1029*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX 0 1030*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA2 0x0422 1031*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX 0 1032*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA3 0x0423 1033*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX 0 1034*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA4 0x0424 1035*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX 0 1036*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA5 0x0425 1037*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX 0 1038*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA6 0x0426 1039*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX 0 1040*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA7 0x0427 1041*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX 0 1042*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA8 0x0428 1043*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX 0 1044*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_CNTL 0x0429 1045*c349dbc7Sjsg #define mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX 0 1046*c349dbc7Sjsg 1047*c349dbc7Sjsg #endif 1048