1*fb4d8502Sjsg /* 2*fb4d8502Sjsg * UVD_5_0 Register documentation 3*fb4d8502Sjsg * 4*fb4d8502Sjsg * Copyright (C) 2014 Advanced Micro Devices, Inc. 5*fb4d8502Sjsg * 6*fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 7*fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 8*fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 9*fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10*fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 11*fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 12*fb4d8502Sjsg * 13*fb4d8502Sjsg * The above copyright notice and this permission notice shall be included 14*fb4d8502Sjsg * in all copies or substantial portions of the Software. 15*fb4d8502Sjsg * 16*fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17*fb4d8502Sjsg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18*fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19*fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20*fb4d8502Sjsg * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21*fb4d8502Sjsg * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22*fb4d8502Sjsg */ 23*fb4d8502Sjsg 24*fb4d8502Sjsg #ifndef UVD_5_0_SH_MASK_H 25*fb4d8502Sjsg #define UVD_5_0_SH_MASK_H 26*fb4d8502Sjsg 27*fb4d8502Sjsg #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28*fb4d8502Sjsg #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29*fb4d8502Sjsg #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30*fb4d8502Sjsg #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31*fb4d8502Sjsg #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32*fb4d8502Sjsg #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33*fb4d8502Sjsg #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34*fb4d8502Sjsg #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35*fb4d8502Sjsg #define UVD_SEMA_CMD__MODE_MASK 0x40 36*fb4d8502Sjsg #define UVD_SEMA_CMD__MODE__SHIFT 0x6 37*fb4d8502Sjsg #define UVD_SEMA_CMD__VMID_EN_MASK 0x80 38*fb4d8502Sjsg #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 39*fb4d8502Sjsg #define UVD_SEMA_CMD__VMID_MASK 0xf00 40*fb4d8502Sjsg #define UVD_SEMA_CMD__VMID__SHIFT 0x8 41*fb4d8502Sjsg #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 42*fb4d8502Sjsg #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 43*fb4d8502Sjsg #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe 44*fb4d8502Sjsg #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 45*fb4d8502Sjsg #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000 46*fb4d8502Sjsg #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 47*fb4d8502Sjsg #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff 48*fb4d8502Sjsg #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 49*fb4d8502Sjsg #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff 50*fb4d8502Sjsg #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 51*fb4d8502Sjsg #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 52*fb4d8502Sjsg #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 53*fb4d8502Sjsg #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 54*fb4d8502Sjsg #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 55*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7 56*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 57*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 58*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 59*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 60*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 61*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 62*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 63*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 64*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 65*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 66*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 67*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 68*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 69*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 70*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 71*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 72*fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 73*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 74*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 75*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 76*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 77*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 78*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 79*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 80*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 81*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 82*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 83*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 84*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 85*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 86*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 87*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 88*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 89*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 90*fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 91*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 92*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 93*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 94*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 95*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 96*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 97*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 98*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 99*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 100*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 101*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 102*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 103*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 104*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 105*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 106*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 107*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 108*fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 109*fb4d8502Sjsg #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 110*fb4d8502Sjsg #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 111*fb4d8502Sjsg #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 112*fb4d8502Sjsg #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 113*fb4d8502Sjsg #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 114*fb4d8502Sjsg #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 115*fb4d8502Sjsg #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 116*fb4d8502Sjsg #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 117*fb4d8502Sjsg #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 118*fb4d8502Sjsg #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 119*fb4d8502Sjsg #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 120*fb4d8502Sjsg #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 121*fb4d8502Sjsg #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 122*fb4d8502Sjsg #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 123*fb4d8502Sjsg #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2 124*fb4d8502Sjsg #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 125*fb4d8502Sjsg #define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff 126*fb4d8502Sjsg #define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0 127*fb4d8502Sjsg #define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000 128*fb4d8502Sjsg #define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10 129*fb4d8502Sjsg #define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000 130*fb4d8502Sjsg #define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f 131*fb4d8502Sjsg #define UVD_CTX_INDEX__INDEX_MASK 0x1ff 132*fb4d8502Sjsg #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 133*fb4d8502Sjsg #define UVD_CTX_DATA__DATA_MASK 0xffffffff 134*fb4d8502Sjsg #define UVD_CTX_DATA__DATA__SHIFT 0x0 135*fb4d8502Sjsg #define UVD_CGC_GATE__SYS_MASK 0x1 136*fb4d8502Sjsg #define UVD_CGC_GATE__SYS__SHIFT 0x0 137*fb4d8502Sjsg #define UVD_CGC_GATE__UDEC_MASK 0x2 138*fb4d8502Sjsg #define UVD_CGC_GATE__UDEC__SHIFT 0x1 139*fb4d8502Sjsg #define UVD_CGC_GATE__MPEG2_MASK 0x4 140*fb4d8502Sjsg #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 141*fb4d8502Sjsg #define UVD_CGC_GATE__REGS_MASK 0x8 142*fb4d8502Sjsg #define UVD_CGC_GATE__REGS__SHIFT 0x3 143*fb4d8502Sjsg #define UVD_CGC_GATE__RBC_MASK 0x10 144*fb4d8502Sjsg #define UVD_CGC_GATE__RBC__SHIFT 0x4 145*fb4d8502Sjsg #define UVD_CGC_GATE__LMI_MC_MASK 0x20 146*fb4d8502Sjsg #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 147*fb4d8502Sjsg #define UVD_CGC_GATE__LMI_UMC_MASK 0x40 148*fb4d8502Sjsg #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 149*fb4d8502Sjsg #define UVD_CGC_GATE__IDCT_MASK 0x80 150*fb4d8502Sjsg #define UVD_CGC_GATE__IDCT__SHIFT 0x7 151*fb4d8502Sjsg #define UVD_CGC_GATE__MPRD_MASK 0x100 152*fb4d8502Sjsg #define UVD_CGC_GATE__MPRD__SHIFT 0x8 153*fb4d8502Sjsg #define UVD_CGC_GATE__MPC_MASK 0x200 154*fb4d8502Sjsg #define UVD_CGC_GATE__MPC__SHIFT 0x9 155*fb4d8502Sjsg #define UVD_CGC_GATE__LBSI_MASK 0x400 156*fb4d8502Sjsg #define UVD_CGC_GATE__LBSI__SHIFT 0xa 157*fb4d8502Sjsg #define UVD_CGC_GATE__LRBBM_MASK 0x800 158*fb4d8502Sjsg #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 159*fb4d8502Sjsg #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 160*fb4d8502Sjsg #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 161*fb4d8502Sjsg #define UVD_CGC_GATE__UDEC_CM_MASK 0x2000 162*fb4d8502Sjsg #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 163*fb4d8502Sjsg #define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 164*fb4d8502Sjsg #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 165*fb4d8502Sjsg #define UVD_CGC_GATE__UDEC_DB_MASK 0x8000 166*fb4d8502Sjsg #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 167*fb4d8502Sjsg #define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 168*fb4d8502Sjsg #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 169*fb4d8502Sjsg #define UVD_CGC_GATE__WCB_MASK 0x20000 170*fb4d8502Sjsg #define UVD_CGC_GATE__WCB__SHIFT 0x11 171*fb4d8502Sjsg #define UVD_CGC_GATE__VCPU_MASK 0x40000 172*fb4d8502Sjsg #define UVD_CGC_GATE__VCPU__SHIFT 0x12 173*fb4d8502Sjsg #define UVD_CGC_GATE__SCPU_MASK 0x80000 174*fb4d8502Sjsg #define UVD_CGC_GATE__SCPU__SHIFT 0x13 175*fb4d8502Sjsg #define UVD_CGC_GATE__JPEG_MASK 0x100000 176*fb4d8502Sjsg #define UVD_CGC_GATE__JPEG__SHIFT 0x14 177*fb4d8502Sjsg #define UVD_CGC_GATE__JPEG2_MASK 0x200000 178*fb4d8502Sjsg #define UVD_CGC_GATE__JPEG2__SHIFT 0x15 179*fb4d8502Sjsg #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 180*fb4d8502Sjsg #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 181*fb4d8502Sjsg #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2 182*fb4d8502Sjsg #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 183*fb4d8502Sjsg #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4 184*fb4d8502Sjsg #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 185*fb4d8502Sjsg #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8 186*fb4d8502Sjsg #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 187*fb4d8502Sjsg #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10 188*fb4d8502Sjsg #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 189*fb4d8502Sjsg #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20 190*fb4d8502Sjsg #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 191*fb4d8502Sjsg #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40 192*fb4d8502Sjsg #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 193*fb4d8502Sjsg #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80 194*fb4d8502Sjsg #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 195*fb4d8502Sjsg #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100 196*fb4d8502Sjsg #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 197*fb4d8502Sjsg #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200 198*fb4d8502Sjsg #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 199*fb4d8502Sjsg #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400 200*fb4d8502Sjsg #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 201*fb4d8502Sjsg #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800 202*fb4d8502Sjsg #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 203*fb4d8502Sjsg #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000 204*fb4d8502Sjsg #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 205*fb4d8502Sjsg #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000 206*fb4d8502Sjsg #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 207*fb4d8502Sjsg #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000 208*fb4d8502Sjsg #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 209*fb4d8502Sjsg #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000 210*fb4d8502Sjsg #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 211*fb4d8502Sjsg #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000 212*fb4d8502Sjsg #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 213*fb4d8502Sjsg #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000 214*fb4d8502Sjsg #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 215*fb4d8502Sjsg #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000 216*fb4d8502Sjsg #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 217*fb4d8502Sjsg #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 218*fb4d8502Sjsg #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 219*fb4d8502Sjsg #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000 220*fb4d8502Sjsg #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 221*fb4d8502Sjsg #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000 222*fb4d8502Sjsg #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 223*fb4d8502Sjsg #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000 224*fb4d8502Sjsg #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 225*fb4d8502Sjsg #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000 226*fb4d8502Sjsg #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 227*fb4d8502Sjsg #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000 228*fb4d8502Sjsg #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 229*fb4d8502Sjsg #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000 230*fb4d8502Sjsg #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 231*fb4d8502Sjsg #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000 232*fb4d8502Sjsg #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 233*fb4d8502Sjsg #define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000 234*fb4d8502Sjsg #define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b 235*fb4d8502Sjsg #define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000 236*fb4d8502Sjsg #define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c 237*fb4d8502Sjsg #define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000 238*fb4d8502Sjsg #define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e 239*fb4d8502Sjsg #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000 240*fb4d8502Sjsg #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 241*fb4d8502Sjsg #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 242*fb4d8502Sjsg #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 243*fb4d8502Sjsg #define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2 244*fb4d8502Sjsg #define UVD_CGC_CTRL__JPEG2_MODE__SHIFT 0x1 245*fb4d8502Sjsg #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c 246*fb4d8502Sjsg #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 247*fb4d8502Sjsg #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 248*fb4d8502Sjsg #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 249*fb4d8502Sjsg #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 250*fb4d8502Sjsg #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 251*fb4d8502Sjsg #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000 252*fb4d8502Sjsg #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 253*fb4d8502Sjsg #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 254*fb4d8502Sjsg #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 255*fb4d8502Sjsg #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000 256*fb4d8502Sjsg #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 257*fb4d8502Sjsg #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000 258*fb4d8502Sjsg #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 259*fb4d8502Sjsg #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 260*fb4d8502Sjsg #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 261*fb4d8502Sjsg #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000 262*fb4d8502Sjsg #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 263*fb4d8502Sjsg #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000 264*fb4d8502Sjsg #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 265*fb4d8502Sjsg #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 266*fb4d8502Sjsg #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 267*fb4d8502Sjsg #define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 268*fb4d8502Sjsg #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 269*fb4d8502Sjsg #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000 270*fb4d8502Sjsg #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 271*fb4d8502Sjsg #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000 272*fb4d8502Sjsg #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 273*fb4d8502Sjsg #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000 274*fb4d8502Sjsg #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 275*fb4d8502Sjsg #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 276*fb4d8502Sjsg #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 277*fb4d8502Sjsg #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 278*fb4d8502Sjsg #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 279*fb4d8502Sjsg #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000 280*fb4d8502Sjsg #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 281*fb4d8502Sjsg #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000 282*fb4d8502Sjsg #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 283*fb4d8502Sjsg #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 284*fb4d8502Sjsg #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 285*fb4d8502Sjsg #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 286*fb4d8502Sjsg #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 287*fb4d8502Sjsg #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 288*fb4d8502Sjsg #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 289*fb4d8502Sjsg #define UVD_CGC_CTRL__JPEG_MODE_MASK 0x80000000 290*fb4d8502Sjsg #define UVD_CGC_CTRL__JPEG_MODE__SHIFT 0x1f 291*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1 292*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 293*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2 294*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 295*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4 296*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 297*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 298*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 299*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 300*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 301*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 302*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 303*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40 304*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 305*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 306*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 307*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100 308*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 309*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200 310*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 311*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400 312*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 313*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800 314*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 315*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000 316*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 317*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000 318*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 319*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000 320*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 321*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK 0x8000 322*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT 0xf 323*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK 0x10000 324*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT 0x10 325*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK 0x20000 326*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT 0x11 327*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK 0x40000 328*fb4d8502Sjsg #define UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT 0x12 329*fb4d8502Sjsg #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1 330*fb4d8502Sjsg #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 331*fb4d8502Sjsg #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2 332*fb4d8502Sjsg #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 333*fb4d8502Sjsg #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4 334*fb4d8502Sjsg #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 335*fb4d8502Sjsg #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8 336*fb4d8502Sjsg #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 337*fb4d8502Sjsg #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70 338*fb4d8502Sjsg #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4 339*fb4d8502Sjsg #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80 340*fb4d8502Sjsg #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 341*fb4d8502Sjsg #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 342*fb4d8502Sjsg #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 343*fb4d8502Sjsg #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600 344*fb4d8502Sjsg #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 345*fb4d8502Sjsg #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800 346*fb4d8502Sjsg #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 347*fb4d8502Sjsg #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000 348*fb4d8502Sjsg #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 349*fb4d8502Sjsg #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000 350*fb4d8502Sjsg #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 351*fb4d8502Sjsg #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000 352*fb4d8502Sjsg #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 353*fb4d8502Sjsg #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000 354*fb4d8502Sjsg #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 355*fb4d8502Sjsg #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000 356*fb4d8502Sjsg #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 357*fb4d8502Sjsg #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1 358*fb4d8502Sjsg #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 359*fb4d8502Sjsg #define UVD_MASTINT_EN__VCPU_EN_MASK 0x2 360*fb4d8502Sjsg #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 361*fb4d8502Sjsg #define UVD_MASTINT_EN__SYS_EN_MASK 0x4 362*fb4d8502Sjsg #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 363*fb4d8502Sjsg #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0 364*fb4d8502Sjsg #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 365*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf 366*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0 367*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0 368*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4 369*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00 370*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8 371*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000 372*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc 373*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000 374*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10 375*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000 376*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14 377*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000 378*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18 379*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000 380*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c 381*fb4d8502Sjsg #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff 382*fb4d8502Sjsg #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 383*fb4d8502Sjsg #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 384*fb4d8502Sjsg #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 385*fb4d8502Sjsg #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200 386*fb4d8502Sjsg #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 387*fb4d8502Sjsg #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800 388*fb4d8502Sjsg #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 389*fb4d8502Sjsg #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000 390*fb4d8502Sjsg #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 391*fb4d8502Sjsg #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000 392*fb4d8502Sjsg #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 393*fb4d8502Sjsg #define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000 394*fb4d8502Sjsg #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 395*fb4d8502Sjsg #define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000 396*fb4d8502Sjsg #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 397*fb4d8502Sjsg #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000 398*fb4d8502Sjsg #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 399*fb4d8502Sjsg #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 400*fb4d8502Sjsg #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 401*fb4d8502Sjsg #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000 402*fb4d8502Sjsg #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 403*fb4d8502Sjsg #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000 404*fb4d8502Sjsg #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 405*fb4d8502Sjsg #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000 406*fb4d8502Sjsg #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 407*fb4d8502Sjsg #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000 408*fb4d8502Sjsg #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 409*fb4d8502Sjsg #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000 410*fb4d8502Sjsg #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 411*fb4d8502Sjsg #define UVD_LMI_CTRL__RFU_MASK 0xf8000000 412*fb4d8502Sjsg #define UVD_LMI_CTRL__RFU__SHIFT 0x1b 413*fb4d8502Sjsg #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1 414*fb4d8502Sjsg #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 415*fb4d8502Sjsg #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2 416*fb4d8502Sjsg #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 417*fb4d8502Sjsg #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 418*fb4d8502Sjsg #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 419*fb4d8502Sjsg #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8 420*fb4d8502Sjsg #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 421*fb4d8502Sjsg #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10 422*fb4d8502Sjsg #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 423*fb4d8502Sjsg #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20 424*fb4d8502Sjsg #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 425*fb4d8502Sjsg #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40 426*fb4d8502Sjsg #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 427*fb4d8502Sjsg #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80 428*fb4d8502Sjsg #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 429*fb4d8502Sjsg #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100 430*fb4d8502Sjsg #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 431*fb4d8502Sjsg #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200 432*fb4d8502Sjsg #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 433*fb4d8502Sjsg #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400 434*fb4d8502Sjsg #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 435*fb4d8502Sjsg #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800 436*fb4d8502Sjsg #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 437*fb4d8502Sjsg #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000 438*fb4d8502Sjsg #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 439*fb4d8502Sjsg #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000 440*fb4d8502Sjsg #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 441*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3 442*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 443*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc 444*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 445*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30 446*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 447*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0 448*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 449*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300 450*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 451*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00 452*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 453*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000 454*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 455*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000 456*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 457*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000 458*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 459*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000 460*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 461*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000 462*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 463*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000 464*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 465*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000 466*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 467*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000 468*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 469*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000 470*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 471*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3 472*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 473*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc 474*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 475*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30 476*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 477*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0 478*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 479*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300 480*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 481*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00 482*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 483*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000 484*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 485*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000 486*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 487*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000 488*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 489*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000 490*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 491*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000 492*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 493*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000 494*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 495*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000 496*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 497*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000 498*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 499*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000 500*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 501*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000 502*fb4d8502Sjsg #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 503*fb4d8502Sjsg #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 504*fb4d8502Sjsg #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 505*fb4d8502Sjsg #define UVD_MPC_CNTL__PERF_RST_MASK 0x40 506*fb4d8502Sjsg #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 507*fb4d8502Sjsg #define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00 508*fb4d8502Sjsg #define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 509*fb4d8502Sjsg #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000 510*fb4d8502Sjsg #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 511*fb4d8502Sjsg #define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000 512*fb4d8502Sjsg #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 513*fb4d8502Sjsg #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f 514*fb4d8502Sjsg #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 515*fb4d8502Sjsg #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0 516*fb4d8502Sjsg #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 517*fb4d8502Sjsg #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 518*fb4d8502Sjsg #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 519*fb4d8502Sjsg #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 520*fb4d8502Sjsg #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 521*fb4d8502Sjsg #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 522*fb4d8502Sjsg #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 523*fb4d8502Sjsg #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f 524*fb4d8502Sjsg #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 525*fb4d8502Sjsg #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 526*fb4d8502Sjsg #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 527*fb4d8502Sjsg #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 528*fb4d8502Sjsg #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 529*fb4d8502Sjsg #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f 530*fb4d8502Sjsg #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 531*fb4d8502Sjsg #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 532*fb4d8502Sjsg #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 533*fb4d8502Sjsg #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000 534*fb4d8502Sjsg #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 535*fb4d8502Sjsg #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000 536*fb4d8502Sjsg #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 537*fb4d8502Sjsg #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000 538*fb4d8502Sjsg #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 539*fb4d8502Sjsg #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f 540*fb4d8502Sjsg #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 541*fb4d8502Sjsg #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0 542*fb4d8502Sjsg #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 543*fb4d8502Sjsg #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 544*fb4d8502Sjsg #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 545*fb4d8502Sjsg #define UVD_MPC_SET_MUX__SET_0_MASK 0x7 546*fb4d8502Sjsg #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 547*fb4d8502Sjsg #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 548*fb4d8502Sjsg #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 549*fb4d8502Sjsg #define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 550*fb4d8502Sjsg #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 551*fb4d8502Sjsg #define UVD_MPC_SET_ALU__FUNCT_MASK 0x7 552*fb4d8502Sjsg #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 553*fb4d8502Sjsg #define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0 554*fb4d8502Sjsg #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 555*fb4d8502Sjsg #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff 556*fb4d8502Sjsg #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 557*fb4d8502Sjsg #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff 558*fb4d8502Sjsg #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 559*fb4d8502Sjsg #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff 560*fb4d8502Sjsg #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 561*fb4d8502Sjsg #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff 562*fb4d8502Sjsg #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 563*fb4d8502Sjsg #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff 564*fb4d8502Sjsg #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 565*fb4d8502Sjsg #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff 566*fb4d8502Sjsg #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 567*fb4d8502Sjsg #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf 568*fb4d8502Sjsg #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 569*fb4d8502Sjsg #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10 570*fb4d8502Sjsg #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 571*fb4d8502Sjsg #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20 572*fb4d8502Sjsg #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 573*fb4d8502Sjsg #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40 574*fb4d8502Sjsg #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 575*fb4d8502Sjsg #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80 576*fb4d8502Sjsg #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 577*fb4d8502Sjsg #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100 578*fb4d8502Sjsg #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 579*fb4d8502Sjsg #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 580*fb4d8502Sjsg #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 581*fb4d8502Sjsg #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400 582*fb4d8502Sjsg #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 583*fb4d8502Sjsg #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 584*fb4d8502Sjsg #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 585*fb4d8502Sjsg #define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000 586*fb4d8502Sjsg #define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd 587*fb4d8502Sjsg #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000 588*fb4d8502Sjsg #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 589*fb4d8502Sjsg #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000 590*fb4d8502Sjsg #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 591*fb4d8502Sjsg #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000 592*fb4d8502Sjsg #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 593*fb4d8502Sjsg #define UVD_VCPU_CNTL__SUVD_EN_MASK 0x80000 594*fb4d8502Sjsg #define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13 595*fb4d8502Sjsg #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000 596*fb4d8502Sjsg #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 597*fb4d8502Sjsg #define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000 598*fb4d8502Sjsg #define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c 599*fb4d8502Sjsg #define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000 600*fb4d8502Sjsg #define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e 601*fb4d8502Sjsg #define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000 602*fb4d8502Sjsg #define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f 603*fb4d8502Sjsg #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1 604*fb4d8502Sjsg #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 605*fb4d8502Sjsg #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2 606*fb4d8502Sjsg #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 607*fb4d8502Sjsg #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4 608*fb4d8502Sjsg #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 609*fb4d8502Sjsg #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8 610*fb4d8502Sjsg #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 611*fb4d8502Sjsg #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10 612*fb4d8502Sjsg #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 613*fb4d8502Sjsg #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20 614*fb4d8502Sjsg #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 615*fb4d8502Sjsg #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40 616*fb4d8502Sjsg #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 617*fb4d8502Sjsg #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80 618*fb4d8502Sjsg #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 619*fb4d8502Sjsg #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100 620*fb4d8502Sjsg #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 621*fb4d8502Sjsg #define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200 622*fb4d8502Sjsg #define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT 0x9 623*fb4d8502Sjsg #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400 624*fb4d8502Sjsg #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 625*fb4d8502Sjsg #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800 626*fb4d8502Sjsg #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 627*fb4d8502Sjsg #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000 628*fb4d8502Sjsg #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 629*fb4d8502Sjsg #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000 630*fb4d8502Sjsg #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 631*fb4d8502Sjsg #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000 632*fb4d8502Sjsg #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 633*fb4d8502Sjsg #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000 634*fb4d8502Sjsg #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 635*fb4d8502Sjsg #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000 636*fb4d8502Sjsg #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 637*fb4d8502Sjsg #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x20000 638*fb4d8502Sjsg #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 639*fb4d8502Sjsg #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x40000 640*fb4d8502Sjsg #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 641*fb4d8502Sjsg #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x80000 642*fb4d8502Sjsg #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 643*fb4d8502Sjsg #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x100000 644*fb4d8502Sjsg #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 645*fb4d8502Sjsg #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x200000 646*fb4d8502Sjsg #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 647*fb4d8502Sjsg #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x400000 648*fb4d8502Sjsg #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 649*fb4d8502Sjsg #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x800000 650*fb4d8502Sjsg #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 651*fb4d8502Sjsg #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x1000000 652*fb4d8502Sjsg #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 653*fb4d8502Sjsg #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x2000000 654*fb4d8502Sjsg #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 655*fb4d8502Sjsg #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x4000000 656*fb4d8502Sjsg #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 657*fb4d8502Sjsg #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x8000000 658*fb4d8502Sjsg #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 659*fb4d8502Sjsg #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000 660*fb4d8502Sjsg #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 661*fb4d8502Sjsg #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000 662*fb4d8502Sjsg #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 663*fb4d8502Sjsg #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000 664*fb4d8502Sjsg #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 665*fb4d8502Sjsg #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000 666*fb4d8502Sjsg #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 667*fb4d8502Sjsg #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0xf 668*fb4d8502Sjsg #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 669*fb4d8502Sjsg #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0 670*fb4d8502Sjsg #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 671*fb4d8502Sjsg #define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0xf 672*fb4d8502Sjsg #define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 673*fb4d8502Sjsg #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0 674*fb4d8502Sjsg #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 675*fb4d8502Sjsg #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0 676*fb4d8502Sjsg #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 677*fb4d8502Sjsg #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f 678*fb4d8502Sjsg #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 679*fb4d8502Sjsg #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00 680*fb4d8502Sjsg #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 681*fb4d8502Sjsg #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 682*fb4d8502Sjsg #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 683*fb4d8502Sjsg #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000 684*fb4d8502Sjsg #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 685*fb4d8502Sjsg #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000 686*fb4d8502Sjsg #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 687*fb4d8502Sjsg #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 688*fb4d8502Sjsg #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 689*fb4d8502Sjsg #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff 690*fb4d8502Sjsg #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 691*fb4d8502Sjsg #define UVD_STATUS__RBC_BUSY_MASK 0x1 692*fb4d8502Sjsg #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 693*fb4d8502Sjsg #define UVD_STATUS__VCPU_REPORT_MASK 0xfe 694*fb4d8502Sjsg #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 695*fb4d8502Sjsg #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1 696*fb4d8502Sjsg #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 697*fb4d8502Sjsg #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2 698*fb4d8502Sjsg #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 699*fb4d8502Sjsg #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4 700*fb4d8502Sjsg #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 701*fb4d8502Sjsg #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8 702*fb4d8502Sjsg #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 703*fb4d8502Sjsg #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1 704*fb4d8502Sjsg #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 705*fb4d8502Sjsg #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe 706*fb4d8502Sjsg #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 707*fb4d8502Sjsg #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 708*fb4d8502Sjsg #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 709*fb4d8502Sjsg #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1 710*fb4d8502Sjsg #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 711*fb4d8502Sjsg #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe 712*fb4d8502Sjsg #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 713*fb4d8502Sjsg #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 714*fb4d8502Sjsg #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 715*fb4d8502Sjsg #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1 716*fb4d8502Sjsg #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 717*fb4d8502Sjsg #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe 718*fb4d8502Sjsg #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 719*fb4d8502Sjsg #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 720*fb4d8502Sjsg #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 721*fb4d8502Sjsg #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff 722*fb4d8502Sjsg #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 723*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SRE_MASK 0x1 724*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 725*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SIT_MASK 0x2 726*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 727*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SMP_MASK 0x4 728*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 729*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SCM_MASK 0x8 730*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 731*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SDB_MASK 0x10 732*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 733*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20 734*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 735*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40 736*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 737*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80 738*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 739*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100 740*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 741*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200 742*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 743*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400 744*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 745*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800 746*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 747*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 748*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 749*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x2000 750*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 751*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x4000 752*fb4d8502Sjsg #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 753*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1 754*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 755*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2 756*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 757*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4 758*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 759*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8 760*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 761*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10 762*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 763*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20 764*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 765*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40 766*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 767*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80 768*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 769*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100 770*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 771*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200 772*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 773*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x400 774*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 775*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800 776*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 777*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x1000 778*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 779*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000 780*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 781*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x4000 782*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 783*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x8000 784*fb4d8502Sjsg #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 785*fb4d8502Sjsg #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1 786*fb4d8502Sjsg #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 787*fb4d8502Sjsg #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2 788*fb4d8502Sjsg #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 789*fb4d8502Sjsg #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4 790*fb4d8502Sjsg #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 791*fb4d8502Sjsg #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8 792*fb4d8502Sjsg #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 793*fb4d8502Sjsg #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10 794*fb4d8502Sjsg #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 795*fb4d8502Sjsg #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x20 796*fb4d8502Sjsg #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 797*fb4d8502Sjsg #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x40 798*fb4d8502Sjsg #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 799*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK 0xf 800*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0 801*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK 0xf0 802*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4 803*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK 0xf00 804*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8 805*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK 0xf000 806*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc 807*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK 0xf0000 808*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10 809*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK 0xf00000 810*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14 811*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK 0xf000000 812*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT 0x18 813*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK 0xf0000000 814*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT 0x1c 815*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK 0xf 816*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0 817*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK 0xf0 818*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4 819*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK 0xf00 820*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8 821*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK 0xf000 822*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc 823*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK 0xf0000 824*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10 825*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK 0xf00000 826*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT 0x14 827*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK 0xf000000 828*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT 0x18 829*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK 0xf0000000 830*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT 0x1c 831*fb4d8502Sjsg #define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1 832*fb4d8502Sjsg #define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 833*fb4d8502Sjsg #define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2 834*fb4d8502Sjsg #define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 835*fb4d8502Sjsg #define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4 836*fb4d8502Sjsg #define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 837*fb4d8502Sjsg #define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8 838*fb4d8502Sjsg #define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 839*fb4d8502Sjsg #define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10 840*fb4d8502Sjsg #define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 841*fb4d8502Sjsg #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20 842*fb4d8502Sjsg #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 843*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3 844*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 845*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc 846*fb4d8502Sjsg #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 847*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf 848*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 849*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0 850*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 851*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00 852*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 853*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000 854*fb4d8502Sjsg #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc 855*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1 856*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 857*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2 858*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 859*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4 860*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 861*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8 862*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 863*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10 864*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 865*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20 866*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 867*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40 868*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 869*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80 870*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 871*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100 872*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 873*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200 874*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 875*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400 876*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 877*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800 878*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb 879*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000 880*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 881*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000 882*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 883*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK 0x4000 884*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe 885*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK 0x8000 886*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT 0xf 887*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000 888*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 889*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000 890*fb4d8502Sjsg #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 891*fb4d8502Sjsg #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1 892*fb4d8502Sjsg #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 893*fb4d8502Sjsg #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2 894*fb4d8502Sjsg #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 895*fb4d8502Sjsg #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c 896*fb4d8502Sjsg #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 897*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK 0xf 898*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0 899*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK 0xf0 900*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4 901*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK 0xf00 902*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8 903*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK 0xf000 904*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc 905*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID_MASK 0xf0000 906*fb4d8502Sjsg #define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID__SHIFT 0x10 907*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff 908*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0 909*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100 910*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8 911*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200 912*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9 913*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400 914*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa 915*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800 916*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb 917*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000 918*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc 919*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000 920*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd 921*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000 922*fb4d8502Sjsg #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c 923*fb4d8502Sjsg #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff 924*fb4d8502Sjsg #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0 925*fb4d8502Sjsg #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff 926*fb4d8502Sjsg #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0 927*fb4d8502Sjsg #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3 928*fb4d8502Sjsg #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 929*fb4d8502Sjsg #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 930*fb4d8502Sjsg #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 931*fb4d8502Sjsg #define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x8 932*fb4d8502Sjsg #define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3 933*fb4d8502Sjsg #define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x10 934*fb4d8502Sjsg #define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4 935*fb4d8502Sjsg #define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x20 936*fb4d8502Sjsg #define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5 937*fb4d8502Sjsg #define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0xc0 938*fb4d8502Sjsg #define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6 939*fb4d8502Sjsg #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100 940*fb4d8502Sjsg #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 941*fb4d8502Sjsg #define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x200 942*fb4d8502Sjsg #define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9 943*fb4d8502Sjsg #define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x400 944*fb4d8502Sjsg #define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa 945*fb4d8502Sjsg #define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK 0xffffff 946*fb4d8502Sjsg #define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT 0x0 947*fb4d8502Sjsg #define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK 0xffffff 948*fb4d8502Sjsg #define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT 0x0 949*fb4d8502Sjsg #define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK 0xffffff 950*fb4d8502Sjsg #define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT 0x0 951*fb4d8502Sjsg #define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK 0xffffff 952*fb4d8502Sjsg #define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT 0x0 953*fb4d8502Sjsg #define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK 0xffffff 954*fb4d8502Sjsg #define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT 0x0 955*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 956*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 957*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 958*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 959*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 960*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 961*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 962*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 963*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 964*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 965*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 966*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 967*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 968*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 969*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 970*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 971*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 972*fb4d8502Sjsg #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 973*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 974*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 975*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 976*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 977*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 978*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 979*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 980*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 981*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 982*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 983*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 984*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 985*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 986*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 987*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 988*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 989*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 990*fb4d8502Sjsg #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 991*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7 992*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 993*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 994*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 995*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 996*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 997*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 998*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 999*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1000*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1001*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1002*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1003*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1004*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1005*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1006*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1007*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1008*fb4d8502Sjsg #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1009*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 1010*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1011*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 1012*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1013*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 1014*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 1015*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 1016*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 1017*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1018*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1019*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1020*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1021*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1022*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1023*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1024*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1025*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1026*fb4d8502Sjsg #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1027*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x7 1028*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1029*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 1030*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1031*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 1032*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 1033*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 1034*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 1035*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1036*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1037*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1038*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1039*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1040*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1041*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1042*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1043*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1044*fb4d8502Sjsg #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1045*fb4d8502Sjsg 1046*fb4d8502Sjsg #endif /* UVD_5_0_SH_MASK_H */ 1047