1c349dbc7Sjsg /* 2c349dbc7Sjsg * Copyright 2018 Advanced Micro Devices, Inc. 3c349dbc7Sjsg * 4c349dbc7Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5c349dbc7Sjsg * copy of this software and associated documentation files (the "Software"), 6c349dbc7Sjsg * to deal in the Software without restriction, including without limitation 7c349dbc7Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c349dbc7Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9c349dbc7Sjsg * Software is furnished to do so, subject to the following conditions: 10c349dbc7Sjsg * 11c349dbc7Sjsg * The above copyright notice and this permission notice shall be included in 12c349dbc7Sjsg * all copies or substantial portions of the Software. 13c349dbc7Sjsg * 14c349dbc7Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c349dbc7Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c349dbc7Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c349dbc7Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c349dbc7Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c349dbc7Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c349dbc7Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21c349dbc7Sjsg * 22c349dbc7Sjsg */ 23c349dbc7Sjsg 24c349dbc7Sjsg #ifndef _DISCOVERY_H_ 25c349dbc7Sjsg #define _DISCOVERY_H_ 26c349dbc7Sjsg 27c349dbc7Sjsg #define PSP_HEADER_SIZE 256 28c349dbc7Sjsg #define BINARY_SIGNATURE 0x28211407 29c349dbc7Sjsg #define DISCOVERY_TABLE_SIGNATURE 0x53445049 301bb76ff1Sjsg #define GC_TABLE_ID 0x4347 311bb76ff1Sjsg #define HARVEST_TABLE_SIGNATURE 0x56524148 321bb76ff1Sjsg #define VCN_INFO_TABLE_ID 0x004E4356 33*f005ef32Sjsg #define MALL_INFO_TABLE_ID 0x4C4C414D 34c349dbc7Sjsg 35c349dbc7Sjsg typedef enum 36c349dbc7Sjsg { 37c349dbc7Sjsg IP_DISCOVERY = 0, 38c349dbc7Sjsg GC, 39c349dbc7Sjsg HARVEST_INFO, 401bb76ff1Sjsg VCN_INFO, 411bb76ff1Sjsg MALL_INFO, 42c349dbc7Sjsg RESERVED_1, 43c349dbc7Sjsg TOTAL_TABLES = 6 44c349dbc7Sjsg } table; 45c349dbc7Sjsg 46c349dbc7Sjsg #pragma pack(1) 47c349dbc7Sjsg 48c349dbc7Sjsg typedef struct table_info 49c349dbc7Sjsg { 50c349dbc7Sjsg uint16_t offset; /* Byte offset */ 51c349dbc7Sjsg uint16_t checksum; /* Byte sum of the table */ 52c349dbc7Sjsg uint16_t size; /* Table size */ 53c349dbc7Sjsg uint16_t padding; 54c349dbc7Sjsg } table_info; 55c349dbc7Sjsg 56c349dbc7Sjsg typedef struct binary_header 57c349dbc7Sjsg { 58c349dbc7Sjsg /* psp structure should go at the top of this structure */ 59c349dbc7Sjsg uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */ 60c349dbc7Sjsg uint16_t version_major; 61c349dbc7Sjsg uint16_t version_minor; 62c349dbc7Sjsg uint16_t binary_checksum; /* Byte sum of the binary after this field */ 63c349dbc7Sjsg uint16_t binary_size; /* Binary Size*/ 64c349dbc7Sjsg table_info table_list[TOTAL_TABLES]; 65c349dbc7Sjsg } binary_header; 66c349dbc7Sjsg 67c349dbc7Sjsg typedef struct die_info 68c349dbc7Sjsg { 69c349dbc7Sjsg uint16_t die_id; 70c349dbc7Sjsg uint16_t die_offset; /* Points to the corresponding die_header structure */ 71c349dbc7Sjsg } die_info; 72c349dbc7Sjsg 73c349dbc7Sjsg 74c349dbc7Sjsg typedef struct ip_discovery_header 75c349dbc7Sjsg { 76c349dbc7Sjsg uint32_t signature; /* Table Signature */ 77c349dbc7Sjsg uint16_t version; /* Table Version */ 78c349dbc7Sjsg uint16_t size; /* Table Size */ 79c349dbc7Sjsg uint32_t id; /* Table ID */ 80c349dbc7Sjsg uint16_t num_dies; /* Number of Dies */ 81c349dbc7Sjsg die_info die_info[16]; /* list die information for up to 16 dies */ 82*f005ef32Sjsg union { 83*f005ef32Sjsg uint16_t padding[1]; /* version <= 3 */ 84*f005ef32Sjsg struct { /* version == 4 */ 85*f005ef32Sjsg uint8_t base_addr_64_bit : 1; /* ip structures are using 64 bit base address */ 86*f005ef32Sjsg uint8_t reserved : 7; 87*f005ef32Sjsg uint8_t reserved2; 88*f005ef32Sjsg }; 89*f005ef32Sjsg }; 90c349dbc7Sjsg } ip_discovery_header; 91c349dbc7Sjsg 92c349dbc7Sjsg typedef struct ip 93c349dbc7Sjsg { 94c349dbc7Sjsg uint16_t hw_id; /* Hardware ID */ 95c349dbc7Sjsg uint8_t number_instance; /* instance of the IP */ 96c349dbc7Sjsg uint8_t num_base_address; /* Number of Base Addresses */ 97c349dbc7Sjsg uint8_t major; /* HCID Major */ 98c349dbc7Sjsg uint8_t minor; /* HCID Minor */ 99c349dbc7Sjsg uint8_t revision; /* HCID Revision */ 100c349dbc7Sjsg #if defined(__BIG_ENDIAN) 101c349dbc7Sjsg uint8_t reserved : 4; /* Placeholder field */ 102c349dbc7Sjsg uint8_t harvest : 4; /* Harvest */ 103c349dbc7Sjsg #else 104c349dbc7Sjsg uint8_t harvest : 4; /* Harvest */ 105c349dbc7Sjsg uint8_t reserved : 4; /* Placeholder field */ 106c349dbc7Sjsg #endif 1071bb76ff1Sjsg uint32_t base_address[]; /* variable number of Addresses */ 108c349dbc7Sjsg } ip; 109c349dbc7Sjsg 1101bb76ff1Sjsg typedef struct ip_v3 1111bb76ff1Sjsg { 1121bb76ff1Sjsg uint16_t hw_id; /* Hardware ID */ 1131bb76ff1Sjsg uint8_t instance_number; /* Instance number for the IP */ 1141bb76ff1Sjsg uint8_t num_base_address; /* Number of base addresses*/ 1151bb76ff1Sjsg uint8_t major; /* Hardware ID.major version */ 1161bb76ff1Sjsg uint8_t minor; /* Hardware ID.minor version */ 1171bb76ff1Sjsg uint8_t revision; /* Hardware ID.revision version */ 1181bb76ff1Sjsg #if defined(__BIG_ENDIAN) 1191bb76ff1Sjsg uint8_t variant : 4; /* HW variant */ 1201bb76ff1Sjsg uint8_t sub_revision : 4; /* HCID Sub-Revision */ 1211bb76ff1Sjsg #else 1221bb76ff1Sjsg uint8_t sub_revision : 4; /* HCID Sub-Revision */ 1231bb76ff1Sjsg uint8_t variant : 4; /* HW variant */ 1241bb76ff1Sjsg #endif 125*f005ef32Sjsg uint32_t base_address[]; /* Base Address list. Corresponds to the num_base_address field*/ 1261bb76ff1Sjsg } ip_v3; 1271bb76ff1Sjsg 128*f005ef32Sjsg typedef struct ip_v4 { 129*f005ef32Sjsg uint16_t hw_id; /* Hardware ID */ 130*f005ef32Sjsg uint8_t instance_number; /* Instance number for the IP */ 131*f005ef32Sjsg uint8_t num_base_address; /* Number of base addresses*/ 132*f005ef32Sjsg uint8_t major; /* Hardware ID.major version */ 133*f005ef32Sjsg uint8_t minor; /* Hardware ID.minor version */ 134*f005ef32Sjsg uint8_t revision; /* Hardware ID.revision version */ 135*f005ef32Sjsg #if defined(LITTLEENDIAN_CPU) 136*f005ef32Sjsg uint8_t sub_revision : 4; /* HCID Sub-Revision */ 137*f005ef32Sjsg uint8_t variant : 4; /* HW variant */ 138*f005ef32Sjsg #elif defined(BIGENDIAN_CPU) 139*f005ef32Sjsg uint8_t variant : 4; /* HW variant */ 140*f005ef32Sjsg uint8_t sub_revision : 4; /* HCID Sub-Revision */ 141*f005ef32Sjsg #endif 142*f005ef32Sjsg union { 143*f005ef32Sjsg DECLARE_FLEX_ARRAY(uint32_t, base_address); /* 32-bit Base Address list. Corresponds to the num_base_address field*/ 144*f005ef32Sjsg DECLARE_FLEX_ARRAY(uint64_t, base_address_64); /* 64-bit Base Address list. Corresponds to the num_base_address field*/ 145*f005ef32Sjsg } __packed; 146*f005ef32Sjsg } ip_v4; 147*f005ef32Sjsg 148c349dbc7Sjsg typedef struct die_header 149c349dbc7Sjsg { 150c349dbc7Sjsg uint16_t die_id; 151c349dbc7Sjsg uint16_t num_ips; 152c349dbc7Sjsg } die_header; 153c349dbc7Sjsg 154c349dbc7Sjsg typedef struct ip_structure 155c349dbc7Sjsg { 156c349dbc7Sjsg ip_discovery_header* header; 157c349dbc7Sjsg struct die 158c349dbc7Sjsg { 159c349dbc7Sjsg die_header *die_header; 1601bb76ff1Sjsg union 1611bb76ff1Sjsg { 162c349dbc7Sjsg ip *ip_list; 1631bb76ff1Sjsg ip_v3 *ip_v3_list; 164*f005ef32Sjsg ip_v4 *ip_v4_list; 1651bb76ff1Sjsg }; /* IP list. Variable size*/ 166c349dbc7Sjsg } die; 167c349dbc7Sjsg } ip_structure; 168c349dbc7Sjsg 169c349dbc7Sjsg struct gpu_info_header { 170c349dbc7Sjsg uint32_t table_id; /* table ID */ 171c349dbc7Sjsg uint16_t version_major; /* table version */ 172c349dbc7Sjsg uint16_t version_minor; /* table version */ 173c349dbc7Sjsg uint32_t size; /* size of the entire header+data in bytes */ 174c349dbc7Sjsg }; 175c349dbc7Sjsg 176c349dbc7Sjsg struct gc_info_v1_0 { 177c349dbc7Sjsg struct gpu_info_header header; 178c349dbc7Sjsg 179c349dbc7Sjsg uint32_t gc_num_se; 180c349dbc7Sjsg uint32_t gc_num_wgp0_per_sa; 181c349dbc7Sjsg uint32_t gc_num_wgp1_per_sa; 182c349dbc7Sjsg uint32_t gc_num_rb_per_se; 183c349dbc7Sjsg uint32_t gc_num_gl2c; 184c349dbc7Sjsg uint32_t gc_num_gprs; 185c349dbc7Sjsg uint32_t gc_num_max_gs_thds; 186c349dbc7Sjsg uint32_t gc_gs_table_depth; 187c349dbc7Sjsg uint32_t gc_gsprim_buff_depth; 188c349dbc7Sjsg uint32_t gc_parameter_cache_depth; 189c349dbc7Sjsg uint32_t gc_double_offchip_lds_buffer; 190c349dbc7Sjsg uint32_t gc_wave_size; 191c349dbc7Sjsg uint32_t gc_max_waves_per_simd; 192c349dbc7Sjsg uint32_t gc_max_scratch_slots_per_cu; 193c349dbc7Sjsg uint32_t gc_lds_size; 194c349dbc7Sjsg uint32_t gc_num_sc_per_se; 195c349dbc7Sjsg uint32_t gc_num_sa_per_se; 196c349dbc7Sjsg uint32_t gc_num_packer_per_sc; 197c349dbc7Sjsg uint32_t gc_num_gl2a; 198c349dbc7Sjsg }; 199c349dbc7Sjsg 2002bb0cdd1Sjsg struct gc_info_v1_1 { 2012bb0cdd1Sjsg struct gpu_info_header header; 2022bb0cdd1Sjsg 2032bb0cdd1Sjsg uint32_t gc_num_se; 2042bb0cdd1Sjsg uint32_t gc_num_wgp0_per_sa; 2052bb0cdd1Sjsg uint32_t gc_num_wgp1_per_sa; 2062bb0cdd1Sjsg uint32_t gc_num_rb_per_se; 2072bb0cdd1Sjsg uint32_t gc_num_gl2c; 2082bb0cdd1Sjsg uint32_t gc_num_gprs; 2092bb0cdd1Sjsg uint32_t gc_num_max_gs_thds; 2102bb0cdd1Sjsg uint32_t gc_gs_table_depth; 2112bb0cdd1Sjsg uint32_t gc_gsprim_buff_depth; 2122bb0cdd1Sjsg uint32_t gc_parameter_cache_depth; 2132bb0cdd1Sjsg uint32_t gc_double_offchip_lds_buffer; 2142bb0cdd1Sjsg uint32_t gc_wave_size; 2152bb0cdd1Sjsg uint32_t gc_max_waves_per_simd; 2162bb0cdd1Sjsg uint32_t gc_max_scratch_slots_per_cu; 2172bb0cdd1Sjsg uint32_t gc_lds_size; 2182bb0cdd1Sjsg uint32_t gc_num_sc_per_se; 2192bb0cdd1Sjsg uint32_t gc_num_sa_per_se; 2202bb0cdd1Sjsg uint32_t gc_num_packer_per_sc; 2212bb0cdd1Sjsg uint32_t gc_num_gl2a; 2222bb0cdd1Sjsg uint32_t gc_num_tcp_per_sa; 2232bb0cdd1Sjsg uint32_t gc_num_sdp_interface; 2242bb0cdd1Sjsg uint32_t gc_num_tcps; 2252bb0cdd1Sjsg }; 2262bb0cdd1Sjsg 2271bb76ff1Sjsg struct gc_info_v1_2 { 2281bb76ff1Sjsg struct gpu_info_header header; 2291bb76ff1Sjsg uint32_t gc_num_se; 2301bb76ff1Sjsg uint32_t gc_num_wgp0_per_sa; 2311bb76ff1Sjsg uint32_t gc_num_wgp1_per_sa; 2321bb76ff1Sjsg uint32_t gc_num_rb_per_se; 2331bb76ff1Sjsg uint32_t gc_num_gl2c; 2341bb76ff1Sjsg uint32_t gc_num_gprs; 2351bb76ff1Sjsg uint32_t gc_num_max_gs_thds; 2361bb76ff1Sjsg uint32_t gc_gs_table_depth; 2371bb76ff1Sjsg uint32_t gc_gsprim_buff_depth; 2381bb76ff1Sjsg uint32_t gc_parameter_cache_depth; 2391bb76ff1Sjsg uint32_t gc_double_offchip_lds_buffer; 2401bb76ff1Sjsg uint32_t gc_wave_size; 2411bb76ff1Sjsg uint32_t gc_max_waves_per_simd; 2421bb76ff1Sjsg uint32_t gc_max_scratch_slots_per_cu; 2431bb76ff1Sjsg uint32_t gc_lds_size; 2441bb76ff1Sjsg uint32_t gc_num_sc_per_se; 2451bb76ff1Sjsg uint32_t gc_num_sa_per_se; 2461bb76ff1Sjsg uint32_t gc_num_packer_per_sc; 2471bb76ff1Sjsg uint32_t gc_num_gl2a; 2481bb76ff1Sjsg uint32_t gc_num_tcp_per_sa; 2491bb76ff1Sjsg uint32_t gc_num_sdp_interface; 2501bb76ff1Sjsg uint32_t gc_num_tcps; 2511bb76ff1Sjsg uint32_t gc_num_tcp_per_wpg; 2521bb76ff1Sjsg uint32_t gc_tcp_l1_size; 2531bb76ff1Sjsg uint32_t gc_num_sqc_per_wgp; 2541bb76ff1Sjsg uint32_t gc_l1_instruction_cache_size_per_sqc; 2551bb76ff1Sjsg uint32_t gc_l1_data_cache_size_per_sqc; 2561bb76ff1Sjsg uint32_t gc_gl1c_per_sa; 2571bb76ff1Sjsg uint32_t gc_gl1c_size_per_instance; 2581bb76ff1Sjsg uint32_t gc_gl2c_per_gpu; 2591bb76ff1Sjsg }; 2601bb76ff1Sjsg 2612bb0cdd1Sjsg struct gc_info_v2_0 { 2622bb0cdd1Sjsg struct gpu_info_header header; 2632bb0cdd1Sjsg 2642bb0cdd1Sjsg uint32_t gc_num_se; 2652bb0cdd1Sjsg uint32_t gc_num_cu_per_sh; 2662bb0cdd1Sjsg uint32_t gc_num_sh_per_se; 2672bb0cdd1Sjsg uint32_t gc_num_rb_per_se; 2682bb0cdd1Sjsg uint32_t gc_num_tccs; 2692bb0cdd1Sjsg uint32_t gc_num_gprs; 2702bb0cdd1Sjsg uint32_t gc_num_max_gs_thds; 2712bb0cdd1Sjsg uint32_t gc_gs_table_depth; 2722bb0cdd1Sjsg uint32_t gc_gsprim_buff_depth; 2732bb0cdd1Sjsg uint32_t gc_parameter_cache_depth; 2742bb0cdd1Sjsg uint32_t gc_double_offchip_lds_buffer; 2752bb0cdd1Sjsg uint32_t gc_wave_size; 2762bb0cdd1Sjsg uint32_t gc_max_waves_per_simd; 2772bb0cdd1Sjsg uint32_t gc_max_scratch_slots_per_cu; 2782bb0cdd1Sjsg uint32_t gc_lds_size; 2792bb0cdd1Sjsg uint32_t gc_num_sc_per_se; 2802bb0cdd1Sjsg uint32_t gc_num_packer_per_sc; 2812bb0cdd1Sjsg }; 2822bb0cdd1Sjsg 283*f005ef32Sjsg struct gc_info_v2_1 { 284*f005ef32Sjsg struct gpu_info_header header; 285*f005ef32Sjsg 286*f005ef32Sjsg uint32_t gc_num_se; 287*f005ef32Sjsg uint32_t gc_num_cu_per_sh; 288*f005ef32Sjsg uint32_t gc_num_sh_per_se; 289*f005ef32Sjsg uint32_t gc_num_rb_per_se; 290*f005ef32Sjsg uint32_t gc_num_tccs; 291*f005ef32Sjsg uint32_t gc_num_gprs; 292*f005ef32Sjsg uint32_t gc_num_max_gs_thds; 293*f005ef32Sjsg uint32_t gc_gs_table_depth; 294*f005ef32Sjsg uint32_t gc_gsprim_buff_depth; 295*f005ef32Sjsg uint32_t gc_parameter_cache_depth; 296*f005ef32Sjsg uint32_t gc_double_offchip_lds_buffer; 297*f005ef32Sjsg uint32_t gc_wave_size; 298*f005ef32Sjsg uint32_t gc_max_waves_per_simd; 299*f005ef32Sjsg uint32_t gc_max_scratch_slots_per_cu; 300*f005ef32Sjsg uint32_t gc_lds_size; 301*f005ef32Sjsg uint32_t gc_num_sc_per_se; 302*f005ef32Sjsg uint32_t gc_num_packer_per_sc; 303*f005ef32Sjsg /* new for v2_1 */ 304*f005ef32Sjsg uint32_t gc_num_tcp_per_sh; 305*f005ef32Sjsg uint32_t gc_tcp_size_per_cu; 306*f005ef32Sjsg uint32_t gc_num_sdp_interface; 307*f005ef32Sjsg uint32_t gc_num_cu_per_sqc; 308*f005ef32Sjsg uint32_t gc_instruction_cache_size_per_sqc; 309*f005ef32Sjsg uint32_t gc_scalar_data_cache_size_per_sqc; 310*f005ef32Sjsg uint32_t gc_tcc_size; 311*f005ef32Sjsg }; 312*f005ef32Sjsg 313c349dbc7Sjsg typedef struct harvest_info_header { 314c349dbc7Sjsg uint32_t signature; /* Table Signature */ 315c349dbc7Sjsg uint32_t version; /* Table Version */ 316c349dbc7Sjsg } harvest_info_header; 317c349dbc7Sjsg 318c349dbc7Sjsg typedef struct harvest_info { 319c349dbc7Sjsg uint16_t hw_id; /* Hardware ID */ 320c349dbc7Sjsg uint8_t number_instance; /* Instance of the IP */ 321c349dbc7Sjsg uint8_t reserved; /* Reserved for alignment */ 322c349dbc7Sjsg } harvest_info; 323c349dbc7Sjsg 324c349dbc7Sjsg typedef struct harvest_table { 325c349dbc7Sjsg harvest_info_header header; 326c349dbc7Sjsg harvest_info list[32]; 327c349dbc7Sjsg } harvest_table; 328c349dbc7Sjsg 3291bb76ff1Sjsg struct mall_info_header { 3301bb76ff1Sjsg uint32_t table_id; /* table ID */ 3311bb76ff1Sjsg uint16_t version_major; /* table version */ 3321bb76ff1Sjsg uint16_t version_minor; /* table version */ 3331bb76ff1Sjsg uint32_t size_bytes; /* size of the entire header+data in bytes */ 3341bb76ff1Sjsg }; 3351bb76ff1Sjsg 3361bb76ff1Sjsg struct mall_info_v1_0 { 3371bb76ff1Sjsg struct mall_info_header header; 3381bb76ff1Sjsg uint32_t mall_size_per_m; 3391bb76ff1Sjsg uint32_t m_s_present; 3401bb76ff1Sjsg uint32_t m_half_use; 3411bb76ff1Sjsg uint32_t m_mall_config; 3421bb76ff1Sjsg uint32_t reserved[5]; 3431bb76ff1Sjsg }; 3441bb76ff1Sjsg 345*f005ef32Sjsg struct mall_info_v2_0 { 346*f005ef32Sjsg struct mall_info_header header; 347*f005ef32Sjsg uint32_t mall_size_per_umc; 348*f005ef32Sjsg uint32_t reserved[8]; 349*f005ef32Sjsg }; 350*f005ef32Sjsg 3511bb76ff1Sjsg #define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4 3521bb76ff1Sjsg 3531bb76ff1Sjsg struct vcn_info_header { 3541bb76ff1Sjsg uint32_t table_id; /* table ID */ 3551bb76ff1Sjsg uint16_t version_major; /* table version */ 3561bb76ff1Sjsg uint16_t version_minor; /* table version */ 3571bb76ff1Sjsg uint32_t size_bytes; /* size of the entire header+data in bytes */ 3581bb76ff1Sjsg }; 3591bb76ff1Sjsg 3601bb76ff1Sjsg struct vcn_instance_info_v1_0 3611bb76ff1Sjsg { 3621bb76ff1Sjsg uint32_t instance_num; /* VCN IP instance number. 0 - VCN0; 1 - VCN1 etc*/ 3631bb76ff1Sjsg union _fuse_data { 3641bb76ff1Sjsg struct { 3651bb76ff1Sjsg uint32_t av1_disabled : 1; 3661bb76ff1Sjsg uint32_t vp9_disabled : 1; 3671bb76ff1Sjsg uint32_t hevc_disabled : 1; 3681bb76ff1Sjsg uint32_t h264_disabled : 1; 3691bb76ff1Sjsg uint32_t reserved : 28; 3701bb76ff1Sjsg } bits; 3711bb76ff1Sjsg uint32_t all_bits; 3721bb76ff1Sjsg } fuse_data; 3731bb76ff1Sjsg uint32_t reserved[2]; 3741bb76ff1Sjsg }; 3751bb76ff1Sjsg 3761bb76ff1Sjsg struct vcn_info_v1_0 { 3771bb76ff1Sjsg struct vcn_info_header header; 3781bb76ff1Sjsg uint32_t num_of_instances; /* number of entries used in instance_info below*/ 3791bb76ff1Sjsg struct vcn_instance_info_v1_0 instance_info[VCN_INFO_TABLE_MAX_NUM_INSTANCES]; 3801bb76ff1Sjsg uint32_t reserved[4]; 3811bb76ff1Sjsg }; 3821bb76ff1Sjsg 383c349dbc7Sjsg #pragma pack() 384c349dbc7Sjsg 385c349dbc7Sjsg #endif 386