1*1bb76ff1Sjsg /* 2*1bb76ff1Sjsg * Copyright 2011 Advanced Micro Devices, Inc. 3*1bb76ff1Sjsg * 4*1bb76ff1Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*1bb76ff1Sjsg * copy of this software and associated documentation files (the "Software"), 6*1bb76ff1Sjsg * to deal in the Software without restriction, including without limitation 7*1bb76ff1Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*1bb76ff1Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9*1bb76ff1Sjsg * Software is furnished to do so, subject to the following conditions: 10*1bb76ff1Sjsg * 11*1bb76ff1Sjsg * The above copyright notice and this permission notice shall be included in 12*1bb76ff1Sjsg * all copies or substantial portions of the Software. 13*1bb76ff1Sjsg * 14*1bb76ff1Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*1bb76ff1Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*1bb76ff1Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*1bb76ff1Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*1bb76ff1Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*1bb76ff1Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*1bb76ff1Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21*1bb76ff1Sjsg * 22*1bb76ff1Sjsg */ 23*1bb76ff1Sjsg #ifndef PP_SMC_H 24*1bb76ff1Sjsg #define PP_SMC_H 25*1bb76ff1Sjsg 26*1bb76ff1Sjsg #pragma pack(push, 1) 27*1bb76ff1Sjsg 28*1bb76ff1Sjsg #define PPSMC_SWSTATE_FLAG_DC 0x01 29*1bb76ff1Sjsg #define PPSMC_SWSTATE_FLAG_UVD 0x02 30*1bb76ff1Sjsg #define PPSMC_SWSTATE_FLAG_VCE 0x04 31*1bb76ff1Sjsg #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08 32*1bb76ff1Sjsg 33*1bb76ff1Sjsg #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 34*1bb76ff1Sjsg #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 35*1bb76ff1Sjsg #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff 36*1bb76ff1Sjsg 37*1bb76ff1Sjsg #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 38*1bb76ff1Sjsg #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 39*1bb76ff1Sjsg #define PPSMC_SYSTEMFLAG_GDDR5 0x04 40*1bb76ff1Sjsg #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 41*1bb76ff1Sjsg #define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 42*1bb76ff1Sjsg #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 43*1bb76ff1Sjsg #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO 0x40 44*1bb76ff1Sjsg 45*1bb76ff1Sjsg #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 46*1bb76ff1Sjsg #define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 47*1bb76ff1Sjsg #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 48*1bb76ff1Sjsg #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 49*1bb76ff1Sjsg #define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x02 50*1bb76ff1Sjsg 51*1bb76ff1Sjsg #define PPSMC_DISPLAY_WATERMARK_LOW 0 52*1bb76ff1Sjsg #define PPSMC_DISPLAY_WATERMARK_HIGH 1 53*1bb76ff1Sjsg 54*1bb76ff1Sjsg #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 55*1bb76ff1Sjsg #define PPSMC_STATEFLAG_POWERBOOST 0x02 56*1bb76ff1Sjsg #define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 57*1bb76ff1Sjsg #define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 58*1bb76ff1Sjsg 59*1bb76ff1Sjsg #define FDO_MODE_HARDWARE 0 60*1bb76ff1Sjsg #define FDO_MODE_PIECE_WISE_LINEAR 1 61*1bb76ff1Sjsg 62*1bb76ff1Sjsg enum FAN_CONTROL { 63*1bb76ff1Sjsg FAN_CONTROL_FUZZY, 64*1bb76ff1Sjsg FAN_CONTROL_TABLE 65*1bb76ff1Sjsg }; 66*1bb76ff1Sjsg 67*1bb76ff1Sjsg #define PPSMC_Result_OK ((uint8_t)0x01) 68*1bb76ff1Sjsg #define PPSMC_Result_Failed ((uint8_t)0xFF) 69*1bb76ff1Sjsg 70*1bb76ff1Sjsg typedef uint8_t PPSMC_Result; 71*1bb76ff1Sjsg 72*1bb76ff1Sjsg #define PPSMC_MSG_Halt ((uint8_t)0x10) 73*1bb76ff1Sjsg #define PPSMC_MSG_Resume ((uint8_t)0x11) 74*1bb76ff1Sjsg #define PPSMC_MSG_ZeroLevelsDisabled ((uint8_t)0x13) 75*1bb76ff1Sjsg #define PPSMC_MSG_OneLevelsDisabled ((uint8_t)0x14) 76*1bb76ff1Sjsg #define PPSMC_MSG_TwoLevelsDisabled ((uint8_t)0x15) 77*1bb76ff1Sjsg #define PPSMC_MSG_EnableThermalInterrupt ((uint8_t)0x16) 78*1bb76ff1Sjsg #define PPSMC_MSG_RunningOnAC ((uint8_t)0x17) 79*1bb76ff1Sjsg #define PPSMC_MSG_SwitchToSwState ((uint8_t)0x20) 80*1bb76ff1Sjsg #define PPSMC_MSG_SwitchToInitialState ((uint8_t)0x40) 81*1bb76ff1Sjsg #define PPSMC_MSG_NoForcedLevel ((uint8_t)0x41) 82*1bb76ff1Sjsg #define PPSMC_MSG_ForceHigh ((uint8_t)0x42) 83*1bb76ff1Sjsg #define PPSMC_MSG_ForceMediumOrHigh ((uint8_t)0x43) 84*1bb76ff1Sjsg #define PPSMC_MSG_SwitchToMinimumPower ((uint8_t)0x51) 85*1bb76ff1Sjsg #define PPSMC_MSG_ResumeFromMinimumPower ((uint8_t)0x52) 86*1bb76ff1Sjsg #define PPSMC_MSG_EnableCac ((uint8_t)0x53) 87*1bb76ff1Sjsg #define PPSMC_MSG_DisableCac ((uint8_t)0x54) 88*1bb76ff1Sjsg #define PPSMC_TDPClampingActive ((uint8_t)0x59) 89*1bb76ff1Sjsg #define PPSMC_TDPClampingInactive ((uint8_t)0x5A) 90*1bb76ff1Sjsg #define PPSMC_StartFanControl ((uint8_t)0x5B) 91*1bb76ff1Sjsg #define PPSMC_StopFanControl ((uint8_t)0x5C) 92*1bb76ff1Sjsg #define PPSMC_MSG_NoDisplay ((uint8_t)0x5D) 93*1bb76ff1Sjsg #define PPSMC_NoDisplay ((uint8_t)0x5D) 94*1bb76ff1Sjsg #define PPSMC_MSG_HasDisplay ((uint8_t)0x5E) 95*1bb76ff1Sjsg #define PPSMC_HasDisplay ((uint8_t)0x5E) 96*1bb76ff1Sjsg #define PPSMC_MSG_UVDPowerOFF ((uint8_t)0x60) 97*1bb76ff1Sjsg #define PPSMC_MSG_UVDPowerON ((uint8_t)0x61) 98*1bb76ff1Sjsg #define PPSMC_MSG_EnableULV ((uint8_t)0x62) 99*1bb76ff1Sjsg #define PPSMC_MSG_DisableULV ((uint8_t)0x63) 100*1bb76ff1Sjsg #define PPSMC_MSG_EnterULV ((uint8_t)0x64) 101*1bb76ff1Sjsg #define PPSMC_MSG_ExitULV ((uint8_t)0x65) 102*1bb76ff1Sjsg #define PPSMC_CACLongTermAvgEnable ((uint8_t)0x6E) 103*1bb76ff1Sjsg #define PPSMC_CACLongTermAvgDisable ((uint8_t)0x6F) 104*1bb76ff1Sjsg #define PPSMC_MSG_CollectCAC_PowerCorreln ((uint8_t)0x7A) 105*1bb76ff1Sjsg #define PPSMC_FlushDataCache ((uint8_t)0x80) 106*1bb76ff1Sjsg #define PPSMC_MSG_SetEnabledLevels ((uint8_t)0x82) 107*1bb76ff1Sjsg #define PPSMC_MSG_SetForcedLevels ((uint8_t)0x83) 108*1bb76ff1Sjsg #define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84) 109*1bb76ff1Sjsg #define PPSMC_MSG_EnableDTE ((uint8_t)0x87) 110*1bb76ff1Sjsg #define PPSMC_MSG_DisableDTE ((uint8_t)0x88) 111*1bb76ff1Sjsg #define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint8_t)0x96) 112*1bb76ff1Sjsg #define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint8_t)0x97) 113*1bb76ff1Sjsg #define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149) 114*1bb76ff1Sjsg 115*1bb76ff1Sjsg /* CI/KV/KB */ 116*1bb76ff1Sjsg #define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) 117*1bb76ff1Sjsg #define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) 118*1bb76ff1Sjsg #define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) 119*1bb76ff1Sjsg #define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) 120*1bb76ff1Sjsg #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) 121*1bb76ff1Sjsg #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) 122*1bb76ff1Sjsg #define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) 123*1bb76ff1Sjsg #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) 124*1bb76ff1Sjsg #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) 125*1bb76ff1Sjsg #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) 126*1bb76ff1Sjsg #define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) 127*1bb76ff1Sjsg #define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) 128*1bb76ff1Sjsg #define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) 129*1bb76ff1Sjsg #define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) 130*1bb76ff1Sjsg #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) 131*1bb76ff1Sjsg #define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) 132*1bb76ff1Sjsg #define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) 133*1bb76ff1Sjsg #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) 134*1bb76ff1Sjsg #define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) 135*1bb76ff1Sjsg #define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) 136*1bb76ff1Sjsg #define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) 137*1bb76ff1Sjsg #define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) 138*1bb76ff1Sjsg #define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e) 139*1bb76ff1Sjsg #define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f) 140*1bb76ff1Sjsg #define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150) 141*1bb76ff1Sjsg #define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151) 142*1bb76ff1Sjsg #define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154) 143*1bb76ff1Sjsg #define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155) 144*1bb76ff1Sjsg #define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156) 145*1bb76ff1Sjsg #define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157) 146*1bb76ff1Sjsg #define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158) 147*1bb76ff1Sjsg #define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159) 148*1bb76ff1Sjsg #define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a) 149*1bb76ff1Sjsg #define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b) 150*1bb76ff1Sjsg #define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) 151*1bb76ff1Sjsg #define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) 152*1bb76ff1Sjsg #define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) 153*1bb76ff1Sjsg #define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) 154*1bb76ff1Sjsg #define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) 155*1bb76ff1Sjsg #define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) 156*1bb76ff1Sjsg #define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) 157*1bb76ff1Sjsg #define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) 158*1bb76ff1Sjsg #define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) 159*1bb76ff1Sjsg #define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) 160*1bb76ff1Sjsg #define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) 161*1bb76ff1Sjsg #define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) 162*1bb76ff1Sjsg #define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) 163*1bb76ff1Sjsg #define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) 164*1bb76ff1Sjsg #define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) 165*1bb76ff1Sjsg #define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) 166*1bb76ff1Sjsg #define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) 167*1bb76ff1Sjsg #define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205) 168*1bb76ff1Sjsg 169*1bb76ff1Sjsg #define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) 170*1bb76ff1Sjsg #define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) 171*1bb76ff1Sjsg 172*1bb76ff1Sjsg #define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) 173*1bb76ff1Sjsg #define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) 174*1bb76ff1Sjsg 175*1bb76ff1Sjsg /* TN */ 176*1bb76ff1Sjsg #define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) 177*1bb76ff1Sjsg #define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104) 178*1bb76ff1Sjsg #define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108) 179*1bb76ff1Sjsg #define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109) 180*1bb76ff1Sjsg #define PPSMC_MSG_Thermal_Cntl_Enable ((uint32_t) 0x10a) 181*1bb76ff1Sjsg #define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e) 182*1bb76ff1Sjsg #define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f) 183*1bb76ff1Sjsg #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112) 184*1bb76ff1Sjsg #define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d) 185*1bb76ff1Sjsg #define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e) 186*1bb76ff1Sjsg #define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120) 187*1bb76ff1Sjsg #define PPSMC_MSG_DisableBAPM ((uint32_t) 0x121) 188*1bb76ff1Sjsg #define PPSMC_MSG_UVD_DPM_Config ((uint32_t) 0x124) 189*1bb76ff1Sjsg 190*1bb76ff1Sjsg #define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250) 191*1bb76ff1Sjsg #define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251) 192*1bb76ff1Sjsg #define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252) 193*1bb76ff1Sjsg #define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253) 194*1bb76ff1Sjsg #define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254) 195*1bb76ff1Sjsg 196*1bb76ff1Sjsg typedef uint16_t PPSMC_Msg; 197*1bb76ff1Sjsg 198*1bb76ff1Sjsg #pragma pack(pop) 199*1bb76ff1Sjsg 200*1bb76ff1Sjsg #endif 201