1ad8b1aafSjsg /*
2ad8b1aafSjsg  * Copyright 2016 Advanced Micro Devices, Inc.
3ad8b1aafSjsg  *
4ad8b1aafSjsg  * Permission is hereby granted, free of charge, to any person obtaining a
5ad8b1aafSjsg  * copy of this software and associated documentation files (the "Software"),
6ad8b1aafSjsg  * to deal in the Software without restriction, including without limitation
7ad8b1aafSjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8ad8b1aafSjsg  * and/or sell copies of the Software, and to permit persons to whom the
9ad8b1aafSjsg  * Software is furnished to do so, subject to the following conditions:
10ad8b1aafSjsg  *
11ad8b1aafSjsg  * The above copyright notice and this permission notice shall be included in
12ad8b1aafSjsg  * all copies or substantial portions of the Software.
13ad8b1aafSjsg  *
14ad8b1aafSjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15ad8b1aafSjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16ad8b1aafSjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17ad8b1aafSjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18ad8b1aafSjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19ad8b1aafSjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20ad8b1aafSjsg  * OTHER DEALINGS IN THE SOFTWARE.
21ad8b1aafSjsg  *
22ad8b1aafSjsg  */
23ad8b1aafSjsg 
24ad8b1aafSjsg #include <asm/div64.h>
25ad8b1aafSjsg #include "smu7_thermal.h"
26ad8b1aafSjsg #include "smu7_hwmgr.h"
27ad8b1aafSjsg #include "smu7_common.h"
28ad8b1aafSjsg 
smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr * hwmgr,struct phm_fan_speed_info * fan_speed_info)29ad8b1aafSjsg int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
30ad8b1aafSjsg 		struct phm_fan_speed_info *fan_speed_info)
31ad8b1aafSjsg {
32ad8b1aafSjsg 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
33ad8b1aafSjsg 		return -ENODEV;
34ad8b1aafSjsg 
35ad8b1aafSjsg 	fan_speed_info->supports_percent_read = true;
36ad8b1aafSjsg 	fan_speed_info->supports_percent_write = true;
37ad8b1aafSjsg 	fan_speed_info->min_percent = 0;
38ad8b1aafSjsg 	fan_speed_info->max_percent = 100;
39ad8b1aafSjsg 
40ad8b1aafSjsg 	if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
41ad8b1aafSjsg 	    hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
42ad8b1aafSjsg 		fan_speed_info->supports_rpm_read = true;
43ad8b1aafSjsg 		fan_speed_info->supports_rpm_write = true;
44ad8b1aafSjsg 		fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM;
45ad8b1aafSjsg 		fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
46ad8b1aafSjsg 	} else {
47ad8b1aafSjsg 		fan_speed_info->min_rpm = 0;
48ad8b1aafSjsg 		fan_speed_info->max_rpm = 0;
49ad8b1aafSjsg 	}
50ad8b1aafSjsg 
51ad8b1aafSjsg 	return 0;
52ad8b1aafSjsg }
53ad8b1aafSjsg 
smu7_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr * hwmgr,uint32_t * speed)54*5ca02815Sjsg int smu7_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr,
55ad8b1aafSjsg 		uint32_t *speed)
56ad8b1aafSjsg {
57ad8b1aafSjsg 	uint32_t duty100;
58ad8b1aafSjsg 	uint32_t duty;
59ad8b1aafSjsg 	uint64_t tmp64;
60ad8b1aafSjsg 
61ad8b1aafSjsg 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
62ad8b1aafSjsg 		return -ENODEV;
63ad8b1aafSjsg 
64ad8b1aafSjsg 	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
65ad8b1aafSjsg 			CG_FDO_CTRL1, FMAX_DUTY100);
66ad8b1aafSjsg 	duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
67ad8b1aafSjsg 			CG_THERMAL_STATUS, FDO_PWM_DUTY);
68ad8b1aafSjsg 
69ad8b1aafSjsg 	if (duty100 == 0)
70ad8b1aafSjsg 		return -EINVAL;
71ad8b1aafSjsg 
72ad8b1aafSjsg 
73*5ca02815Sjsg 	tmp64 = (uint64_t)duty * 255;
74ad8b1aafSjsg 	do_div(tmp64, duty100);
75*5ca02815Sjsg 	*speed = MIN((uint32_t)tmp64, 255);
76ad8b1aafSjsg 
77ad8b1aafSjsg 	return 0;
78ad8b1aafSjsg }
79ad8b1aafSjsg 
smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr * hwmgr,uint32_t * speed)80ad8b1aafSjsg int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
81ad8b1aafSjsg {
82ad8b1aafSjsg 	uint32_t tach_period;
83ad8b1aafSjsg 	uint32_t crystal_clock_freq;
84ad8b1aafSjsg 
85ad8b1aafSjsg 	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
86ad8b1aafSjsg 	    !hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution)
87ad8b1aafSjsg 		return -ENODEV;
88ad8b1aafSjsg 
89ad8b1aafSjsg 	tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
90ad8b1aafSjsg 			CG_TACH_STATUS, TACH_PERIOD);
91ad8b1aafSjsg 
92ad8b1aafSjsg 	if (tach_period == 0)
93ad8b1aafSjsg 		return -EINVAL;
94ad8b1aafSjsg 
95ad8b1aafSjsg 	crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
96ad8b1aafSjsg 
97ad8b1aafSjsg 	*speed = 60 * crystal_clock_freq * 10000 / tach_period;
98ad8b1aafSjsg 
99ad8b1aafSjsg 	return 0;
100ad8b1aafSjsg }
101ad8b1aafSjsg 
102ad8b1aafSjsg /**
103*5ca02815Sjsg  * smu7_fan_ctrl_set_static_mode - Set Fan Speed Control to static mode, so that the user can decide what speed to use.
104*5ca02815Sjsg  * @hwmgr:  the address of the powerplay hardware manager.
105*5ca02815Sjsg  * @mode:   the fan control mode, 0 default, 1 by percent, 5, by RPM
106*5ca02815Sjsg  * Exception: Should always succeed.
107ad8b1aafSjsg  */
smu7_fan_ctrl_set_static_mode(struct pp_hwmgr * hwmgr,uint32_t mode)108ad8b1aafSjsg int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
109ad8b1aafSjsg {
110ad8b1aafSjsg 	if (hwmgr->fan_ctrl_is_in_default_mode) {
111ad8b1aafSjsg 		hwmgr->fan_ctrl_default_mode =
112ad8b1aafSjsg 				PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
113ad8b1aafSjsg 						CG_FDO_CTRL2, FDO_PWM_MODE);
114ad8b1aafSjsg 		hwmgr->tmin =
115ad8b1aafSjsg 				PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
116ad8b1aafSjsg 						CG_FDO_CTRL2, TMIN);
117ad8b1aafSjsg 		hwmgr->fan_ctrl_is_in_default_mode = false;
118ad8b1aafSjsg 	}
119ad8b1aafSjsg 
120ad8b1aafSjsg 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
121ad8b1aafSjsg 			CG_FDO_CTRL2, TMIN, 0);
122ad8b1aafSjsg 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
123ad8b1aafSjsg 			CG_FDO_CTRL2, FDO_PWM_MODE, mode);
124ad8b1aafSjsg 
125ad8b1aafSjsg 	return 0;
126ad8b1aafSjsg }
127ad8b1aafSjsg 
128ad8b1aafSjsg /**
129*5ca02815Sjsg  * smu7_fan_ctrl_set_default_mode - Reset Fan Speed Control to default mode.
130*5ca02815Sjsg  * @hwmgr:  the address of the powerplay hardware manager.
131*5ca02815Sjsg  * Exception: Should always succeed.
132ad8b1aafSjsg  */
smu7_fan_ctrl_set_default_mode(struct pp_hwmgr * hwmgr)133ad8b1aafSjsg int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
134ad8b1aafSjsg {
135ad8b1aafSjsg 	if (!hwmgr->fan_ctrl_is_in_default_mode) {
136ad8b1aafSjsg 		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
137ad8b1aafSjsg 				CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode);
138ad8b1aafSjsg 		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
139ad8b1aafSjsg 				CG_FDO_CTRL2, TMIN, hwmgr->tmin);
140ad8b1aafSjsg 		hwmgr->fan_ctrl_is_in_default_mode = true;
141ad8b1aafSjsg 	}
142ad8b1aafSjsg 
143ad8b1aafSjsg 	return 0;
144ad8b1aafSjsg }
145ad8b1aafSjsg 
smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr * hwmgr)146ad8b1aafSjsg int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
147ad8b1aafSjsg {
148ad8b1aafSjsg 	int result;
149ad8b1aafSjsg 
150ad8b1aafSjsg 	if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
151ad8b1aafSjsg 		result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_StartFanControl,
152ad8b1aafSjsg 					FAN_CONTROL_FUZZY, NULL);
153ad8b1aafSjsg 
154ad8b1aafSjsg 		if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM))
155ad8b1aafSjsg 			hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
156ad8b1aafSjsg 					hwmgr->thermal_controller.
157ad8b1aafSjsg 					advanceFanControlParameters.usMaxFanRPM);
158ad8b1aafSjsg 		else
159ad8b1aafSjsg 			hwmgr->hwmgr_func->set_max_fan_pwm_output(hwmgr,
160ad8b1aafSjsg 					hwmgr->thermal_controller.
161ad8b1aafSjsg 					advanceFanControlParameters.usMaxFanPWM);
162ad8b1aafSjsg 
163ad8b1aafSjsg 	} else {
164ad8b1aafSjsg 		result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_StartFanControl,
165ad8b1aafSjsg 					FAN_CONTROL_TABLE, NULL);
166ad8b1aafSjsg 	}
167ad8b1aafSjsg 
168ad8b1aafSjsg 	if (!result && hwmgr->thermal_controller.
169ad8b1aafSjsg 			advanceFanControlParameters.ucTargetTemperature)
170ad8b1aafSjsg 		result = smum_send_msg_to_smc_with_parameter(hwmgr,
171ad8b1aafSjsg 				PPSMC_MSG_SetFanTemperatureTarget,
172ad8b1aafSjsg 				hwmgr->thermal_controller.
173ad8b1aafSjsg 				advanceFanControlParameters.ucTargetTemperature,
174ad8b1aafSjsg 				NULL);
175*5ca02815Sjsg 
176*5ca02815Sjsg 	if (!result &&
177*5ca02815Sjsg 	    (hwmgr->chip_id == CHIP_POLARIS10 ||
178*5ca02815Sjsg 	    hwmgr->chip_id == CHIP_POLARIS11 ||
179*5ca02815Sjsg 	    hwmgr->chip_id == CHIP_POLARIS12) &&
180*5ca02815Sjsg 	    hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM &&
181*5ca02815Sjsg 	    !PP_CAP(PHM_PlatformCaps_customThermalManagement))
182*5ca02815Sjsg 		result = smum_send_msg_to_smc(hwmgr,
183*5ca02815Sjsg 				PPSMC_MSG_EnableZeroRpm,
184*5ca02815Sjsg 				NULL);
185*5ca02815Sjsg 
186ad8b1aafSjsg 	hwmgr->fan_ctrl_enabled = true;
187ad8b1aafSjsg 
188ad8b1aafSjsg 	return result;
189ad8b1aafSjsg }
190ad8b1aafSjsg 
191ad8b1aafSjsg 
smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr * hwmgr)192ad8b1aafSjsg int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
193ad8b1aafSjsg {
194ad8b1aafSjsg 	hwmgr->fan_ctrl_enabled = false;
195ad8b1aafSjsg 	return smum_send_msg_to_smc(hwmgr, PPSMC_StopFanControl, NULL);
196ad8b1aafSjsg }
197ad8b1aafSjsg 
198ad8b1aafSjsg /**
199*5ca02815Sjsg  * smu7_fan_ctrl_set_fan_speed_pwm - Set Fan Speed in PWM.
200*5ca02815Sjsg  * @hwmgr: the address of the powerplay hardware manager.
201*5ca02815Sjsg  * @speed: is the pwm value (0 - 255) to be set.
202ad8b1aafSjsg  */
smu7_fan_ctrl_set_fan_speed_pwm(struct pp_hwmgr * hwmgr,uint32_t speed)203*5ca02815Sjsg int smu7_fan_ctrl_set_fan_speed_pwm(struct pp_hwmgr *hwmgr,
204ad8b1aafSjsg 		uint32_t speed)
205ad8b1aafSjsg {
206ad8b1aafSjsg 	uint32_t duty100;
207ad8b1aafSjsg 	uint32_t duty;
208ad8b1aafSjsg 	uint64_t tmp64;
209ad8b1aafSjsg 
210ad8b1aafSjsg 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
211ad8b1aafSjsg 		return 0;
212ad8b1aafSjsg 
213*5ca02815Sjsg 	speed = MIN(speed, 255);
214ad8b1aafSjsg 
215ad8b1aafSjsg 	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
216ad8b1aafSjsg 		smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
217ad8b1aafSjsg 
218ad8b1aafSjsg 	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
219ad8b1aafSjsg 			CG_FDO_CTRL1, FMAX_DUTY100);
220ad8b1aafSjsg 
221ad8b1aafSjsg 	if (duty100 == 0)
222ad8b1aafSjsg 		return -EINVAL;
223ad8b1aafSjsg 
224ad8b1aafSjsg 	tmp64 = (uint64_t)speed * duty100;
225*5ca02815Sjsg 	do_div(tmp64, 255);
226ad8b1aafSjsg 	duty = (uint32_t)tmp64;
227ad8b1aafSjsg 
228ad8b1aafSjsg 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
229ad8b1aafSjsg 			CG_FDO_CTRL0, FDO_STATIC_DUTY, duty);
230ad8b1aafSjsg 
231ad8b1aafSjsg 	return smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
232ad8b1aafSjsg }
233ad8b1aafSjsg 
234ad8b1aafSjsg /**
235*5ca02815Sjsg * smu7_fan_ctrl_reset_fan_speed_to_default - Reset Fan Speed to default.
236*5ca02815Sjsg * @hwmgr:  the address of the powerplay hardware manager.
237*5ca02815Sjsg * Exception: Always succeeds.
238ad8b1aafSjsg */
smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr * hwmgr)239ad8b1aafSjsg int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
240ad8b1aafSjsg {
241ad8b1aafSjsg 	int result;
242ad8b1aafSjsg 
243ad8b1aafSjsg 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
244ad8b1aafSjsg 		return 0;
245ad8b1aafSjsg 
246ad8b1aafSjsg 	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {
247ad8b1aafSjsg 		result = smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
248ad8b1aafSjsg 		if (!result)
249ad8b1aafSjsg 			result = smu7_fan_ctrl_start_smc_fan_control(hwmgr);
250ad8b1aafSjsg 	} else
251ad8b1aafSjsg 		result = smu7_fan_ctrl_set_default_mode(hwmgr);
252ad8b1aafSjsg 
253ad8b1aafSjsg 	return result;
254ad8b1aafSjsg }
255ad8b1aafSjsg 
256ad8b1aafSjsg /**
257*5ca02815Sjsg  * smu7_fan_ctrl_set_fan_speed_rpm - Set Fan Speed in RPM.
258*5ca02815Sjsg  * @hwmgr: the address of the powerplay hardware manager.
259*5ca02815Sjsg  * @speed: is the percentage value (min - max) to be set.
260*5ca02815Sjsg  * Exception: Fails is the speed not lie between min and max.
261ad8b1aafSjsg  */
smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr * hwmgr,uint32_t speed)262ad8b1aafSjsg int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
263ad8b1aafSjsg {
264ad8b1aafSjsg 	uint32_t tach_period;
265ad8b1aafSjsg 	uint32_t crystal_clock_freq;
266ad8b1aafSjsg 
267ad8b1aafSjsg 	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
268ad8b1aafSjsg 			(hwmgr->thermal_controller.fanInfo.
269ad8b1aafSjsg 			ucTachometerPulsesPerRevolution == 0) ||
270ad8b1aafSjsg 			speed == 0 ||
271ad8b1aafSjsg 			(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
272ad8b1aafSjsg 			(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
273ad8b1aafSjsg 		return 0;
274ad8b1aafSjsg 
275ad8b1aafSjsg 	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
276ad8b1aafSjsg 		smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
277ad8b1aafSjsg 
278ad8b1aafSjsg 	crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
279ad8b1aafSjsg 
280ad8b1aafSjsg 	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
281ad8b1aafSjsg 
282ad8b1aafSjsg 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
283ad8b1aafSjsg 				CG_TACH_CTRL, TARGET_PERIOD, tach_period);
284ad8b1aafSjsg 
285ad8b1aafSjsg 	return smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
286ad8b1aafSjsg }
287ad8b1aafSjsg 
288ad8b1aafSjsg /**
289*5ca02815Sjsg  * smu7_thermal_get_temperature - Reads the remote temperature from the SIslands thermal controller.
290ad8b1aafSjsg  *
291*5ca02815Sjsg  * @hwmgr: The address of the hardware manager.
292ad8b1aafSjsg  */
smu7_thermal_get_temperature(struct pp_hwmgr * hwmgr)293ad8b1aafSjsg int smu7_thermal_get_temperature(struct pp_hwmgr *hwmgr)
294ad8b1aafSjsg {
295ad8b1aafSjsg 	int temp;
296ad8b1aafSjsg 
297ad8b1aafSjsg 	temp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
298ad8b1aafSjsg 			CG_MULT_THERMAL_STATUS, CTF_TEMP);
299ad8b1aafSjsg 
300ad8b1aafSjsg 	/* Bit 9 means the reading is lower than the lowest usable value. */
301ad8b1aafSjsg 	if (temp & 0x200)
302ad8b1aafSjsg 		temp = SMU7_THERMAL_MAXIMUM_TEMP_READING;
303ad8b1aafSjsg 	else
304ad8b1aafSjsg 		temp = temp & 0x1ff;
305ad8b1aafSjsg 
306ad8b1aafSjsg 	temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
307ad8b1aafSjsg 
308ad8b1aafSjsg 	return temp;
309ad8b1aafSjsg }
310ad8b1aafSjsg 
311ad8b1aafSjsg /**
312*5ca02815Sjsg  * smu7_thermal_set_temperature_range - Set the requested temperature range for high and low alert signals
313ad8b1aafSjsg  *
314*5ca02815Sjsg  * @hwmgr: The address of the hardware manager.
315*5ca02815Sjsg  * @low_temp: Temperature to be programmed for high alert signals
316*5ca02815Sjsg  * @high_temp: Temperature to be programmed for low alert signals
317*5ca02815Sjsg  * Exception: PP_Result_BadInput if the input data is not valid.
318ad8b1aafSjsg  */
smu7_thermal_set_temperature_range(struct pp_hwmgr * hwmgr,int low_temp,int high_temp)319ad8b1aafSjsg static int smu7_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
320ad8b1aafSjsg 		int low_temp, int high_temp)
321ad8b1aafSjsg {
322ad8b1aafSjsg 	int low = SMU7_THERMAL_MINIMUM_ALERT_TEMP *
323ad8b1aafSjsg 			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
324ad8b1aafSjsg 	int high = SMU7_THERMAL_MAXIMUM_ALERT_TEMP *
325ad8b1aafSjsg 			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
326ad8b1aafSjsg 
327ad8b1aafSjsg 	if (low < low_temp)
328ad8b1aafSjsg 		low = low_temp;
329ad8b1aafSjsg 	if (high > high_temp)
330ad8b1aafSjsg 		high = high_temp;
331ad8b1aafSjsg 
332ad8b1aafSjsg 	if (low > high)
333ad8b1aafSjsg 		return -EINVAL;
334ad8b1aafSjsg 
335ad8b1aafSjsg 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
336ad8b1aafSjsg 			CG_THERMAL_INT, DIG_THERM_INTH,
337ad8b1aafSjsg 			(high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
338ad8b1aafSjsg 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
339ad8b1aafSjsg 			CG_THERMAL_INT, DIG_THERM_INTL,
340ad8b1aafSjsg 			(low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
341ad8b1aafSjsg 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
342ad8b1aafSjsg 			CG_THERMAL_CTRL, DIG_THERM_DPM,
343ad8b1aafSjsg 			(high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
344ad8b1aafSjsg 
345ad8b1aafSjsg 	return 0;
346ad8b1aafSjsg }
347ad8b1aafSjsg 
348ad8b1aafSjsg /**
349*5ca02815Sjsg  * smu7_thermal_initialize - Programs thermal controller one-time setting registers
350ad8b1aafSjsg  *
351*5ca02815Sjsg  * @hwmgr: The address of the hardware manager.
352ad8b1aafSjsg  */
smu7_thermal_initialize(struct pp_hwmgr * hwmgr)353ad8b1aafSjsg static int smu7_thermal_initialize(struct pp_hwmgr *hwmgr)
354ad8b1aafSjsg {
355ad8b1aafSjsg 	if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution)
356ad8b1aafSjsg 		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
357ad8b1aafSjsg 				CG_TACH_CTRL, EDGE_PER_REV,
358ad8b1aafSjsg 				hwmgr->thermal_controller.fanInfo.
359ad8b1aafSjsg 				ucTachometerPulsesPerRevolution - 1);
360ad8b1aafSjsg 
361ad8b1aafSjsg 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
362ad8b1aafSjsg 			CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28);
363ad8b1aafSjsg 
364ad8b1aafSjsg 	return 0;
365ad8b1aafSjsg }
366ad8b1aafSjsg 
367ad8b1aafSjsg /**
368*5ca02815Sjsg  * smu7_thermal_enable_alert - Enable thermal alerts on the RV770 thermal controller.
369ad8b1aafSjsg  *
370*5ca02815Sjsg  * @hwmgr: The address of the hardware manager.
371ad8b1aafSjsg  */
smu7_thermal_enable_alert(struct pp_hwmgr * hwmgr)372ad8b1aafSjsg static void smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr)
373ad8b1aafSjsg {
374ad8b1aafSjsg 	uint32_t alert;
375ad8b1aafSjsg 
376ad8b1aafSjsg 	alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
377ad8b1aafSjsg 			CG_THERMAL_INT, THERM_INT_MASK);
378ad8b1aafSjsg 	alert &= ~(SMU7_THERMAL_HIGH_ALERT_MASK | SMU7_THERMAL_LOW_ALERT_MASK);
379ad8b1aafSjsg 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
380ad8b1aafSjsg 			CG_THERMAL_INT, THERM_INT_MASK, alert);
381ad8b1aafSjsg 
382ad8b1aafSjsg 	/* send message to SMU to enable internal thermal interrupts */
383ad8b1aafSjsg 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Enable, NULL);
384ad8b1aafSjsg }
385ad8b1aafSjsg 
386ad8b1aafSjsg /**
387*5ca02815Sjsg  * smu7_thermal_disable_alert - Disable thermal alerts on the RV770 thermal controller.
388*5ca02815Sjsg  * @hwmgr: The address of the hardware manager.
389ad8b1aafSjsg  */
smu7_thermal_disable_alert(struct pp_hwmgr * hwmgr)390ad8b1aafSjsg int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr)
391ad8b1aafSjsg {
392ad8b1aafSjsg 	uint32_t alert;
393ad8b1aafSjsg 
394ad8b1aafSjsg 	alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
395ad8b1aafSjsg 			CG_THERMAL_INT, THERM_INT_MASK);
396ad8b1aafSjsg 	alert |= (SMU7_THERMAL_HIGH_ALERT_MASK | SMU7_THERMAL_LOW_ALERT_MASK);
397ad8b1aafSjsg 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
398ad8b1aafSjsg 			CG_THERMAL_INT, THERM_INT_MASK, alert);
399ad8b1aafSjsg 
400ad8b1aafSjsg 	/* send message to SMU to disable internal thermal interrupts */
401ad8b1aafSjsg 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Disable, NULL);
402ad8b1aafSjsg }
403ad8b1aafSjsg 
404ad8b1aafSjsg /**
405*5ca02815Sjsg  * smu7_thermal_stop_thermal_controller - Uninitialize the thermal controller.
406ad8b1aafSjsg  * Currently just disables alerts.
407*5ca02815Sjsg  * @hwmgr: The address of the hardware manager.
408ad8b1aafSjsg  */
smu7_thermal_stop_thermal_controller(struct pp_hwmgr * hwmgr)409ad8b1aafSjsg int smu7_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
410ad8b1aafSjsg {
411ad8b1aafSjsg 	int result = smu7_thermal_disable_alert(hwmgr);
412ad8b1aafSjsg 
413ad8b1aafSjsg 	if (!hwmgr->thermal_controller.fanInfo.bNoFan)
414ad8b1aafSjsg 		smu7_fan_ctrl_set_default_mode(hwmgr);
415ad8b1aafSjsg 
416ad8b1aafSjsg 	return result;
417ad8b1aafSjsg }
418ad8b1aafSjsg 
419ad8b1aafSjsg /**
420*5ca02815Sjsg  * smu7_thermal_start_smc_fan_control - Start the fan control on the SMC.
421*5ca02815Sjsg  * @hwmgr:  the address of the powerplay hardware manager.
422*5ca02815Sjsg  * Return:   result from set temperature range routine
423ad8b1aafSjsg  */
smu7_thermal_start_smc_fan_control(struct pp_hwmgr * hwmgr)424ad8b1aafSjsg static int smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
425ad8b1aafSjsg {
426ad8b1aafSjsg /* If the fantable setup has failed we could have disabled
427ad8b1aafSjsg  * PHM_PlatformCaps_MicrocodeFanControl even after
428ad8b1aafSjsg  * this function was included in the table.
429ad8b1aafSjsg  * Make sure that we still think controlling the fan is OK.
430ad8b1aafSjsg */
431ad8b1aafSjsg 	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {
432ad8b1aafSjsg 		smu7_fan_ctrl_start_smc_fan_control(hwmgr);
433ad8b1aafSjsg 		smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
434ad8b1aafSjsg 	}
435ad8b1aafSjsg 
436ad8b1aafSjsg 	return 0;
437ad8b1aafSjsg }
438ad8b1aafSjsg 
smu7_start_thermal_controller(struct pp_hwmgr * hwmgr,struct PP_TemperatureRange * range)439ad8b1aafSjsg int smu7_start_thermal_controller(struct pp_hwmgr *hwmgr,
440ad8b1aafSjsg 				struct PP_TemperatureRange *range)
441ad8b1aafSjsg {
442ad8b1aafSjsg 	int ret = 0;
443ad8b1aafSjsg 
444ad8b1aafSjsg 	if (range == NULL)
445ad8b1aafSjsg 		return -EINVAL;
446ad8b1aafSjsg 
447ad8b1aafSjsg 	smu7_thermal_initialize(hwmgr);
448ad8b1aafSjsg 	ret = smu7_thermal_set_temperature_range(hwmgr, range->min, range->max);
449ad8b1aafSjsg 	if (ret)
450ad8b1aafSjsg 		return -EINVAL;
451ad8b1aafSjsg 	smu7_thermal_enable_alert(hwmgr);
452ad8b1aafSjsg 	ret = smum_thermal_avfs_enable(hwmgr);
453ad8b1aafSjsg 	if (ret)
454ad8b1aafSjsg 		return -EINVAL;
455ad8b1aafSjsg 
456ad8b1aafSjsg /* We should restrict performance levels to low before we halt the SMC.
457ad8b1aafSjsg  * On the other hand we are still in boot state when we do this
458ad8b1aafSjsg  * so it would be pointless.
459ad8b1aafSjsg  * If this assumption changes we have to revisit this table.
460ad8b1aafSjsg  */
461ad8b1aafSjsg 	smum_thermal_setup_fan_table(hwmgr);
462ad8b1aafSjsg 	smu7_thermal_start_smc_fan_control(hwmgr);
463ad8b1aafSjsg 	return 0;
464ad8b1aafSjsg }
465ad8b1aafSjsg 
466ad8b1aafSjsg 
467ad8b1aafSjsg 
smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr * hwmgr)468ad8b1aafSjsg int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
469ad8b1aafSjsg {
470ad8b1aafSjsg 	if (!hwmgr->thermal_controller.fanInfo.bNoFan)
471ad8b1aafSjsg 		smu7_fan_ctrl_set_default_mode(hwmgr);
472ad8b1aafSjsg 	return 0;
473ad8b1aafSjsg }
474ad8b1aafSjsg 
475