1ad8b1aafSjsg /*
2ad8b1aafSjsg * Copyright 2016 Advanced Micro Devices, Inc.
3ad8b1aafSjsg *
4ad8b1aafSjsg * Permission is hereby granted, free of charge, to any person obtaining a
5ad8b1aafSjsg * copy of this software and associated documentation files (the "Software"),
6ad8b1aafSjsg * to deal in the Software without restriction, including without limitation
7ad8b1aafSjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8ad8b1aafSjsg * and/or sell copies of the Software, and to permit persons to whom the
9ad8b1aafSjsg * Software is furnished to do so, subject to the following conditions:
10ad8b1aafSjsg *
11ad8b1aafSjsg * The above copyright notice and this permission notice shall be included in
12ad8b1aafSjsg * all copies or substantial portions of the Software.
13ad8b1aafSjsg *
14ad8b1aafSjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15ad8b1aafSjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16ad8b1aafSjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17ad8b1aafSjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18ad8b1aafSjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19ad8b1aafSjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20ad8b1aafSjsg * OTHER DEALINGS IN THE SOFTWARE.
21ad8b1aafSjsg *
22ad8b1aafSjsg */
23ad8b1aafSjsg
24ad8b1aafSjsg #include "vega10_thermal.h"
25ad8b1aafSjsg #include "vega10_hwmgr.h"
26ad8b1aafSjsg #include "vega10_smumgr.h"
27ad8b1aafSjsg #include "vega10_ppsmc.h"
28ad8b1aafSjsg #include "vega10_inc.h"
29ad8b1aafSjsg #include "soc15_common.h"
30ad8b1aafSjsg #include "pp_debug.h"
31ad8b1aafSjsg
vega10_get_current_rpm(struct pp_hwmgr * hwmgr,uint32_t * current_rpm)32ad8b1aafSjsg static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
33ad8b1aafSjsg {
34ad8b1aafSjsg smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm, current_rpm);
35ad8b1aafSjsg return 0;
36ad8b1aafSjsg }
37ad8b1aafSjsg
vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr * hwmgr,struct phm_fan_speed_info * fan_speed_info)38ad8b1aafSjsg int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
39ad8b1aafSjsg struct phm_fan_speed_info *fan_speed_info)
40ad8b1aafSjsg {
41ad8b1aafSjsg
42ad8b1aafSjsg if (hwmgr->thermal_controller.fanInfo.bNoFan)
43ad8b1aafSjsg return 0;
44ad8b1aafSjsg
45ad8b1aafSjsg fan_speed_info->supports_percent_read = true;
46ad8b1aafSjsg fan_speed_info->supports_percent_write = true;
47ad8b1aafSjsg fan_speed_info->min_percent = 0;
48ad8b1aafSjsg fan_speed_info->max_percent = 100;
49ad8b1aafSjsg
50ad8b1aafSjsg if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
51ad8b1aafSjsg hwmgr->thermal_controller.fanInfo.
52ad8b1aafSjsg ucTachometerPulsesPerRevolution) {
53ad8b1aafSjsg fan_speed_info->supports_rpm_read = true;
54ad8b1aafSjsg fan_speed_info->supports_rpm_write = true;
55ad8b1aafSjsg fan_speed_info->min_rpm =
56ad8b1aafSjsg hwmgr->thermal_controller.fanInfo.ulMinRPM;
57ad8b1aafSjsg fan_speed_info->max_rpm =
58ad8b1aafSjsg hwmgr->thermal_controller.fanInfo.ulMaxRPM;
59ad8b1aafSjsg } else {
60ad8b1aafSjsg fan_speed_info->min_rpm = 0;
61ad8b1aafSjsg fan_speed_info->max_rpm = 0;
62ad8b1aafSjsg }
63ad8b1aafSjsg
64ad8b1aafSjsg return 0;
65ad8b1aafSjsg }
66ad8b1aafSjsg
vega10_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr * hwmgr,uint32_t * speed)675ca02815Sjsg int vega10_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr,
68ad8b1aafSjsg uint32_t *speed)
69ad8b1aafSjsg {
70*2e34c102Sjsg struct amdgpu_device *adev = hwmgr->adev;
71*2e34c102Sjsg uint32_t duty100, duty;
72*2e34c102Sjsg uint64_t tmp64;
73ad8b1aafSjsg
74*2e34c102Sjsg duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
75*2e34c102Sjsg CG_FDO_CTRL1, FMAX_DUTY100);
76*2e34c102Sjsg duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
77*2e34c102Sjsg CG_THERMAL_STATUS, FDO_PWM_DUTY);
78ad8b1aafSjsg
79*2e34c102Sjsg if (!duty100)
80*2e34c102Sjsg return -EINVAL;
81ad8b1aafSjsg
82*2e34c102Sjsg tmp64 = (uint64_t)duty * 255;
83*2e34c102Sjsg do_div(tmp64, duty100);
84*2e34c102Sjsg *speed = MIN((uint32_t)tmp64, 255);
85ad8b1aafSjsg
86ad8b1aafSjsg return 0;
87ad8b1aafSjsg }
88ad8b1aafSjsg
vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr * hwmgr,uint32_t * speed)89ad8b1aafSjsg int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
90ad8b1aafSjsg {
91ad8b1aafSjsg struct amdgpu_device *adev = hwmgr->adev;
92ad8b1aafSjsg struct vega10_hwmgr *data = hwmgr->backend;
93ad8b1aafSjsg uint32_t tach_period;
94ad8b1aafSjsg uint32_t crystal_clock_freq;
95ad8b1aafSjsg int result = 0;
96ad8b1aafSjsg
97ad8b1aafSjsg if (hwmgr->thermal_controller.fanInfo.bNoFan)
98ad8b1aafSjsg return -1;
99ad8b1aafSjsg
100ad8b1aafSjsg if (data->smu_features[GNLD_FAN_CONTROL].supported) {
101ad8b1aafSjsg result = vega10_get_current_rpm(hwmgr, speed);
102ad8b1aafSjsg } else {
103ad8b1aafSjsg tach_period =
104ad8b1aafSjsg REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
105ad8b1aafSjsg CG_TACH_STATUS,
106ad8b1aafSjsg TACH_PERIOD);
107ad8b1aafSjsg
108ad8b1aafSjsg if (tach_period == 0)
109ad8b1aafSjsg return -EINVAL;
110ad8b1aafSjsg
111ad8b1aafSjsg crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
112ad8b1aafSjsg
113ad8b1aafSjsg *speed = 60 * crystal_clock_freq * 10000 / tach_period;
114ad8b1aafSjsg }
115ad8b1aafSjsg
116ad8b1aafSjsg return result;
117ad8b1aafSjsg }
118ad8b1aafSjsg
119ad8b1aafSjsg /**
1205ca02815Sjsg * vega10_fan_ctrl_set_static_mode - Set Fan Speed Control to static mode,
121ad8b1aafSjsg * so that the user can decide what speed to use.
1225ca02815Sjsg * @hwmgr: the address of the powerplay hardware manager.
1235ca02815Sjsg * @mode: the fan control mode, 0 default, 1 by percent, 5, by RPM
1245ca02815Sjsg * Exception: Should always succeed.
125ad8b1aafSjsg */
vega10_fan_ctrl_set_static_mode(struct pp_hwmgr * hwmgr,uint32_t mode)126ad8b1aafSjsg int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
127ad8b1aafSjsg {
128ad8b1aafSjsg struct amdgpu_device *adev = hwmgr->adev;
129ad8b1aafSjsg
130ad8b1aafSjsg if (hwmgr->fan_ctrl_is_in_default_mode) {
131ad8b1aafSjsg hwmgr->fan_ctrl_default_mode =
132ad8b1aafSjsg REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
133ad8b1aafSjsg CG_FDO_CTRL2, FDO_PWM_MODE);
134ad8b1aafSjsg hwmgr->tmin =
135ad8b1aafSjsg REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
136ad8b1aafSjsg CG_FDO_CTRL2, TMIN);
137ad8b1aafSjsg hwmgr->fan_ctrl_is_in_default_mode = false;
138ad8b1aafSjsg }
139ad8b1aafSjsg
140ad8b1aafSjsg WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
141ad8b1aafSjsg REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
142ad8b1aafSjsg CG_FDO_CTRL2, TMIN, 0));
143ad8b1aafSjsg WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
144ad8b1aafSjsg REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
145ad8b1aafSjsg CG_FDO_CTRL2, FDO_PWM_MODE, mode));
146ad8b1aafSjsg
147ad8b1aafSjsg return 0;
148ad8b1aafSjsg }
149ad8b1aafSjsg
150ad8b1aafSjsg /**
1515ca02815Sjsg * vega10_fan_ctrl_set_default_mode - Reset Fan Speed Control to default mode.
1525ca02815Sjsg * @hwmgr: the address of the powerplay hardware manager.
1535ca02815Sjsg * Exception: Should always succeed.
154ad8b1aafSjsg */
vega10_fan_ctrl_set_default_mode(struct pp_hwmgr * hwmgr)155ad8b1aafSjsg int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
156ad8b1aafSjsg {
157ad8b1aafSjsg struct amdgpu_device *adev = hwmgr->adev;
158ad8b1aafSjsg
159ad8b1aafSjsg if (!hwmgr->fan_ctrl_is_in_default_mode) {
160ad8b1aafSjsg WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
161ad8b1aafSjsg REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
162ad8b1aafSjsg CG_FDO_CTRL2, FDO_PWM_MODE,
163ad8b1aafSjsg hwmgr->fan_ctrl_default_mode));
164ad8b1aafSjsg WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
165ad8b1aafSjsg REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
166ad8b1aafSjsg CG_FDO_CTRL2, TMIN,
167ad8b1aafSjsg hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
168ad8b1aafSjsg hwmgr->fan_ctrl_is_in_default_mode = true;
169ad8b1aafSjsg }
170ad8b1aafSjsg
171ad8b1aafSjsg return 0;
172ad8b1aafSjsg }
173ad8b1aafSjsg
174ad8b1aafSjsg /**
1755ca02815Sjsg * vega10_enable_fan_control_feature - Enables the SMC Fan Control Feature.
176ad8b1aafSjsg *
1775ca02815Sjsg * @hwmgr: the address of the powerplay hardware manager.
1785ca02815Sjsg * Return: 0 on success. -1 otherwise.
179ad8b1aafSjsg */
vega10_enable_fan_control_feature(struct pp_hwmgr * hwmgr)180ad8b1aafSjsg static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
181ad8b1aafSjsg {
182ad8b1aafSjsg struct vega10_hwmgr *data = hwmgr->backend;
183ad8b1aafSjsg
184ad8b1aafSjsg if (data->smu_features[GNLD_FAN_CONTROL].supported) {
185ad8b1aafSjsg PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
186ad8b1aafSjsg hwmgr, true,
187ad8b1aafSjsg data->smu_features[GNLD_FAN_CONTROL].
188ad8b1aafSjsg smu_feature_bitmap),
189ad8b1aafSjsg "Attempt to Enable FAN CONTROL feature Failed!",
190ad8b1aafSjsg return -1);
191ad8b1aafSjsg data->smu_features[GNLD_FAN_CONTROL].enabled = true;
192ad8b1aafSjsg }
193ad8b1aafSjsg
194ad8b1aafSjsg return 0;
195ad8b1aafSjsg }
196ad8b1aafSjsg
vega10_disable_fan_control_feature(struct pp_hwmgr * hwmgr)197ad8b1aafSjsg static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
198ad8b1aafSjsg {
199ad8b1aafSjsg struct vega10_hwmgr *data = hwmgr->backend;
200ad8b1aafSjsg
201ad8b1aafSjsg if (data->smu_features[GNLD_FAN_CONTROL].supported) {
202ad8b1aafSjsg PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
203ad8b1aafSjsg hwmgr, false,
204ad8b1aafSjsg data->smu_features[GNLD_FAN_CONTROL].
205ad8b1aafSjsg smu_feature_bitmap),
206ad8b1aafSjsg "Attempt to Enable FAN CONTROL feature Failed!",
207ad8b1aafSjsg return -1);
208ad8b1aafSjsg data->smu_features[GNLD_FAN_CONTROL].enabled = false;
209ad8b1aafSjsg }
210ad8b1aafSjsg
211ad8b1aafSjsg return 0;
212ad8b1aafSjsg }
213ad8b1aafSjsg
vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr * hwmgr)214ad8b1aafSjsg int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
215ad8b1aafSjsg {
216ad8b1aafSjsg if (hwmgr->thermal_controller.fanInfo.bNoFan)
217ad8b1aafSjsg return -1;
218ad8b1aafSjsg
219ad8b1aafSjsg PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
220ad8b1aafSjsg "Attempt to Enable SMC FAN CONTROL Feature Failed!",
221ad8b1aafSjsg return -1);
222ad8b1aafSjsg
223ad8b1aafSjsg return 0;
224ad8b1aafSjsg }
225ad8b1aafSjsg
226ad8b1aafSjsg
vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr * hwmgr)227ad8b1aafSjsg int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
228ad8b1aafSjsg {
229ad8b1aafSjsg struct vega10_hwmgr *data = hwmgr->backend;
230ad8b1aafSjsg
231ad8b1aafSjsg if (hwmgr->thermal_controller.fanInfo.bNoFan)
232ad8b1aafSjsg return -1;
233ad8b1aafSjsg
234ad8b1aafSjsg if (data->smu_features[GNLD_FAN_CONTROL].supported) {
235ad8b1aafSjsg PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
236ad8b1aafSjsg "Attempt to Disable SMC FAN CONTROL Feature Failed!",
237ad8b1aafSjsg return -1);
238ad8b1aafSjsg }
239ad8b1aafSjsg return 0;
240ad8b1aafSjsg }
241ad8b1aafSjsg
242ad8b1aafSjsg /**
2435ca02815Sjsg * vega10_fan_ctrl_set_fan_speed_pwm - Set Fan Speed in PWM.
2445ca02815Sjsg * @hwmgr: the address of the powerplay hardware manager.
2455ca02815Sjsg * @speed: is the percentage value (0 - 255) to be set.
246ad8b1aafSjsg */
vega10_fan_ctrl_set_fan_speed_pwm(struct pp_hwmgr * hwmgr,uint32_t speed)2475ca02815Sjsg int vega10_fan_ctrl_set_fan_speed_pwm(struct pp_hwmgr *hwmgr,
248ad8b1aafSjsg uint32_t speed)
249ad8b1aafSjsg {
250ad8b1aafSjsg struct amdgpu_device *adev = hwmgr->adev;
251ad8b1aafSjsg uint32_t duty100;
252ad8b1aafSjsg uint32_t duty;
253ad8b1aafSjsg uint64_t tmp64;
254ad8b1aafSjsg
255ad8b1aafSjsg if (hwmgr->thermal_controller.fanInfo.bNoFan)
256ad8b1aafSjsg return 0;
257ad8b1aafSjsg
2585ca02815Sjsg speed = MIN(speed, 255);
259ad8b1aafSjsg
260ad8b1aafSjsg if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
261ad8b1aafSjsg vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
262ad8b1aafSjsg
263ad8b1aafSjsg duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
264ad8b1aafSjsg CG_FDO_CTRL1, FMAX_DUTY100);
265ad8b1aafSjsg
266ad8b1aafSjsg if (duty100 == 0)
267ad8b1aafSjsg return -EINVAL;
268ad8b1aafSjsg
269ad8b1aafSjsg tmp64 = (uint64_t)speed * duty100;
2705ca02815Sjsg do_div(tmp64, 255);
271ad8b1aafSjsg duty = (uint32_t)tmp64;
272ad8b1aafSjsg
273ad8b1aafSjsg WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
274ad8b1aafSjsg REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
275ad8b1aafSjsg CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
276ad8b1aafSjsg
277ad8b1aafSjsg return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
278ad8b1aafSjsg }
279ad8b1aafSjsg
280ad8b1aafSjsg /**
2815ca02815Sjsg * vega10_fan_ctrl_reset_fan_speed_to_default - Reset Fan Speed to default.
2825ca02815Sjsg * @hwmgr: the address of the powerplay hardware manager.
2835ca02815Sjsg * Exception: Always succeeds.
284ad8b1aafSjsg */
vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr * hwmgr)285ad8b1aafSjsg int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
286ad8b1aafSjsg {
287ad8b1aafSjsg if (hwmgr->thermal_controller.fanInfo.bNoFan)
288ad8b1aafSjsg return 0;
289ad8b1aafSjsg
290ad8b1aafSjsg if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
291ad8b1aafSjsg return vega10_fan_ctrl_start_smc_fan_control(hwmgr);
292ad8b1aafSjsg else
293ad8b1aafSjsg return vega10_fan_ctrl_set_default_mode(hwmgr);
294ad8b1aafSjsg }
295ad8b1aafSjsg
296ad8b1aafSjsg /**
2975ca02815Sjsg * vega10_fan_ctrl_set_fan_speed_rpm - Set Fan Speed in RPM.
2985ca02815Sjsg * @hwmgr: the address of the powerplay hardware manager.
2995ca02815Sjsg * @speed: is the percentage value (min - max) to be set.
3005ca02815Sjsg * Exception: Fails is the speed not lie between min and max.
301ad8b1aafSjsg */
vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr * hwmgr,uint32_t speed)302ad8b1aafSjsg int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
303ad8b1aafSjsg {
304ad8b1aafSjsg struct amdgpu_device *adev = hwmgr->adev;
305ad8b1aafSjsg uint32_t tach_period;
306ad8b1aafSjsg uint32_t crystal_clock_freq;
307ad8b1aafSjsg int result = 0;
308ad8b1aafSjsg
309ad8b1aafSjsg if (hwmgr->thermal_controller.fanInfo.bNoFan ||
310ad8b1aafSjsg speed == 0 ||
311ad8b1aafSjsg (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
312ad8b1aafSjsg (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
313ad8b1aafSjsg return -1;
314ad8b1aafSjsg
315ad8b1aafSjsg if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
316ad8b1aafSjsg result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
317ad8b1aafSjsg
318ad8b1aafSjsg if (!result) {
319ad8b1aafSjsg crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
320ad8b1aafSjsg tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
321ad8b1aafSjsg WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
322ad8b1aafSjsg REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
323ad8b1aafSjsg CG_TACH_CTRL, TARGET_PERIOD,
324ad8b1aafSjsg tach_period));
325ad8b1aafSjsg }
326ad8b1aafSjsg return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
327ad8b1aafSjsg }
328ad8b1aafSjsg
329ad8b1aafSjsg /**
3305ca02815Sjsg * vega10_thermal_get_temperature - Reads the remote temperature from the SIslands thermal controller.
331ad8b1aafSjsg *
3325ca02815Sjsg * @hwmgr: The address of the hardware manager.
333ad8b1aafSjsg */
vega10_thermal_get_temperature(struct pp_hwmgr * hwmgr)334ad8b1aafSjsg int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
335ad8b1aafSjsg {
336ad8b1aafSjsg struct amdgpu_device *adev = hwmgr->adev;
337ad8b1aafSjsg int temp;
338ad8b1aafSjsg
339ad8b1aafSjsg temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
340ad8b1aafSjsg
341ad8b1aafSjsg temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
342ad8b1aafSjsg CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
343ad8b1aafSjsg
344ad8b1aafSjsg temp = temp & 0x1ff;
345ad8b1aafSjsg
346ad8b1aafSjsg temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
347ad8b1aafSjsg
348ad8b1aafSjsg return temp;
349ad8b1aafSjsg }
350ad8b1aafSjsg
351ad8b1aafSjsg /**
3525ca02815Sjsg * vega10_thermal_set_temperature_range - Set the requested temperature range for high and low alert signals
353ad8b1aafSjsg *
3545ca02815Sjsg * @hwmgr: The address of the hardware manager.
3555ca02815Sjsg * @range: Temperature range to be programmed for
356ad8b1aafSjsg * high and low alert signals
3575ca02815Sjsg * Exception: PP_Result_BadInput if the input data is not valid.
358ad8b1aafSjsg */
vega10_thermal_set_temperature_range(struct pp_hwmgr * hwmgr,struct PP_TemperatureRange * range)359ad8b1aafSjsg static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
360ad8b1aafSjsg struct PP_TemperatureRange *range)
361ad8b1aafSjsg {
362ad8b1aafSjsg struct phm_ppt_v2_information *pp_table_info =
363ad8b1aafSjsg (struct phm_ppt_v2_information *)(hwmgr->pptable);
364ad8b1aafSjsg struct phm_tdp_table *tdp_table = pp_table_info->tdp_table;
365ad8b1aafSjsg struct amdgpu_device *adev = hwmgr->adev;
366ad8b1aafSjsg int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP;
367ad8b1aafSjsg int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP;
368ad8b1aafSjsg uint32_t val;
369ad8b1aafSjsg
370ad8b1aafSjsg /* compare them in unit celsius degree */
371ad8b1aafSjsg if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
372ad8b1aafSjsg low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
373ad8b1aafSjsg
374ad8b1aafSjsg /*
375ad8b1aafSjsg * As a common sense, usSoftwareShutdownTemp should be bigger
376ad8b1aafSjsg * than ThotspotLimit. For any invalid usSoftwareShutdownTemp,
377ad8b1aafSjsg * we will just use the max possible setting VEGA10_THERMAL_MAXIMUM_ALERT_TEMP
378ad8b1aafSjsg * to avoid false alarms.
379ad8b1aafSjsg */
380ad8b1aafSjsg if ((tdp_table->usSoftwareShutdownTemp >
381ad8b1aafSjsg range->hotspot_crit_max / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)) {
382ad8b1aafSjsg if (high > tdp_table->usSoftwareShutdownTemp)
383ad8b1aafSjsg high = tdp_table->usSoftwareShutdownTemp;
384ad8b1aafSjsg }
385ad8b1aafSjsg
386ad8b1aafSjsg if (low > high)
387ad8b1aafSjsg return -EINVAL;
388ad8b1aafSjsg
389ad8b1aafSjsg val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
390ad8b1aafSjsg
391ad8b1aafSjsg val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
392ad8b1aafSjsg val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
393ad8b1aafSjsg val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
394ad8b1aafSjsg val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
395ad8b1aafSjsg val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
396ad8b1aafSjsg (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &
397ad8b1aafSjsg (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
398ad8b1aafSjsg
399ad8b1aafSjsg WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
400ad8b1aafSjsg
401ad8b1aafSjsg return 0;
402ad8b1aafSjsg }
403ad8b1aafSjsg
404ad8b1aafSjsg /**
4055ca02815Sjsg * vega10_thermal_initialize - Programs thermal controller one-time setting registers
406ad8b1aafSjsg *
4075ca02815Sjsg * @hwmgr: The address of the hardware manager.
408ad8b1aafSjsg */
vega10_thermal_initialize(struct pp_hwmgr * hwmgr)409ad8b1aafSjsg static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
410ad8b1aafSjsg {
411ad8b1aafSjsg struct amdgpu_device *adev = hwmgr->adev;
412ad8b1aafSjsg
413ad8b1aafSjsg if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
414ad8b1aafSjsg WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
415ad8b1aafSjsg REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
416ad8b1aafSjsg CG_TACH_CTRL, EDGE_PER_REV,
417ad8b1aafSjsg hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1));
418ad8b1aafSjsg }
419ad8b1aafSjsg
420ad8b1aafSjsg WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
421ad8b1aafSjsg REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
422ad8b1aafSjsg CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28));
423ad8b1aafSjsg
424ad8b1aafSjsg return 0;
425ad8b1aafSjsg }
426ad8b1aafSjsg
427ad8b1aafSjsg /**
4285ca02815Sjsg * vega10_thermal_enable_alert - Enable thermal alerts on the RV770 thermal controller.
429ad8b1aafSjsg *
4305ca02815Sjsg * @hwmgr: The address of the hardware manager.
431ad8b1aafSjsg */
vega10_thermal_enable_alert(struct pp_hwmgr * hwmgr)432ad8b1aafSjsg static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
433ad8b1aafSjsg {
434ad8b1aafSjsg struct amdgpu_device *adev = hwmgr->adev;
435ad8b1aafSjsg struct vega10_hwmgr *data = hwmgr->backend;
436ad8b1aafSjsg uint32_t val = 0;
437ad8b1aafSjsg
438ad8b1aafSjsg if (data->smu_features[GNLD_FW_CTF].supported) {
439ad8b1aafSjsg if (data->smu_features[GNLD_FW_CTF].enabled)
440ad8b1aafSjsg printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
441ad8b1aafSjsg
442ad8b1aafSjsg PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
443ad8b1aafSjsg true,
444ad8b1aafSjsg data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
445ad8b1aafSjsg "Attempt to Enable FW CTF feature Failed!",
446ad8b1aafSjsg return -1);
447ad8b1aafSjsg data->smu_features[GNLD_FW_CTF].enabled = true;
448ad8b1aafSjsg }
449ad8b1aafSjsg
450ad8b1aafSjsg val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
451ad8b1aafSjsg val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
452ad8b1aafSjsg val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
453ad8b1aafSjsg
454ad8b1aafSjsg WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
455ad8b1aafSjsg
456ad8b1aafSjsg return 0;
457ad8b1aafSjsg }
458ad8b1aafSjsg
459ad8b1aafSjsg /**
4605ca02815Sjsg * vega10_thermal_disable_alert - Disable thermal alerts on the RV770 thermal controller.
4615ca02815Sjsg * @hwmgr: The address of the hardware manager.
462ad8b1aafSjsg */
vega10_thermal_disable_alert(struct pp_hwmgr * hwmgr)463ad8b1aafSjsg int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
464ad8b1aafSjsg {
465ad8b1aafSjsg struct amdgpu_device *adev = hwmgr->adev;
466ad8b1aafSjsg struct vega10_hwmgr *data = hwmgr->backend;
467ad8b1aafSjsg
468ad8b1aafSjsg if (data->smu_features[GNLD_FW_CTF].supported) {
469ad8b1aafSjsg if (!data->smu_features[GNLD_FW_CTF].enabled)
470ad8b1aafSjsg printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
471ad8b1aafSjsg
472ad8b1aafSjsg
473ad8b1aafSjsg PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
474ad8b1aafSjsg false,
475ad8b1aafSjsg data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
476ad8b1aafSjsg "Attempt to disable FW CTF feature Failed!",
477ad8b1aafSjsg return -1);
478ad8b1aafSjsg data->smu_features[GNLD_FW_CTF].enabled = false;
479ad8b1aafSjsg }
480ad8b1aafSjsg
481ad8b1aafSjsg WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
482ad8b1aafSjsg
483ad8b1aafSjsg return 0;
484ad8b1aafSjsg }
485ad8b1aafSjsg
486ad8b1aafSjsg /**
4875ca02815Sjsg * vega10_thermal_stop_thermal_controller - Uninitialize the thermal controller.
488ad8b1aafSjsg * Currently just disables alerts.
4895ca02815Sjsg * @hwmgr: The address of the hardware manager.
490ad8b1aafSjsg */
vega10_thermal_stop_thermal_controller(struct pp_hwmgr * hwmgr)491ad8b1aafSjsg int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
492ad8b1aafSjsg {
493ad8b1aafSjsg int result = vega10_thermal_disable_alert(hwmgr);
494ad8b1aafSjsg
495ad8b1aafSjsg if (!hwmgr->thermal_controller.fanInfo.bNoFan)
496ad8b1aafSjsg vega10_fan_ctrl_set_default_mode(hwmgr);
497ad8b1aafSjsg
498ad8b1aafSjsg return result;
499ad8b1aafSjsg }
500ad8b1aafSjsg
501ad8b1aafSjsg /**
5025ca02815Sjsg * vega10_thermal_setup_fan_table - Set up the fan table to control the fan using the SMC.
5035ca02815Sjsg * @hwmgr: the address of the powerplay hardware manager.
5045ca02815Sjsg * Return: result from set temperature range routine
505ad8b1aafSjsg */
vega10_thermal_setup_fan_table(struct pp_hwmgr * hwmgr)506ad8b1aafSjsg static int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
507ad8b1aafSjsg {
508ad8b1aafSjsg int ret;
509ad8b1aafSjsg struct vega10_hwmgr *data = hwmgr->backend;
510ad8b1aafSjsg PPTable_t *table = &(data->smc_state_table.pp_table);
511ad8b1aafSjsg
512ad8b1aafSjsg if (!data->smu_features[GNLD_FAN_CONTROL].supported)
513ad8b1aafSjsg return 0;
514ad8b1aafSjsg
515ad8b1aafSjsg table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller.
516ad8b1aafSjsg advanceFanControlParameters.usMaxFanRPM;
517ad8b1aafSjsg table->FanThrottlingRpm = hwmgr->thermal_controller.
518ad8b1aafSjsg advanceFanControlParameters.usFanRPMMaxLimit;
519ad8b1aafSjsg table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller.
520ad8b1aafSjsg advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
521ad8b1aafSjsg table->FanTargetTemperature = hwmgr->thermal_controller.
522ad8b1aafSjsg advanceFanControlParameters.usTMax;
523ad8b1aafSjsg
524ad8b1aafSjsg smum_send_msg_to_smc_with_parameter(hwmgr,
525ad8b1aafSjsg PPSMC_MSG_SetFanTemperatureTarget,
526ad8b1aafSjsg (uint32_t)table->FanTargetTemperature,
527ad8b1aafSjsg NULL);
528ad8b1aafSjsg
529ad8b1aafSjsg table->FanPwmMin = hwmgr->thermal_controller.
530ad8b1aafSjsg advanceFanControlParameters.usPWMMin * 255 / 100;
531ad8b1aafSjsg table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller.
532ad8b1aafSjsg advanceFanControlParameters.ulTargetGfxClk);
533ad8b1aafSjsg table->FanGainEdge = hwmgr->thermal_controller.
534ad8b1aafSjsg advanceFanControlParameters.usFanGainEdge;
535ad8b1aafSjsg table->FanGainHotspot = hwmgr->thermal_controller.
536ad8b1aafSjsg advanceFanControlParameters.usFanGainHotspot;
537ad8b1aafSjsg table->FanGainLiquid = hwmgr->thermal_controller.
538ad8b1aafSjsg advanceFanControlParameters.usFanGainLiquid;
539ad8b1aafSjsg table->FanGainVrVddc = hwmgr->thermal_controller.
540ad8b1aafSjsg advanceFanControlParameters.usFanGainVrVddc;
541ad8b1aafSjsg table->FanGainVrMvdd = hwmgr->thermal_controller.
542ad8b1aafSjsg advanceFanControlParameters.usFanGainVrMvdd;
543ad8b1aafSjsg table->FanGainPlx = hwmgr->thermal_controller.
544ad8b1aafSjsg advanceFanControlParameters.usFanGainPlx;
545ad8b1aafSjsg table->FanGainHbm = hwmgr->thermal_controller.
546ad8b1aafSjsg advanceFanControlParameters.usFanGainHbm;
547ad8b1aafSjsg table->FanZeroRpmEnable = hwmgr->thermal_controller.
548ad8b1aafSjsg advanceFanControlParameters.ucEnableZeroRPM;
549ad8b1aafSjsg table->FanStopTemp = hwmgr->thermal_controller.
550ad8b1aafSjsg advanceFanControlParameters.usZeroRPMStopTemperature;
551ad8b1aafSjsg table->FanStartTemp = hwmgr->thermal_controller.
552ad8b1aafSjsg advanceFanControlParameters.usZeroRPMStartTemperature;
553ad8b1aafSjsg
554ad8b1aafSjsg ret = smum_smc_table_manager(hwmgr,
555ad8b1aafSjsg (uint8_t *)(&(data->smc_state_table.pp_table)),
556ad8b1aafSjsg PPTABLE, false);
557ad8b1aafSjsg if (ret)
558ad8b1aafSjsg pr_info("Failed to update Fan Control Table in PPTable!");
559ad8b1aafSjsg
560ad8b1aafSjsg return ret;
561ad8b1aafSjsg }
562ad8b1aafSjsg
vega10_enable_mgpu_fan_boost(struct pp_hwmgr * hwmgr)563ad8b1aafSjsg int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
564ad8b1aafSjsg {
565ad8b1aafSjsg struct vega10_hwmgr *data = hwmgr->backend;
566ad8b1aafSjsg PPTable_t *table = &(data->smc_state_table.pp_table);
567ad8b1aafSjsg int ret;
568ad8b1aafSjsg
569ad8b1aafSjsg if (!data->smu_features[GNLD_FAN_CONTROL].supported)
570ad8b1aafSjsg return 0;
571ad8b1aafSjsg
572ad8b1aafSjsg if (!hwmgr->thermal_controller.advanceFanControlParameters.
573ad8b1aafSjsg usMGpuThrottlingRPMLimit)
574ad8b1aafSjsg return 0;
575ad8b1aafSjsg
576ad8b1aafSjsg table->FanThrottlingRpm = hwmgr->thermal_controller.
577ad8b1aafSjsg advanceFanControlParameters.usMGpuThrottlingRPMLimit;
578ad8b1aafSjsg
579ad8b1aafSjsg ret = smum_smc_table_manager(hwmgr,
580ad8b1aafSjsg (uint8_t *)(&(data->smc_state_table.pp_table)),
581ad8b1aafSjsg PPTABLE, false);
582ad8b1aafSjsg if (ret) {
583ad8b1aafSjsg pr_info("Failed to update fan control table in pptable!");
584ad8b1aafSjsg return ret;
585ad8b1aafSjsg }
586ad8b1aafSjsg
587ad8b1aafSjsg ret = vega10_disable_fan_control_feature(hwmgr);
588ad8b1aafSjsg if (ret) {
589ad8b1aafSjsg pr_info("Attempt to disable SMC fan control feature failed!");
590ad8b1aafSjsg return ret;
591ad8b1aafSjsg }
592ad8b1aafSjsg
593ad8b1aafSjsg ret = vega10_enable_fan_control_feature(hwmgr);
594ad8b1aafSjsg if (ret)
595ad8b1aafSjsg pr_info("Attempt to enable SMC fan control feature failed!");
596ad8b1aafSjsg
597ad8b1aafSjsg return ret;
598ad8b1aafSjsg }
599ad8b1aafSjsg
600ad8b1aafSjsg /**
6015ca02815Sjsg * vega10_thermal_start_smc_fan_control - Start the fan control on the SMC.
6025ca02815Sjsg * @hwmgr: the address of the powerplay hardware manager.
6035ca02815Sjsg * Return: result from set temperature range routine
604ad8b1aafSjsg */
vega10_thermal_start_smc_fan_control(struct pp_hwmgr * hwmgr)605ad8b1aafSjsg static int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
606ad8b1aafSjsg {
607ad8b1aafSjsg /* If the fantable setup has failed we could have disabled
608ad8b1aafSjsg * PHM_PlatformCaps_MicrocodeFanControl even after
609ad8b1aafSjsg * this function was included in the table.
610ad8b1aafSjsg * Make sure that we still think controlling the fan is OK.
611ad8b1aafSjsg */
612ad8b1aafSjsg if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
613ad8b1aafSjsg vega10_fan_ctrl_start_smc_fan_control(hwmgr);
614ad8b1aafSjsg
615ad8b1aafSjsg return 0;
616ad8b1aafSjsg }
617ad8b1aafSjsg
618ad8b1aafSjsg
vega10_start_thermal_controller(struct pp_hwmgr * hwmgr,struct PP_TemperatureRange * range)619ad8b1aafSjsg int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
620ad8b1aafSjsg struct PP_TemperatureRange *range)
621ad8b1aafSjsg {
622ad8b1aafSjsg int ret = 0;
623ad8b1aafSjsg
624ad8b1aafSjsg if (range == NULL)
625ad8b1aafSjsg return -EINVAL;
626ad8b1aafSjsg
627ad8b1aafSjsg vega10_thermal_initialize(hwmgr);
628ad8b1aafSjsg ret = vega10_thermal_set_temperature_range(hwmgr, range);
629ad8b1aafSjsg if (ret)
630ad8b1aafSjsg return -EINVAL;
631ad8b1aafSjsg
632ad8b1aafSjsg vega10_thermal_enable_alert(hwmgr);
633ad8b1aafSjsg /* We should restrict performance levels to low before we halt the SMC.
634ad8b1aafSjsg * On the other hand we are still in boot state when we do this
635ad8b1aafSjsg * so it would be pointless.
636ad8b1aafSjsg * If this assumption changes we have to revisit this table.
637ad8b1aafSjsg */
638ad8b1aafSjsg ret = vega10_thermal_setup_fan_table(hwmgr);
639ad8b1aafSjsg if (ret)
640ad8b1aafSjsg return -EINVAL;
641ad8b1aafSjsg
642ad8b1aafSjsg vega10_thermal_start_smc_fan_control(hwmgr);
643ad8b1aafSjsg
644ad8b1aafSjsg return 0;
645ad8b1aafSjsg };
646ad8b1aafSjsg
647ad8b1aafSjsg
648ad8b1aafSjsg
649ad8b1aafSjsg
vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr * hwmgr)650ad8b1aafSjsg int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
651ad8b1aafSjsg {
652ad8b1aafSjsg if (!hwmgr->thermal_controller.fanInfo.bNoFan) {
653ad8b1aafSjsg vega10_fan_ctrl_set_default_mode(hwmgr);
654ad8b1aafSjsg vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
655ad8b1aafSjsg }
656ad8b1aafSjsg return 0;
657ad8b1aafSjsg }
658