1*1bb76ff1Sjsg /* 2*1bb76ff1Sjsg * Copyright 2014 Advanced Micro Devices, Inc. 3*1bb76ff1Sjsg * 4*1bb76ff1Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*1bb76ff1Sjsg * copy of this software and associated documentation files (the "Software"), 6*1bb76ff1Sjsg * to deal in the Software without restriction, including without limitation 7*1bb76ff1Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*1bb76ff1Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9*1bb76ff1Sjsg * Software is furnished to do so, subject to the following conditions: 10*1bb76ff1Sjsg * 11*1bb76ff1Sjsg * The above copyright notice and this permission notice shall be included in 12*1bb76ff1Sjsg * all copies or substantial portions of the Software. 13*1bb76ff1Sjsg * 14*1bb76ff1Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*1bb76ff1Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*1bb76ff1Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*1bb76ff1Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*1bb76ff1Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*1bb76ff1Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*1bb76ff1Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21*1bb76ff1Sjsg * 22*1bb76ff1Sjsg */ 23*1bb76ff1Sjsg 24*1bb76ff1Sjsg #ifndef SMU74_DISCRETE_H 25*1bb76ff1Sjsg #define SMU74_DISCRETE_H 26*1bb76ff1Sjsg 27*1bb76ff1Sjsg #include "smu74.h" 28*1bb76ff1Sjsg 29*1bb76ff1Sjsg #pragma pack(push, 1) 30*1bb76ff1Sjsg 31*1bb76ff1Sjsg 32*1bb76ff1Sjsg #define NUM_SCLK_RANGE 8 33*1bb76ff1Sjsg 34*1bb76ff1Sjsg #define VCO_3_6 1 35*1bb76ff1Sjsg #define VCO_2_4 3 36*1bb76ff1Sjsg 37*1bb76ff1Sjsg #define POSTDIV_DIV_BY_1 0 38*1bb76ff1Sjsg #define POSTDIV_DIV_BY_2 1 39*1bb76ff1Sjsg #define POSTDIV_DIV_BY_4 2 40*1bb76ff1Sjsg #define POSTDIV_DIV_BY_8 3 41*1bb76ff1Sjsg #define POSTDIV_DIV_BY_16 4 42*1bb76ff1Sjsg 43*1bb76ff1Sjsg struct sclkFcwRange_t { 44*1bb76ff1Sjsg uint8_t vco_setting; 45*1bb76ff1Sjsg uint8_t postdiv; 46*1bb76ff1Sjsg uint16_t fcw_pcc; 47*1bb76ff1Sjsg 48*1bb76ff1Sjsg uint16_t fcw_trans_upper; 49*1bb76ff1Sjsg uint16_t fcw_trans_lower; 50*1bb76ff1Sjsg }; 51*1bb76ff1Sjsg typedef struct sclkFcwRange_t sclkFcwRange_t; 52*1bb76ff1Sjsg 53*1bb76ff1Sjsg struct SMIO_Pattern { 54*1bb76ff1Sjsg uint16_t Voltage; 55*1bb76ff1Sjsg uint8_t Smio; 56*1bb76ff1Sjsg uint8_t padding; 57*1bb76ff1Sjsg }; 58*1bb76ff1Sjsg 59*1bb76ff1Sjsg typedef struct SMIO_Pattern SMIO_Pattern; 60*1bb76ff1Sjsg 61*1bb76ff1Sjsg struct SMIO_Table { 62*1bb76ff1Sjsg SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS]; 63*1bb76ff1Sjsg }; 64*1bb76ff1Sjsg 65*1bb76ff1Sjsg typedef struct SMIO_Table SMIO_Table; 66*1bb76ff1Sjsg 67*1bb76ff1Sjsg struct SMU_SclkSetting { 68*1bb76ff1Sjsg uint32_t SclkFrequency; 69*1bb76ff1Sjsg uint16_t Fcw_int; 70*1bb76ff1Sjsg uint16_t Fcw_frac; 71*1bb76ff1Sjsg uint16_t Pcc_fcw_int; 72*1bb76ff1Sjsg uint8_t PllRange; 73*1bb76ff1Sjsg uint8_t SSc_En; 74*1bb76ff1Sjsg uint16_t Sclk_slew_rate; 75*1bb76ff1Sjsg uint16_t Pcc_up_slew_rate; 76*1bb76ff1Sjsg uint16_t Pcc_down_slew_rate; 77*1bb76ff1Sjsg uint16_t Fcw1_int; 78*1bb76ff1Sjsg uint16_t Fcw1_frac; 79*1bb76ff1Sjsg uint16_t Sclk_ss_slew_rate; 80*1bb76ff1Sjsg }; 81*1bb76ff1Sjsg typedef struct SMU_SclkSetting SMU_SclkSetting; 82*1bb76ff1Sjsg 83*1bb76ff1Sjsg struct SMU74_Discrete_GraphicsLevel { 84*1bb76ff1Sjsg SMU_VoltageLevel MinVoltage; 85*1bb76ff1Sjsg uint8_t pcieDpmLevel; 86*1bb76ff1Sjsg uint8_t DeepSleepDivId; 87*1bb76ff1Sjsg uint16_t ActivityLevel; 88*1bb76ff1Sjsg uint32_t CgSpllFuncCntl3; 89*1bb76ff1Sjsg uint32_t CgSpllFuncCntl4; 90*1bb76ff1Sjsg uint32_t CcPwrDynRm; 91*1bb76ff1Sjsg uint32_t CcPwrDynRm1; 92*1bb76ff1Sjsg uint8_t SclkDid; 93*1bb76ff1Sjsg uint8_t padding; 94*1bb76ff1Sjsg uint8_t EnabledForActivity; 95*1bb76ff1Sjsg uint8_t EnabledForThrottle; 96*1bb76ff1Sjsg uint8_t UpHyst; 97*1bb76ff1Sjsg uint8_t DownHyst; 98*1bb76ff1Sjsg uint8_t VoltageDownHyst; 99*1bb76ff1Sjsg uint8_t PowerThrottle; 100*1bb76ff1Sjsg SMU_SclkSetting SclkSetting; 101*1bb76ff1Sjsg }; 102*1bb76ff1Sjsg 103*1bb76ff1Sjsg typedef struct SMU74_Discrete_GraphicsLevel SMU74_Discrete_GraphicsLevel; 104*1bb76ff1Sjsg 105*1bb76ff1Sjsg struct SMU74_Discrete_ACPILevel { 106*1bb76ff1Sjsg uint32_t Flags; 107*1bb76ff1Sjsg SMU_VoltageLevel MinVoltage; 108*1bb76ff1Sjsg uint32_t SclkFrequency; 109*1bb76ff1Sjsg uint8_t SclkDid; 110*1bb76ff1Sjsg uint8_t DisplayWatermark; 111*1bb76ff1Sjsg uint8_t DeepSleepDivId; 112*1bb76ff1Sjsg uint8_t padding; 113*1bb76ff1Sjsg uint32_t CcPwrDynRm; 114*1bb76ff1Sjsg uint32_t CcPwrDynRm1; 115*1bb76ff1Sjsg 116*1bb76ff1Sjsg SMU_SclkSetting SclkSetting; 117*1bb76ff1Sjsg }; 118*1bb76ff1Sjsg 119*1bb76ff1Sjsg typedef struct SMU74_Discrete_ACPILevel SMU74_Discrete_ACPILevel; 120*1bb76ff1Sjsg 121*1bb76ff1Sjsg struct SMU74_Discrete_Ulv { 122*1bb76ff1Sjsg uint32_t CcPwrDynRm; 123*1bb76ff1Sjsg uint32_t CcPwrDynRm1; 124*1bb76ff1Sjsg uint16_t VddcOffset; 125*1bb76ff1Sjsg uint8_t VddcOffsetVid; 126*1bb76ff1Sjsg uint8_t VddcPhase; 127*1bb76ff1Sjsg uint16_t BifSclkDfs; 128*1bb76ff1Sjsg uint16_t Reserved; 129*1bb76ff1Sjsg }; 130*1bb76ff1Sjsg 131*1bb76ff1Sjsg typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv; 132*1bb76ff1Sjsg 133*1bb76ff1Sjsg struct SMU74_Discrete_MemoryLevel { 134*1bb76ff1Sjsg SMU_VoltageLevel MinVoltage; 135*1bb76ff1Sjsg uint32_t MinMvdd; 136*1bb76ff1Sjsg 137*1bb76ff1Sjsg uint32_t MclkFrequency; 138*1bb76ff1Sjsg 139*1bb76ff1Sjsg uint8_t StutterEnable; 140*1bb76ff1Sjsg uint8_t EnabledForThrottle; 141*1bb76ff1Sjsg uint8_t EnabledForActivity; 142*1bb76ff1Sjsg uint8_t padding_0; 143*1bb76ff1Sjsg 144*1bb76ff1Sjsg uint8_t UpHyst; 145*1bb76ff1Sjsg uint8_t DownHyst; 146*1bb76ff1Sjsg uint8_t VoltageDownHyst; 147*1bb76ff1Sjsg uint8_t padding_1; 148*1bb76ff1Sjsg 149*1bb76ff1Sjsg uint16_t ActivityLevel; 150*1bb76ff1Sjsg uint8_t DisplayWatermark; 151*1bb76ff1Sjsg uint8_t Reserved; 152*1bb76ff1Sjsg }; 153*1bb76ff1Sjsg 154*1bb76ff1Sjsg typedef struct SMU74_Discrete_MemoryLevel SMU74_Discrete_MemoryLevel; 155*1bb76ff1Sjsg 156*1bb76ff1Sjsg struct SMU74_Discrete_LinkLevel { 157*1bb76ff1Sjsg uint8_t PcieGenSpeed; 158*1bb76ff1Sjsg uint8_t PcieLaneCount; 159*1bb76ff1Sjsg uint8_t EnabledForActivity; 160*1bb76ff1Sjsg uint8_t SPC; 161*1bb76ff1Sjsg uint32_t DownThreshold; 162*1bb76ff1Sjsg uint32_t UpThreshold; 163*1bb76ff1Sjsg uint16_t BifSclkDfs; 164*1bb76ff1Sjsg uint16_t Reserved; 165*1bb76ff1Sjsg }; 166*1bb76ff1Sjsg 167*1bb76ff1Sjsg typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel; 168*1bb76ff1Sjsg 169*1bb76ff1Sjsg struct SMU74_Discrete_MCArbDramTimingTableEntry { 170*1bb76ff1Sjsg uint32_t McArbDramTiming; 171*1bb76ff1Sjsg uint32_t McArbDramTiming2; 172*1bb76ff1Sjsg uint8_t McArbBurstTime; 173*1bb76ff1Sjsg uint8_t padding[3]; 174*1bb76ff1Sjsg }; 175*1bb76ff1Sjsg 176*1bb76ff1Sjsg typedef struct SMU74_Discrete_MCArbDramTimingTableEntry SMU74_Discrete_MCArbDramTimingTableEntry; 177*1bb76ff1Sjsg 178*1bb76ff1Sjsg struct SMU74_Discrete_MCArbDramTimingTable { 179*1bb76ff1Sjsg SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 180*1bb76ff1Sjsg }; 181*1bb76ff1Sjsg 182*1bb76ff1Sjsg typedef struct SMU74_Discrete_MCArbDramTimingTable SMU74_Discrete_MCArbDramTimingTable; 183*1bb76ff1Sjsg 184*1bb76ff1Sjsg struct SMU74_Discrete_UvdLevel { 185*1bb76ff1Sjsg uint32_t VclkFrequency; 186*1bb76ff1Sjsg uint32_t DclkFrequency; 187*1bb76ff1Sjsg SMU_VoltageLevel MinVoltage; 188*1bb76ff1Sjsg uint8_t VclkDivider; 189*1bb76ff1Sjsg uint8_t DclkDivider; 190*1bb76ff1Sjsg uint8_t padding[2]; 191*1bb76ff1Sjsg }; 192*1bb76ff1Sjsg 193*1bb76ff1Sjsg typedef struct SMU74_Discrete_UvdLevel SMU74_Discrete_UvdLevel; 194*1bb76ff1Sjsg 195*1bb76ff1Sjsg struct SMU74_Discrete_ExtClkLevel { 196*1bb76ff1Sjsg uint32_t Frequency; 197*1bb76ff1Sjsg SMU_VoltageLevel MinVoltage; 198*1bb76ff1Sjsg uint8_t Divider; 199*1bb76ff1Sjsg uint8_t padding[3]; 200*1bb76ff1Sjsg }; 201*1bb76ff1Sjsg 202*1bb76ff1Sjsg typedef struct SMU74_Discrete_ExtClkLevel SMU74_Discrete_ExtClkLevel; 203*1bb76ff1Sjsg 204*1bb76ff1Sjsg struct SMU74_Discrete_StateInfo { 205*1bb76ff1Sjsg uint32_t SclkFrequency; 206*1bb76ff1Sjsg uint32_t MclkFrequency; 207*1bb76ff1Sjsg uint32_t VclkFrequency; 208*1bb76ff1Sjsg uint32_t DclkFrequency; 209*1bb76ff1Sjsg uint32_t SamclkFrequency; 210*1bb76ff1Sjsg uint32_t AclkFrequency; 211*1bb76ff1Sjsg uint32_t EclkFrequency; 212*1bb76ff1Sjsg uint16_t MvddVoltage; 213*1bb76ff1Sjsg uint16_t padding16; 214*1bb76ff1Sjsg uint8_t DisplayWatermark; 215*1bb76ff1Sjsg uint8_t McArbIndex; 216*1bb76ff1Sjsg uint8_t McRegIndex; 217*1bb76ff1Sjsg uint8_t SeqIndex; 218*1bb76ff1Sjsg uint8_t SclkDid; 219*1bb76ff1Sjsg int8_t SclkIndex; 220*1bb76ff1Sjsg int8_t MclkIndex; 221*1bb76ff1Sjsg uint8_t PCIeGen; 222*1bb76ff1Sjsg }; 223*1bb76ff1Sjsg 224*1bb76ff1Sjsg typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo; 225*1bb76ff1Sjsg 226*1bb76ff1Sjsg struct SMU_QuadraticCoeffs { 227*1bb76ff1Sjsg int32_t m1; 228*1bb76ff1Sjsg uint32_t b; 229*1bb76ff1Sjsg 230*1bb76ff1Sjsg int16_t m2; 231*1bb76ff1Sjsg uint8_t m1_shift; 232*1bb76ff1Sjsg uint8_t m2_shift; 233*1bb76ff1Sjsg }; 234*1bb76ff1Sjsg typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs; 235*1bb76ff1Sjsg 236*1bb76ff1Sjsg struct SMU74_Discrete_DpmTable { 237*1bb76ff1Sjsg 238*1bb76ff1Sjsg SMU74_PIDController GraphicsPIDController; 239*1bb76ff1Sjsg SMU74_PIDController MemoryPIDController; 240*1bb76ff1Sjsg SMU74_PIDController LinkPIDController; 241*1bb76ff1Sjsg 242*1bb76ff1Sjsg uint32_t SystemFlags; 243*1bb76ff1Sjsg 244*1bb76ff1Sjsg uint32_t VRConfig; 245*1bb76ff1Sjsg uint32_t SmioMask1; 246*1bb76ff1Sjsg uint32_t SmioMask2; 247*1bb76ff1Sjsg SMIO_Table SmioTable1; 248*1bb76ff1Sjsg SMIO_Table SmioTable2; 249*1bb76ff1Sjsg 250*1bb76ff1Sjsg uint32_t MvddLevelCount; 251*1bb76ff1Sjsg 252*1bb76ff1Sjsg 253*1bb76ff1Sjsg uint8_t BapmVddcVidHiSidd[SMU74_MAX_LEVELS_VDDC]; 254*1bb76ff1Sjsg uint8_t BapmVddcVidLoSidd[SMU74_MAX_LEVELS_VDDC]; 255*1bb76ff1Sjsg uint8_t BapmVddcVidHiSidd2[SMU74_MAX_LEVELS_VDDC]; 256*1bb76ff1Sjsg 257*1bb76ff1Sjsg uint8_t GraphicsDpmLevelCount; 258*1bb76ff1Sjsg uint8_t MemoryDpmLevelCount; 259*1bb76ff1Sjsg uint8_t LinkLevelCount; 260*1bb76ff1Sjsg uint8_t MasterDeepSleepControl; 261*1bb76ff1Sjsg 262*1bb76ff1Sjsg uint8_t UvdLevelCount; 263*1bb76ff1Sjsg uint8_t VceLevelCount; 264*1bb76ff1Sjsg uint8_t AcpLevelCount; 265*1bb76ff1Sjsg uint8_t SamuLevelCount; 266*1bb76ff1Sjsg 267*1bb76ff1Sjsg uint8_t ThermOutGpio; 268*1bb76ff1Sjsg uint8_t ThermOutPolarity; 269*1bb76ff1Sjsg uint8_t ThermOutMode; 270*1bb76ff1Sjsg uint8_t BootPhases; 271*1bb76ff1Sjsg 272*1bb76ff1Sjsg uint8_t VRHotLevel; 273*1bb76ff1Sjsg uint8_t LdoRefSel; 274*1bb76ff1Sjsg uint8_t SharedRails; 275*1bb76ff1Sjsg uint8_t Reserved1; 276*1bb76ff1Sjsg uint16_t FanStartTemperature; 277*1bb76ff1Sjsg uint16_t FanStopTemperature; 278*1bb76ff1Sjsg uint16_t MaxVoltage; 279*1bb76ff1Sjsg uint16_t Reserved2; 280*1bb76ff1Sjsg uint32_t Reserved[1]; 281*1bb76ff1Sjsg 282*1bb76ff1Sjsg SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS]; 283*1bb76ff1Sjsg SMU74_Discrete_MemoryLevel MemoryACPILevel; 284*1bb76ff1Sjsg SMU74_Discrete_MemoryLevel MemoryLevel[SMU74_MAX_LEVELS_MEMORY]; 285*1bb76ff1Sjsg SMU74_Discrete_LinkLevel LinkLevel[SMU74_MAX_LEVELS_LINK]; 286*1bb76ff1Sjsg SMU74_Discrete_ACPILevel ACPILevel; 287*1bb76ff1Sjsg SMU74_Discrete_UvdLevel UvdLevel[SMU74_MAX_LEVELS_UVD]; 288*1bb76ff1Sjsg SMU74_Discrete_ExtClkLevel VceLevel[SMU74_MAX_LEVELS_VCE]; 289*1bb76ff1Sjsg SMU74_Discrete_ExtClkLevel AcpLevel[SMU74_MAX_LEVELS_ACP]; 290*1bb76ff1Sjsg SMU74_Discrete_ExtClkLevel SamuLevel[SMU74_MAX_LEVELS_SAMU]; 291*1bb76ff1Sjsg SMU74_Discrete_Ulv Ulv; 292*1bb76ff1Sjsg 293*1bb76ff1Sjsg uint8_t DisplayWatermark[SMU74_MAX_LEVELS_MEMORY][SMU74_MAX_LEVELS_GRAPHICS]; 294*1bb76ff1Sjsg 295*1bb76ff1Sjsg uint32_t SclkStepSize; 296*1bb76ff1Sjsg uint32_t Smio[SMU74_MAX_ENTRIES_SMIO]; 297*1bb76ff1Sjsg 298*1bb76ff1Sjsg uint8_t UvdBootLevel; 299*1bb76ff1Sjsg uint8_t VceBootLevel; 300*1bb76ff1Sjsg uint8_t AcpBootLevel; 301*1bb76ff1Sjsg uint8_t SamuBootLevel; 302*1bb76ff1Sjsg 303*1bb76ff1Sjsg uint8_t GraphicsBootLevel; 304*1bb76ff1Sjsg uint8_t GraphicsVoltageChangeEnable; 305*1bb76ff1Sjsg uint8_t GraphicsThermThrottleEnable; 306*1bb76ff1Sjsg uint8_t GraphicsInterval; 307*1bb76ff1Sjsg 308*1bb76ff1Sjsg uint8_t VoltageInterval; 309*1bb76ff1Sjsg uint8_t ThermalInterval; 310*1bb76ff1Sjsg uint16_t TemperatureLimitHigh; 311*1bb76ff1Sjsg 312*1bb76ff1Sjsg uint16_t TemperatureLimitLow; 313*1bb76ff1Sjsg uint8_t MemoryBootLevel; 314*1bb76ff1Sjsg uint8_t MemoryVoltageChangeEnable; 315*1bb76ff1Sjsg 316*1bb76ff1Sjsg uint16_t BootMVdd; 317*1bb76ff1Sjsg uint8_t MemoryInterval; 318*1bb76ff1Sjsg uint8_t MemoryThermThrottleEnable; 319*1bb76ff1Sjsg 320*1bb76ff1Sjsg uint16_t VoltageResponseTime; 321*1bb76ff1Sjsg uint16_t PhaseResponseTime; 322*1bb76ff1Sjsg 323*1bb76ff1Sjsg uint8_t PCIeBootLinkLevel; 324*1bb76ff1Sjsg uint8_t PCIeGenInterval; 325*1bb76ff1Sjsg uint8_t DTEInterval; 326*1bb76ff1Sjsg uint8_t DTEMode; 327*1bb76ff1Sjsg 328*1bb76ff1Sjsg uint8_t SVI2Enable; 329*1bb76ff1Sjsg uint8_t VRHotGpio; 330*1bb76ff1Sjsg uint8_t AcDcGpio; 331*1bb76ff1Sjsg uint8_t ThermGpio; 332*1bb76ff1Sjsg 333*1bb76ff1Sjsg uint16_t PPM_PkgPwrLimit; 334*1bb76ff1Sjsg uint16_t PPM_TemperatureLimit; 335*1bb76ff1Sjsg 336*1bb76ff1Sjsg uint16_t DefaultTdp; 337*1bb76ff1Sjsg uint16_t TargetTdp; 338*1bb76ff1Sjsg 339*1bb76ff1Sjsg uint16_t FpsHighThreshold; 340*1bb76ff1Sjsg uint16_t FpsLowThreshold; 341*1bb76ff1Sjsg 342*1bb76ff1Sjsg uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS]; 343*1bb76ff1Sjsg uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS]; 344*1bb76ff1Sjsg 345*1bb76ff1Sjsg uint16_t TemperatureLimitEdge; 346*1bb76ff1Sjsg uint16_t TemperatureLimitHotspot; 347*1bb76ff1Sjsg 348*1bb76ff1Sjsg uint16_t BootVddc; 349*1bb76ff1Sjsg uint16_t BootVddci; 350*1bb76ff1Sjsg 351*1bb76ff1Sjsg uint16_t FanGainEdge; 352*1bb76ff1Sjsg uint16_t FanGainHotspot; 353*1bb76ff1Sjsg 354*1bb76ff1Sjsg uint32_t LowSclkInterruptThreshold; 355*1bb76ff1Sjsg uint32_t VddGfxReChkWait; 356*1bb76ff1Sjsg 357*1bb76ff1Sjsg uint8_t ClockStretcherAmount; 358*1bb76ff1Sjsg uint8_t Sclk_CKS_masterEn0_7; 359*1bb76ff1Sjsg uint8_t Sclk_CKS_masterEn8_15; 360*1bb76ff1Sjsg uint8_t DPMFreezeAndForced; 361*1bb76ff1Sjsg 362*1bb76ff1Sjsg uint8_t Sclk_voltageOffset[8]; 363*1bb76ff1Sjsg 364*1bb76ff1Sjsg SMU_ClockStretcherDataTable ClockStretcherDataTable; 365*1bb76ff1Sjsg SMU_CKS_LOOKUPTable CKS_LOOKUPTable; 366*1bb76ff1Sjsg 367*1bb76ff1Sjsg uint32_t CurrSclkPllRange; 368*1bb76ff1Sjsg sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE]; 369*1bb76ff1Sjsg GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES]; 370*1bb76ff1Sjsg SMU_QuadraticCoeffs AVFSGB_VDROOP_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES]; 371*1bb76ff1Sjsg }; 372*1bb76ff1Sjsg 373*1bb76ff1Sjsg typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable; 374*1bb76ff1Sjsg 375*1bb76ff1Sjsg 376*1bb76ff1Sjsg struct SMU74_Discrete_FanTable { 377*1bb76ff1Sjsg uint16_t FdoMode; 378*1bb76ff1Sjsg int16_t TempMin; 379*1bb76ff1Sjsg int16_t TempMed; 380*1bb76ff1Sjsg int16_t TempMax; 381*1bb76ff1Sjsg int16_t Slope1; 382*1bb76ff1Sjsg int16_t Slope2; 383*1bb76ff1Sjsg int16_t FdoMin; 384*1bb76ff1Sjsg int16_t HystUp; 385*1bb76ff1Sjsg int16_t HystDown; 386*1bb76ff1Sjsg int16_t HystSlope; 387*1bb76ff1Sjsg int16_t TempRespLim; 388*1bb76ff1Sjsg int16_t TempCurr; 389*1bb76ff1Sjsg int16_t SlopeCurr; 390*1bb76ff1Sjsg int16_t PwmCurr; 391*1bb76ff1Sjsg uint32_t RefreshPeriod; 392*1bb76ff1Sjsg int16_t FdoMax; 393*1bb76ff1Sjsg uint8_t TempSrc; 394*1bb76ff1Sjsg int8_t Padding; 395*1bb76ff1Sjsg }; 396*1bb76ff1Sjsg 397*1bb76ff1Sjsg typedef struct SMU74_Discrete_FanTable SMU74_Discrete_FanTable; 398*1bb76ff1Sjsg 399*1bb76ff1Sjsg #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4 400*1bb76ff1Sjsg #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG) 401*1bb76ff1Sjsg 402*1bb76ff1Sjsg 403*1bb76ff1Sjsg struct SMU7_MclkDpmScoreboard { 404*1bb76ff1Sjsg uint32_t PercentageBusy; 405*1bb76ff1Sjsg 406*1bb76ff1Sjsg int32_t PIDError; 407*1bb76ff1Sjsg int32_t PIDIntegral; 408*1bb76ff1Sjsg int32_t PIDOutput; 409*1bb76ff1Sjsg 410*1bb76ff1Sjsg uint32_t SigmaDeltaAccum; 411*1bb76ff1Sjsg uint32_t SigmaDeltaOutput; 412*1bb76ff1Sjsg uint32_t SigmaDeltaLevel; 413*1bb76ff1Sjsg 414*1bb76ff1Sjsg uint32_t UtilizationSetpoint; 415*1bb76ff1Sjsg 416*1bb76ff1Sjsg uint8_t TdpClampMode; 417*1bb76ff1Sjsg uint8_t TdcClampMode; 418*1bb76ff1Sjsg uint8_t ThermClampMode; 419*1bb76ff1Sjsg uint8_t VoltageBusy; 420*1bb76ff1Sjsg 421*1bb76ff1Sjsg int8_t CurrLevel; 422*1bb76ff1Sjsg int8_t TargLevel; 423*1bb76ff1Sjsg uint8_t LevelChangeInProgress; 424*1bb76ff1Sjsg uint8_t UpHyst; 425*1bb76ff1Sjsg 426*1bb76ff1Sjsg uint8_t DownHyst; 427*1bb76ff1Sjsg uint8_t VoltageDownHyst; 428*1bb76ff1Sjsg uint8_t DpmEnable; 429*1bb76ff1Sjsg uint8_t DpmRunning; 430*1bb76ff1Sjsg 431*1bb76ff1Sjsg uint8_t DpmForce; 432*1bb76ff1Sjsg uint8_t DpmForceLevel; 433*1bb76ff1Sjsg uint8_t padding2; 434*1bb76ff1Sjsg uint8_t McArbIndex; 435*1bb76ff1Sjsg 436*1bb76ff1Sjsg uint32_t MinimumPerfMclk; 437*1bb76ff1Sjsg 438*1bb76ff1Sjsg uint8_t AcpiReq; 439*1bb76ff1Sjsg uint8_t AcpiAck; 440*1bb76ff1Sjsg uint8_t MclkSwitchInProgress; 441*1bb76ff1Sjsg uint8_t MclkSwitchCritical; 442*1bb76ff1Sjsg 443*1bb76ff1Sjsg uint8_t IgnoreVBlank; 444*1bb76ff1Sjsg uint8_t TargetMclkIndex; 445*1bb76ff1Sjsg uint16_t VbiFailureCount; 446*1bb76ff1Sjsg uint8_t VbiWaitCounter; 447*1bb76ff1Sjsg uint8_t EnabledLevelsChange; 448*1bb76ff1Sjsg 449*1bb76ff1Sjsg uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_MEMORY]; 450*1bb76ff1Sjsg uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_MEMORY]; 451*1bb76ff1Sjsg 452*1bb76ff1Sjsg void (*TargetStateCalculator)(uint8_t); 453*1bb76ff1Sjsg void (*SavedTargetStateCalculator)(uint8_t); 454*1bb76ff1Sjsg 455*1bb76ff1Sjsg uint16_t AutoDpmInterval; 456*1bb76ff1Sjsg uint16_t AutoDpmRange; 457*1bb76ff1Sjsg 458*1bb76ff1Sjsg uint16_t VbiTimeoutCount; 459*1bb76ff1Sjsg uint16_t MclkSwitchingTime; 460*1bb76ff1Sjsg 461*1bb76ff1Sjsg uint8_t fastSwitch; 462*1bb76ff1Sjsg uint8_t Save_PIC_VDDGFX_EXIT; 463*1bb76ff1Sjsg uint8_t Save_PIC_VDDGFX_ENTER; 464*1bb76ff1Sjsg uint8_t padding; 465*1bb76ff1Sjsg }; 466*1bb76ff1Sjsg 467*1bb76ff1Sjsg typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard; 468*1bb76ff1Sjsg 469*1bb76ff1Sjsg struct SMU7_UlvScoreboard { 470*1bb76ff1Sjsg uint8_t EnterUlv; 471*1bb76ff1Sjsg uint8_t ExitUlv; 472*1bb76ff1Sjsg uint8_t UlvActive; 473*1bb76ff1Sjsg uint8_t WaitingForUlv; 474*1bb76ff1Sjsg uint8_t UlvEnable; 475*1bb76ff1Sjsg uint8_t UlvRunning; 476*1bb76ff1Sjsg uint8_t UlvMasterEnable; 477*1bb76ff1Sjsg uint8_t padding; 478*1bb76ff1Sjsg uint32_t UlvAbortedCount; 479*1bb76ff1Sjsg uint32_t UlvTimeStamp; 480*1bb76ff1Sjsg }; 481*1bb76ff1Sjsg 482*1bb76ff1Sjsg typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard; 483*1bb76ff1Sjsg 484*1bb76ff1Sjsg struct VddgfxSavedRegisters { 485*1bb76ff1Sjsg uint32_t GPU_DBG[3]; 486*1bb76ff1Sjsg uint32_t MEC_BaseAddress_Hi; 487*1bb76ff1Sjsg uint32_t MEC_BaseAddress_Lo; 488*1bb76ff1Sjsg uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; 489*1bb76ff1Sjsg uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; 490*1bb76ff1Sjsg uint32_t CP_INT_CNTL; 491*1bb76ff1Sjsg }; 492*1bb76ff1Sjsg 493*1bb76ff1Sjsg typedef struct VddgfxSavedRegisters VddgfxSavedRegisters; 494*1bb76ff1Sjsg 495*1bb76ff1Sjsg struct SMU7_VddGfxScoreboard { 496*1bb76ff1Sjsg uint8_t VddGfxEnable; 497*1bb76ff1Sjsg uint8_t VddGfxActive; 498*1bb76ff1Sjsg uint8_t VPUResetOccured; 499*1bb76ff1Sjsg uint8_t padding; 500*1bb76ff1Sjsg 501*1bb76ff1Sjsg uint32_t VddGfxEnteredCount; 502*1bb76ff1Sjsg uint32_t VddGfxAbortedCount; 503*1bb76ff1Sjsg 504*1bb76ff1Sjsg uint32_t VddGfxVid; 505*1bb76ff1Sjsg 506*1bb76ff1Sjsg VddgfxSavedRegisters SavedRegisters; 507*1bb76ff1Sjsg }; 508*1bb76ff1Sjsg 509*1bb76ff1Sjsg typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard; 510*1bb76ff1Sjsg 511*1bb76ff1Sjsg struct SMU7_TdcLimitScoreboard { 512*1bb76ff1Sjsg uint8_t Enable; 513*1bb76ff1Sjsg uint8_t Running; 514*1bb76ff1Sjsg uint16_t Alpha; 515*1bb76ff1Sjsg uint32_t FilteredIddc; 516*1bb76ff1Sjsg uint32_t IddcLimit; 517*1bb76ff1Sjsg uint32_t IddcHyst; 518*1bb76ff1Sjsg SMU7_HystController_Data HystControllerData; 519*1bb76ff1Sjsg }; 520*1bb76ff1Sjsg 521*1bb76ff1Sjsg typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard; 522*1bb76ff1Sjsg 523*1bb76ff1Sjsg struct SMU7_PkgPwrLimitScoreboard { 524*1bb76ff1Sjsg uint8_t Enable; 525*1bb76ff1Sjsg uint8_t Running; 526*1bb76ff1Sjsg uint16_t Alpha; 527*1bb76ff1Sjsg uint32_t FilteredPkgPwr; 528*1bb76ff1Sjsg uint32_t Limit; 529*1bb76ff1Sjsg uint32_t Hyst; 530*1bb76ff1Sjsg uint32_t LimitFromDriver; 531*1bb76ff1Sjsg SMU7_HystController_Data HystControllerData; 532*1bb76ff1Sjsg }; 533*1bb76ff1Sjsg 534*1bb76ff1Sjsg typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard; 535*1bb76ff1Sjsg 536*1bb76ff1Sjsg struct SMU7_BapmScoreboard { 537*1bb76ff1Sjsg uint32_t source_powers[SMU74_DTE_SOURCES]; 538*1bb76ff1Sjsg uint32_t source_powers_last[SMU74_DTE_SOURCES]; 539*1bb76ff1Sjsg int32_t entity_temperatures[SMU74_NUM_GPU_TES]; 540*1bb76ff1Sjsg int32_t initial_entity_temperatures[SMU74_NUM_GPU_TES]; 541*1bb76ff1Sjsg int32_t Limit; 542*1bb76ff1Sjsg int32_t Hyst; 543*1bb76ff1Sjsg int32_t therm_influence_coeff_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS * 2]; 544*1bb76ff1Sjsg int32_t therm_node_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS]; 545*1bb76ff1Sjsg uint16_t ConfigTDPPowerScalar; 546*1bb76ff1Sjsg uint16_t FanSpeedPowerScalar; 547*1bb76ff1Sjsg uint16_t OverDrivePowerScalar; 548*1bb76ff1Sjsg uint16_t OverDriveLimitScalar; 549*1bb76ff1Sjsg uint16_t FinalPowerScalar; 550*1bb76ff1Sjsg uint8_t VariantID; 551*1bb76ff1Sjsg uint8_t spare997; 552*1bb76ff1Sjsg 553*1bb76ff1Sjsg SMU7_HystController_Data HystControllerData; 554*1bb76ff1Sjsg 555*1bb76ff1Sjsg int32_t temperature_gradient_slope; 556*1bb76ff1Sjsg int32_t temperature_gradient; 557*1bb76ff1Sjsg uint32_t measured_temperature; 558*1bb76ff1Sjsg }; 559*1bb76ff1Sjsg 560*1bb76ff1Sjsg 561*1bb76ff1Sjsg typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard; 562*1bb76ff1Sjsg 563*1bb76ff1Sjsg struct SMU7_AcpiScoreboard { 564*1bb76ff1Sjsg uint32_t SavedInterruptMask[2]; 565*1bb76ff1Sjsg uint8_t LastACPIRequest; 566*1bb76ff1Sjsg uint8_t CgBifResp; 567*1bb76ff1Sjsg uint8_t RequestType; 568*1bb76ff1Sjsg uint8_t Padding; 569*1bb76ff1Sjsg SMU74_Discrete_ACPILevel D0Level; 570*1bb76ff1Sjsg }; 571*1bb76ff1Sjsg 572*1bb76ff1Sjsg typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard; 573*1bb76ff1Sjsg 574*1bb76ff1Sjsg struct SMU74_Discrete_PmFuses { 575*1bb76ff1Sjsg uint8_t BapmVddCVidHiSidd[8]; 576*1bb76ff1Sjsg uint8_t BapmVddCVidLoSidd[8]; 577*1bb76ff1Sjsg uint8_t VddCVid[8]; 578*1bb76ff1Sjsg uint8_t SviLoadLineEn; 579*1bb76ff1Sjsg uint8_t SviLoadLineVddC; 580*1bb76ff1Sjsg uint8_t SviLoadLineTrimVddC; 581*1bb76ff1Sjsg uint8_t SviLoadLineOffsetVddC; 582*1bb76ff1Sjsg uint16_t TDC_VDDC_PkgLimit; 583*1bb76ff1Sjsg uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 584*1bb76ff1Sjsg uint8_t TDC_MAWt; 585*1bb76ff1Sjsg uint8_t TdcWaterfallCtl; 586*1bb76ff1Sjsg uint8_t LPMLTemperatureMin; 587*1bb76ff1Sjsg uint8_t LPMLTemperatureMax; 588*1bb76ff1Sjsg uint8_t Reserved; 589*1bb76ff1Sjsg 590*1bb76ff1Sjsg uint8_t LPMLTemperatureScaler[16]; 591*1bb76ff1Sjsg 592*1bb76ff1Sjsg int16_t FuzzyFan_ErrorSetDelta; 593*1bb76ff1Sjsg int16_t FuzzyFan_ErrorRateSetDelta; 594*1bb76ff1Sjsg int16_t FuzzyFan_PwmSetDelta; 595*1bb76ff1Sjsg uint16_t Reserved6; 596*1bb76ff1Sjsg 597*1bb76ff1Sjsg uint8_t GnbLPML[16]; 598*1bb76ff1Sjsg 599*1bb76ff1Sjsg uint8_t GnbLPMLMaxVid; 600*1bb76ff1Sjsg uint8_t GnbLPMLMinVid; 601*1bb76ff1Sjsg uint8_t Reserved1[2]; 602*1bb76ff1Sjsg 603*1bb76ff1Sjsg uint16_t BapmVddCBaseLeakageHiSidd; 604*1bb76ff1Sjsg uint16_t BapmVddCBaseLeakageLoSidd; 605*1bb76ff1Sjsg 606*1bb76ff1Sjsg uint16_t VFT_Temp[3]; 607*1bb76ff1Sjsg uint16_t padding; 608*1bb76ff1Sjsg 609*1bb76ff1Sjsg SMU_QuadraticCoeffs VFT_ATE[3]; 610*1bb76ff1Sjsg 611*1bb76ff1Sjsg SMU_QuadraticCoeffs AVFS_GB; 612*1bb76ff1Sjsg SMU_QuadraticCoeffs ATE_ACBTC_GB; 613*1bb76ff1Sjsg 614*1bb76ff1Sjsg SMU_QuadraticCoeffs P2V; 615*1bb76ff1Sjsg 616*1bb76ff1Sjsg uint32_t PsmCharzFreq; 617*1bb76ff1Sjsg 618*1bb76ff1Sjsg uint16_t InversionVoltage; 619*1bb76ff1Sjsg uint16_t PsmCharzTemp; 620*1bb76ff1Sjsg 621*1bb76ff1Sjsg uint32_t EnabledAvfsModules; 622*1bb76ff1Sjsg }; 623*1bb76ff1Sjsg 624*1bb76ff1Sjsg typedef struct SMU74_Discrete_PmFuses SMU74_Discrete_PmFuses; 625*1bb76ff1Sjsg 626*1bb76ff1Sjsg struct SMU7_Discrete_Log_Header_Table { 627*1bb76ff1Sjsg uint32_t version; 628*1bb76ff1Sjsg uint32_t asic_id; 629*1bb76ff1Sjsg uint16_t flags; 630*1bb76ff1Sjsg uint16_t entry_size; 631*1bb76ff1Sjsg uint32_t total_size; 632*1bb76ff1Sjsg uint32_t num_of_entries; 633*1bb76ff1Sjsg uint8_t type; 634*1bb76ff1Sjsg uint8_t mode; 635*1bb76ff1Sjsg uint8_t filler_0[2]; 636*1bb76ff1Sjsg uint32_t filler_1[2]; 637*1bb76ff1Sjsg }; 638*1bb76ff1Sjsg 639*1bb76ff1Sjsg typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table; 640*1bb76ff1Sjsg 641*1bb76ff1Sjsg struct SMU7_Discrete_Log_Cntl { 642*1bb76ff1Sjsg uint8_t Enabled; 643*1bb76ff1Sjsg uint8_t Type; 644*1bb76ff1Sjsg uint8_t padding[2]; 645*1bb76ff1Sjsg uint32_t BufferSize; 646*1bb76ff1Sjsg uint32_t SamplesLogged; 647*1bb76ff1Sjsg uint32_t SampleSize; 648*1bb76ff1Sjsg uint32_t AddrL; 649*1bb76ff1Sjsg uint32_t AddrH; 650*1bb76ff1Sjsg }; 651*1bb76ff1Sjsg 652*1bb76ff1Sjsg typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl; 653*1bb76ff1Sjsg 654*1bb76ff1Sjsg #if defined SMU__DGPU_ONLY 655*1bb76ff1Sjsg #define CAC_ACC_NW_NUM_OF_SIGNALS 87 656*1bb76ff1Sjsg #endif 657*1bb76ff1Sjsg 658*1bb76ff1Sjsg 659*1bb76ff1Sjsg struct SMU7_Discrete_Cac_Collection_Table { 660*1bb76ff1Sjsg uint32_t temperature; 661*1bb76ff1Sjsg uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; 662*1bb76ff1Sjsg }; 663*1bb76ff1Sjsg 664*1bb76ff1Sjsg typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table; 665*1bb76ff1Sjsg 666*1bb76ff1Sjsg struct SMU7_Discrete_Cac_Verification_Table { 667*1bb76ff1Sjsg uint32_t VddcTotalPower; 668*1bb76ff1Sjsg uint32_t VddcLeakagePower; 669*1bb76ff1Sjsg uint32_t VddcConstantPower; 670*1bb76ff1Sjsg uint32_t VddcGfxDynamicPower; 671*1bb76ff1Sjsg uint32_t VddcUvdDynamicPower; 672*1bb76ff1Sjsg uint32_t VddcVceDynamicPower; 673*1bb76ff1Sjsg uint32_t VddcAcpDynamicPower; 674*1bb76ff1Sjsg uint32_t VddcPcieDynamicPower; 675*1bb76ff1Sjsg uint32_t VddcDceDynamicPower; 676*1bb76ff1Sjsg uint32_t VddcCurrent; 677*1bb76ff1Sjsg uint32_t VddcVoltage; 678*1bb76ff1Sjsg uint32_t VddciTotalPower; 679*1bb76ff1Sjsg uint32_t VddciLeakagePower; 680*1bb76ff1Sjsg uint32_t VddciConstantPower; 681*1bb76ff1Sjsg uint32_t VddciDynamicPower; 682*1bb76ff1Sjsg uint32_t Vddr1TotalPower; 683*1bb76ff1Sjsg uint32_t Vddr1LeakagePower; 684*1bb76ff1Sjsg uint32_t Vddr1ConstantPower; 685*1bb76ff1Sjsg uint32_t Vddr1DynamicPower; 686*1bb76ff1Sjsg uint32_t spare[4]; 687*1bb76ff1Sjsg uint32_t temperature; 688*1bb76ff1Sjsg }; 689*1bb76ff1Sjsg 690*1bb76ff1Sjsg typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table; 691*1bb76ff1Sjsg 692*1bb76ff1Sjsg struct SMU7_Discrete_Pm_Status_Table { 693*1bb76ff1Sjsg int32_t T_meas_max; 694*1bb76ff1Sjsg int32_t T_meas_acc; 695*1bb76ff1Sjsg int32_t T_calc_max; 696*1bb76ff1Sjsg int32_t T_calc_acc; 697*1bb76ff1Sjsg uint32_t P_scalar_acc; 698*1bb76ff1Sjsg uint32_t P_calc_max; 699*1bb76ff1Sjsg uint32_t P_calc_acc; 700*1bb76ff1Sjsg 701*1bb76ff1Sjsg uint32_t I_calc_max; 702*1bb76ff1Sjsg uint32_t I_calc_acc; 703*1bb76ff1Sjsg uint32_t I_calc_acc_vddci; 704*1bb76ff1Sjsg uint32_t V_calc_noload_acc; 705*1bb76ff1Sjsg uint32_t V_calc_load_acc; 706*1bb76ff1Sjsg uint32_t V_calc_noload_acc_vddci; 707*1bb76ff1Sjsg uint32_t P_meas_acc; 708*1bb76ff1Sjsg uint32_t V_meas_noload_acc; 709*1bb76ff1Sjsg uint32_t V_meas_load_acc; 710*1bb76ff1Sjsg uint32_t I_meas_acc; 711*1bb76ff1Sjsg uint32_t P_meas_acc_vddci; 712*1bb76ff1Sjsg uint32_t V_meas_noload_acc_vddci; 713*1bb76ff1Sjsg uint32_t V_meas_load_acc_vddci; 714*1bb76ff1Sjsg uint32_t I_meas_acc_vddci; 715*1bb76ff1Sjsg 716*1bb76ff1Sjsg uint16_t Sclk_dpm_residency[8]; 717*1bb76ff1Sjsg uint16_t Uvd_dpm_residency[8]; 718*1bb76ff1Sjsg uint16_t Vce_dpm_residency[8]; 719*1bb76ff1Sjsg uint16_t Mclk_dpm_residency[4]; 720*1bb76ff1Sjsg 721*1bb76ff1Sjsg uint32_t P_vddci_acc; 722*1bb76ff1Sjsg uint32_t P_vddr1_acc; 723*1bb76ff1Sjsg uint32_t P_nte1_acc; 724*1bb76ff1Sjsg uint32_t PkgPwr_max; 725*1bb76ff1Sjsg uint32_t PkgPwr_acc; 726*1bb76ff1Sjsg uint32_t MclkSwitchingTime_max; 727*1bb76ff1Sjsg uint32_t MclkSwitchingTime_acc; 728*1bb76ff1Sjsg uint32_t FanPwm_acc; 729*1bb76ff1Sjsg uint32_t FanRpm_acc; 730*1bb76ff1Sjsg 731*1bb76ff1Sjsg uint32_t AccCnt; 732*1bb76ff1Sjsg }; 733*1bb76ff1Sjsg 734*1bb76ff1Sjsg typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table; 735*1bb76ff1Sjsg 736*1bb76ff1Sjsg #define SMU7_MAX_GFX_CU_COUNT 16 737*1bb76ff1Sjsg 738*1bb76ff1Sjsg struct SMU7_GfxCuPgScoreboard { 739*1bb76ff1Sjsg uint8_t Enabled; 740*1bb76ff1Sjsg uint8_t WaterfallUp; 741*1bb76ff1Sjsg uint8_t WaterfallDown; 742*1bb76ff1Sjsg uint8_t WaterfallLimit; 743*1bb76ff1Sjsg uint8_t CurrMaxCu; 744*1bb76ff1Sjsg uint8_t TargMaxCu; 745*1bb76ff1Sjsg uint8_t ClampMode; 746*1bb76ff1Sjsg uint8_t Active; 747*1bb76ff1Sjsg uint8_t MaxSupportedCu; 748*1bb76ff1Sjsg uint8_t MinSupportedCu; 749*1bb76ff1Sjsg uint8_t PendingGfxCuHostInterrupt; 750*1bb76ff1Sjsg uint8_t LastFilteredMaxCuInteger; 751*1bb76ff1Sjsg uint16_t FilteredMaxCu; 752*1bb76ff1Sjsg uint16_t FilteredMaxCuAlpha; 753*1bb76ff1Sjsg uint16_t FilterResetCount; 754*1bb76ff1Sjsg uint16_t FilterResetCountLimit; 755*1bb76ff1Sjsg uint8_t ForceCu; 756*1bb76ff1Sjsg uint8_t ForceCuCount; 757*1bb76ff1Sjsg uint8_t spare[2]; 758*1bb76ff1Sjsg }; 759*1bb76ff1Sjsg 760*1bb76ff1Sjsg typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard; 761*1bb76ff1Sjsg 762*1bb76ff1Sjsg #define SMU7_SCLK_CAC 0x561 763*1bb76ff1Sjsg #define SMU7_MCLK_CAC 0xF9 764*1bb76ff1Sjsg #define SMU7_VCLK_CAC 0x2DE 765*1bb76ff1Sjsg #define SMU7_DCLK_CAC 0x2DE 766*1bb76ff1Sjsg #define SMU7_ECLK_CAC 0x25E 767*1bb76ff1Sjsg #define SMU7_ACLK_CAC 0x25E 768*1bb76ff1Sjsg #define SMU7_SAMCLK_CAC 0x25E 769*1bb76ff1Sjsg #define SMU7_DISPCLK_CAC 0x100 770*1bb76ff1Sjsg #define SMU7_CAC_CONSTANT 0x2EE3430 771*1bb76ff1Sjsg #define SMU7_CAC_CONSTANT_SHIFT 18 772*1bb76ff1Sjsg 773*1bb76ff1Sjsg #define SMU7_VDDCI_MCLK_CONST 1765 774*1bb76ff1Sjsg #define SMU7_VDDCI_MCLK_CONST_SHIFT 16 775*1bb76ff1Sjsg #define SMU7_VDDCI_VDDCI_CONST 50958 776*1bb76ff1Sjsg #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14 777*1bb76ff1Sjsg #define SMU7_VDDCI_CONST 11781 778*1bb76ff1Sjsg #define SMU7_VDDCI_STROBE_PWR 1331 779*1bb76ff1Sjsg 780*1bb76ff1Sjsg #define SMU7_VDDR1_CONST 693 781*1bb76ff1Sjsg #define SMU7_VDDR1_CAC_WEIGHT 20 782*1bb76ff1Sjsg #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19 783*1bb76ff1Sjsg #define SMU7_VDDR1_STROBE_PWR 512 784*1bb76ff1Sjsg 785*1bb76ff1Sjsg #define SMU7_AREA_COEFF_UVD 0xA78 786*1bb76ff1Sjsg #define SMU7_AREA_COEFF_VCE 0x190A 787*1bb76ff1Sjsg #define SMU7_AREA_COEFF_ACP 0x22D1 788*1bb76ff1Sjsg #define SMU7_AREA_COEFF_SAMU 0x534 789*1bb76ff1Sjsg 790*1bb76ff1Sjsg #define SMU7_THERM_OUT_MODE_DISABLE 0x0 791*1bb76ff1Sjsg #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 792*1bb76ff1Sjsg #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 793*1bb76ff1Sjsg 794*1bb76ff1Sjsg // DIDT Defines 795*1bb76ff1Sjsg #define SQ_Enable_MASK 0x1 796*1bb76ff1Sjsg #define SQ_IR_MASK 0x2 797*1bb76ff1Sjsg #define SQ_PCC_MASK 0x4 798*1bb76ff1Sjsg #define SQ_EDC_MASK 0x8 799*1bb76ff1Sjsg 800*1bb76ff1Sjsg #define TCP_Enable_MASK 0x100 801*1bb76ff1Sjsg #define TCP_IR_MASK 0x200 802*1bb76ff1Sjsg #define TCP_PCC_MASK 0x400 803*1bb76ff1Sjsg #define TCP_EDC_MASK 0x800 804*1bb76ff1Sjsg 805*1bb76ff1Sjsg #define TD_Enable_MASK 0x10000 806*1bb76ff1Sjsg #define TD_IR_MASK 0x20000 807*1bb76ff1Sjsg #define TD_PCC_MASK 0x40000 808*1bb76ff1Sjsg #define TD_EDC_MASK 0x80000 809*1bb76ff1Sjsg 810*1bb76ff1Sjsg #define DB_Enable_MASK 0x1000000 811*1bb76ff1Sjsg #define DB_IR_MASK 0x2000000 812*1bb76ff1Sjsg #define DB_PCC_MASK 0x4000000 813*1bb76ff1Sjsg #define DB_EDC_MASK 0x8000000 814*1bb76ff1Sjsg 815*1bb76ff1Sjsg #define SQ_Enable_SHIFT 0 816*1bb76ff1Sjsg #define SQ_IR_SHIFT 1 817*1bb76ff1Sjsg #define SQ_PCC_SHIFT 2 818*1bb76ff1Sjsg #define SQ_EDC_SHIFT 3 819*1bb76ff1Sjsg 820*1bb76ff1Sjsg #define TCP_Enable_SHIFT 8 821*1bb76ff1Sjsg #define TCP_IR_SHIFT 9 822*1bb76ff1Sjsg #define TCP_PCC_SHIFT 10 823*1bb76ff1Sjsg #define TCP_EDC_SHIFT 11 824*1bb76ff1Sjsg 825*1bb76ff1Sjsg #define TD_Enable_SHIFT 16 826*1bb76ff1Sjsg #define TD_IR_SHIFT 17 827*1bb76ff1Sjsg #define TD_PCC_SHIFT 18 828*1bb76ff1Sjsg #define TD_EDC_SHIFT 19 829*1bb76ff1Sjsg 830*1bb76ff1Sjsg #define DB_Enable_SHIFT 24 831*1bb76ff1Sjsg #define DB_IR_SHIFT 25 832*1bb76ff1Sjsg #define DB_PCC_SHIFT 26 833*1bb76ff1Sjsg #define DB_EDC_SHIFT 27 834*1bb76ff1Sjsg 835*1bb76ff1Sjsg #define BTCGB0_Vdroop_Enable_MASK 0x1 836*1bb76ff1Sjsg #define BTCGB1_Vdroop_Enable_MASK 0x2 837*1bb76ff1Sjsg #define AVFSGB0_Vdroop_Enable_MASK 0x4 838*1bb76ff1Sjsg #define AVFSGB1_Vdroop_Enable_MASK 0x8 839*1bb76ff1Sjsg 840*1bb76ff1Sjsg #define BTCGB0_Vdroop_Enable_SHIFT 0 841*1bb76ff1Sjsg #define BTCGB1_Vdroop_Enable_SHIFT 1 842*1bb76ff1Sjsg #define AVFSGB0_Vdroop_Enable_SHIFT 2 843*1bb76ff1Sjsg #define AVFSGB1_Vdroop_Enable_SHIFT 3 844*1bb76ff1Sjsg 845*1bb76ff1Sjsg 846*1bb76ff1Sjsg #pragma pack(pop) 847*1bb76ff1Sjsg 848*1bb76ff1Sjsg 849*1bb76ff1Sjsg #endif 850*1bb76ff1Sjsg 851