1*f005ef32Sjsg /* 2*f005ef32Sjsg * Copyright 2021 Advanced Micro Devices, Inc. 3*f005ef32Sjsg * 4*f005ef32Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*f005ef32Sjsg * copy of this software and associated documentation files (the "Software"), 6*f005ef32Sjsg * to deal in the Software without restriction, including without limitation 7*f005ef32Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*f005ef32Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9*f005ef32Sjsg * Software is furnished to do so, subject to the following conditions: 10*f005ef32Sjsg * 11*f005ef32Sjsg * The above copyright notice and this permission notice shall be included in 12*f005ef32Sjsg * all copies or substantial portions of the Software. 13*f005ef32Sjsg * 14*f005ef32Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*f005ef32Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*f005ef32Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*f005ef32Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*f005ef32Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*f005ef32Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*f005ef32Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21*f005ef32Sjsg * 22*f005ef32Sjsg */ 23*f005ef32Sjsg #ifndef SMU_13_0_6_PPSMC_H 24*f005ef32Sjsg #define SMU_13_0_6_PPSMC_H 25*f005ef32Sjsg 26*f005ef32Sjsg // SMU Response Codes: 27*f005ef32Sjsg #define PPSMC_Result_OK 0x1 28*f005ef32Sjsg #define PPSMC_Result_Failed 0xFF 29*f005ef32Sjsg #define PPSMC_Result_UnknownCmd 0xFE 30*f005ef32Sjsg #define PPSMC_Result_CmdRejectedPrereq 0xFD 31*f005ef32Sjsg #define PPSMC_Result_CmdRejectedBusy 0xFC 32*f005ef32Sjsg 33*f005ef32Sjsg // Message Definitions: 34*f005ef32Sjsg #define PPSMC_MSG_TestMessage 0x1 35*f005ef32Sjsg #define PPSMC_MSG_GetSmuVersion 0x2 36*f005ef32Sjsg #define PPSMC_MSG_GfxDriverReset 0x3 37*f005ef32Sjsg #define PPSMC_MSG_GetDriverIfVersion 0x4 38*f005ef32Sjsg #define PPSMC_MSG_EnableAllSmuFeatures 0x5 39*f005ef32Sjsg #define PPSMC_MSG_DisableAllSmuFeatures 0x6 40*f005ef32Sjsg #define PPSMC_MSG_RequestI2cTransaction 0x7 41*f005ef32Sjsg #define PPSMC_MSG_GetMetricsVersion 0x8 42*f005ef32Sjsg #define PPSMC_MSG_GetMetricsTable 0x9 43*f005ef32Sjsg #define PPSMC_MSG_GetEccInfoTable 0xA 44*f005ef32Sjsg #define PPSMC_MSG_GetEnabledSmuFeaturesLow 0xB 45*f005ef32Sjsg #define PPSMC_MSG_GetEnabledSmuFeaturesHigh 0xC 46*f005ef32Sjsg #define PPSMC_MSG_SetDriverDramAddrHigh 0xD 47*f005ef32Sjsg #define PPSMC_MSG_SetDriverDramAddrLow 0xE 48*f005ef32Sjsg #define PPSMC_MSG_SetToolsDramAddrHigh 0xF 49*f005ef32Sjsg #define PPSMC_MSG_SetToolsDramAddrLow 0x10 50*f005ef32Sjsg #define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x11 51*f005ef32Sjsg #define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x12 52*f005ef32Sjsg #define PPSMC_MSG_SetSoftMinByFreq 0x13 53*f005ef32Sjsg #define PPSMC_MSG_SetSoftMaxByFreq 0x14 54*f005ef32Sjsg #define PPSMC_MSG_GetMinDpmFreq 0x15 55*f005ef32Sjsg #define PPSMC_MSG_GetMaxDpmFreq 0x16 56*f005ef32Sjsg #define PPSMC_MSG_GetDpmFreqByIndex 0x17 57*f005ef32Sjsg #define PPSMC_MSG_SetPptLimit 0x18 58*f005ef32Sjsg #define PPSMC_MSG_GetPptLimit 0x19 59*f005ef32Sjsg #define PPSMC_MSG_DramLogSetDramAddrHigh 0x1A 60*f005ef32Sjsg #define PPSMC_MSG_DramLogSetDramAddrLow 0x1B 61*f005ef32Sjsg #define PPSMC_MSG_DramLogSetDramSize 0x1C 62*f005ef32Sjsg #define PPSMC_MSG_GetDebugData 0x1D 63*f005ef32Sjsg #define PPSMC_MSG_HeavySBR 0x1E 64*f005ef32Sjsg #define PPSMC_MSG_SetNumBadHbmPagesRetired 0x1F 65*f005ef32Sjsg #define PPSMC_MSG_DFCstateControl 0x20 66*f005ef32Sjsg #define PPSMC_MSG_GetGmiPwrDnHyst 0x21 67*f005ef32Sjsg #define PPSMC_MSG_SetGmiPwrDnHyst 0x22 68*f005ef32Sjsg #define PPSMC_MSG_GmiPwrDnControl 0x23 69*f005ef32Sjsg #define PPSMC_MSG_EnterGfxoff 0x24 70*f005ef32Sjsg #define PPSMC_MSG_ExitGfxoff 0x25 71*f005ef32Sjsg #define PPSMC_MSG_EnableDeterminism 0x26 72*f005ef32Sjsg #define PPSMC_MSG_DisableDeterminism 0x27 73*f005ef32Sjsg #define PPSMC_MSG_DumpSTBtoDram 0x28 74*f005ef32Sjsg #define PPSMC_MSG_STBtoDramLogSetDramAddrHigh 0x29 75*f005ef32Sjsg #define PPSMC_MSG_STBtoDramLogSetDramAddrLow 0x2A 76*f005ef32Sjsg #define PPSMC_MSG_STBtoDramLogSetDramSize 0x2B 77*f005ef32Sjsg #define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrHigh 0x2C 78*f005ef32Sjsg #define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow 0x2D 79*f005ef32Sjsg #define PPSMC_MSG_GfxDriverResetRecovery 0x2E 80*f005ef32Sjsg #define PPSMC_MSG_TriggerVFFLR 0x2F 81*f005ef32Sjsg #define PPSMC_MSG_SetSoftMinGfxClk 0x30 82*f005ef32Sjsg #define PPSMC_MSG_SetSoftMaxGfxClk 0x31 83*f005ef32Sjsg #define PPSMC_MSG_GetMinGfxDpmFreq 0x32 84*f005ef32Sjsg #define PPSMC_MSG_GetMaxGfxDpmFreq 0x33 85*f005ef32Sjsg #define PPSMC_MSG_PrepareForDriverUnload 0x34 86*f005ef32Sjsg #define PPSMC_MSG_ReadThrottlerLimit 0x35 87*f005ef32Sjsg #define PPSMC_MSG_QueryValidMcaCount 0x36 88*f005ef32Sjsg #define PPSMC_MSG_McaBankDumpDW 0x37 89*f005ef32Sjsg #define PPSMC_MSG_GetCTFLimit 0x38 90*f005ef32Sjsg #define PPSMC_Message_Count 0x39 91*f005ef32Sjsg 92*f005ef32Sjsg //PPSMC Reset Types for driver msg argument 93*f005ef32Sjsg #define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1 94*f005ef32Sjsg #define PPSMC_RESET_TYPE_DRIVER_MODE_2_RESET 0x2 95*f005ef32Sjsg #define PPSMC_RESET_TYPE_DRIVER_MODE_3_RESET 0x3 96*f005ef32Sjsg 97*f005ef32Sjsg //PPSMC Reset Types for driver msg argument 98*f005ef32Sjsg #define PPSMC_THROTTLING_LIMIT_TYPE_SOCKET 0x1 99*f005ef32Sjsg #define PPSMC_THROTTLING_LIMIT_TYPE_HBM 0x2 100*f005ef32Sjsg 101*f005ef32Sjsg //CTF/Throttle Limit types 102*f005ef32Sjsg #define PPSMC_AID_THM_TYPE 0x1 103*f005ef32Sjsg #define PPSMC_CCD_THM_TYPE 0x2 104*f005ef32Sjsg #define PPSMC_XCD_THM_TYPE 0x3 105*f005ef32Sjsg #define PPSMC_HBM_THM_TYPE 0x4 106*f005ef32Sjsg 107*f005ef32Sjsg typedef uint32_t PPSMC_Result; 108*f005ef32Sjsg typedef uint32_t PPSMC_MSG; 109*f005ef32Sjsg 110*f005ef32Sjsg #endif 111