1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_probe_helper.h> 35 36 #include "i915_drv.h" 37 #include "intel_connector.h" 38 #include "intel_crt.h" 39 #include "intel_crtc.h" 40 #include "intel_ddi.h" 41 #include "intel_ddi_buf_trans.h" 42 #include "intel_de.h" 43 #include "intel_display_types.h" 44 #include "intel_fdi.h" 45 #include "intel_fifo_underrun.h" 46 #include "intel_gmbus.h" 47 #include "intel_hotplug.h" 48 #include "intel_pch_display.h" 49 #include "intel_pch_refclk.h" 50 51 /* Here's the desired hotplug mode */ 52 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 53 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 54 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 55 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 56 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 57 ADPA_CRT_HOTPLUG_ENABLE) 58 59 struct intel_crt { 60 struct intel_encoder base; 61 /* DPMS state is stored in the connector, which we need in the 62 * encoder's enable/disable callbacks */ 63 struct intel_connector *connector; 64 bool force_hotplug_required; 65 i915_reg_t adpa_reg; 66 }; 67 68 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 69 { 70 return container_of(encoder, struct intel_crt, base); 71 } 72 73 static struct intel_crt *intel_attached_crt(struct intel_connector *connector) 74 { 75 return intel_encoder_to_crt(intel_attached_encoder(connector)); 76 } 77 78 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, 79 i915_reg_t adpa_reg, enum pipe *pipe) 80 { 81 u32 val; 82 83 val = intel_de_read(dev_priv, adpa_reg); 84 85 /* asserts want to know the pipe even if the port is disabled */ 86 if (HAS_PCH_CPT(dev_priv)) 87 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT; 88 else 89 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT; 90 91 return val & ADPA_DAC_ENABLE; 92 } 93 94 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 95 enum pipe *pipe) 96 { 97 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 98 struct intel_crt *crt = intel_encoder_to_crt(encoder); 99 intel_wakeref_t wakeref; 100 bool ret; 101 102 wakeref = intel_display_power_get_if_enabled(dev_priv, 103 encoder->power_domain); 104 if (!wakeref) 105 return false; 106 107 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); 108 109 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 110 111 return ret; 112 } 113 114 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 115 { 116 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 117 struct intel_crt *crt = intel_encoder_to_crt(encoder); 118 u32 tmp, flags = 0; 119 120 tmp = intel_de_read(dev_priv, crt->adpa_reg); 121 122 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 123 flags |= DRM_MODE_FLAG_PHSYNC; 124 else 125 flags |= DRM_MODE_FLAG_NHSYNC; 126 127 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 128 flags |= DRM_MODE_FLAG_PVSYNC; 129 else 130 flags |= DRM_MODE_FLAG_NVSYNC; 131 132 return flags; 133 } 134 135 static void intel_crt_get_config(struct intel_encoder *encoder, 136 struct intel_crtc_state *pipe_config) 137 { 138 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 139 140 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 141 142 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 143 } 144 145 static void hsw_crt_get_config(struct intel_encoder *encoder, 146 struct intel_crtc_state *pipe_config) 147 { 148 lpt_pch_get_config(pipe_config); 149 150 hsw_ddi_get_config(encoder, pipe_config); 151 152 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 153 DRM_MODE_FLAG_NHSYNC | 154 DRM_MODE_FLAG_PVSYNC | 155 DRM_MODE_FLAG_NVSYNC); 156 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 157 } 158 159 /* Note: The caller is required to filter out dpms modes not supported by the 160 * platform. */ 161 static void intel_crt_set_dpms(struct intel_encoder *encoder, 162 const struct intel_crtc_state *crtc_state, 163 int mode) 164 { 165 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 166 struct intel_crt *crt = intel_encoder_to_crt(encoder); 167 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 168 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 169 u32 adpa; 170 171 if (DISPLAY_VER(dev_priv) >= 5) 172 adpa = ADPA_HOTPLUG_BITS; 173 else 174 adpa = 0; 175 176 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 177 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 178 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 179 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 180 181 /* For CPT allow 3 pipe config, for others just use A or B */ 182 if (HAS_PCH_LPT(dev_priv)) 183 ; /* Those bits don't exist here */ 184 else if (HAS_PCH_CPT(dev_priv)) 185 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); 186 else 187 adpa |= ADPA_PIPE_SEL(crtc->pipe); 188 189 if (!HAS_PCH_SPLIT(dev_priv)) 190 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 191 192 switch (mode) { 193 case DRM_MODE_DPMS_ON: 194 adpa |= ADPA_DAC_ENABLE; 195 break; 196 case DRM_MODE_DPMS_STANDBY: 197 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 198 break; 199 case DRM_MODE_DPMS_SUSPEND: 200 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 201 break; 202 case DRM_MODE_DPMS_OFF: 203 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 204 break; 205 } 206 207 intel_de_write(dev_priv, crt->adpa_reg, adpa); 208 } 209 210 static void intel_disable_crt(struct intel_atomic_state *state, 211 struct intel_encoder *encoder, 212 const struct intel_crtc_state *old_crtc_state, 213 const struct drm_connector_state *old_conn_state) 214 { 215 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); 216 } 217 218 static void pch_disable_crt(struct intel_atomic_state *state, 219 struct intel_encoder *encoder, 220 const struct intel_crtc_state *old_crtc_state, 221 const struct drm_connector_state *old_conn_state) 222 { 223 } 224 225 static void pch_post_disable_crt(struct intel_atomic_state *state, 226 struct intel_encoder *encoder, 227 const struct intel_crtc_state *old_crtc_state, 228 const struct drm_connector_state *old_conn_state) 229 { 230 intel_disable_crt(state, encoder, old_crtc_state, old_conn_state); 231 } 232 233 static void hsw_disable_crt(struct intel_atomic_state *state, 234 struct intel_encoder *encoder, 235 const struct intel_crtc_state *old_crtc_state, 236 const struct drm_connector_state *old_conn_state) 237 { 238 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 239 240 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); 241 242 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 243 } 244 245 static void hsw_post_disable_crt(struct intel_atomic_state *state, 246 struct intel_encoder *encoder, 247 const struct intel_crtc_state *old_crtc_state, 248 const struct drm_connector_state *old_conn_state) 249 { 250 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 251 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 252 253 intel_crtc_vblank_off(old_crtc_state); 254 255 intel_disable_transcoder(old_crtc_state); 256 257 intel_ddi_disable_transcoder_func(old_crtc_state); 258 259 ilk_pfit_disable(old_crtc_state); 260 261 intel_ddi_disable_pipe_clock(old_crtc_state); 262 263 pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state); 264 265 lpt_pch_disable(state, crtc); 266 267 hsw_fdi_disable(encoder); 268 269 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); 270 271 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 272 } 273 274 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state, 275 struct intel_encoder *encoder, 276 const struct intel_crtc_state *crtc_state, 277 const struct drm_connector_state *conn_state) 278 { 279 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 280 281 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); 282 283 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 284 } 285 286 static void hsw_pre_enable_crt(struct intel_atomic_state *state, 287 struct intel_encoder *encoder, 288 const struct intel_crtc_state *crtc_state, 289 const struct drm_connector_state *conn_state) 290 { 291 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 292 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 293 enum pipe pipe = crtc->pipe; 294 295 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); 296 297 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 298 299 hsw_fdi_link_train(encoder, crtc_state); 300 301 intel_ddi_enable_pipe_clock(encoder, crtc_state); 302 } 303 304 static void hsw_enable_crt(struct intel_atomic_state *state, 305 struct intel_encoder *encoder, 306 const struct intel_crtc_state *crtc_state, 307 const struct drm_connector_state *conn_state) 308 { 309 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 310 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 311 enum pipe pipe = crtc->pipe; 312 313 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); 314 315 intel_ddi_enable_transcoder_func(encoder, crtc_state); 316 317 intel_enable_transcoder(crtc_state); 318 319 lpt_pch_enable(state, crtc); 320 321 intel_crtc_vblank_on(crtc_state); 322 323 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 324 325 intel_crtc_wait_for_next_vblank(crtc); 326 intel_crtc_wait_for_next_vblank(crtc); 327 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 328 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 329 } 330 331 static void intel_enable_crt(struct intel_atomic_state *state, 332 struct intel_encoder *encoder, 333 const struct intel_crtc_state *crtc_state, 334 const struct drm_connector_state *conn_state) 335 { 336 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 337 } 338 339 static enum drm_mode_status 340 intel_crt_mode_valid(struct drm_connector *connector, 341 struct drm_display_mode *mode) 342 { 343 struct drm_device *dev = connector->dev; 344 struct drm_i915_private *dev_priv = to_i915(dev); 345 int max_dotclk = dev_priv->max_dotclk_freq; 346 enum drm_mode_status status; 347 int max_clock; 348 349 status = intel_cpu_transcoder_mode_valid(dev_priv, mode); 350 if (status != MODE_OK) 351 return status; 352 353 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 354 return MODE_NO_DBLESCAN; 355 356 if (mode->clock < 25000) 357 return MODE_CLOCK_LOW; 358 359 if (HAS_PCH_LPT(dev_priv)) 360 max_clock = 180000; 361 else if (IS_VALLEYVIEW(dev_priv)) 362 /* 363 * 270 MHz due to current DPLL limits, 364 * DAC limit supposedly 355 MHz. 365 */ 366 max_clock = 270000; 367 else if (IS_DISPLAY_VER(dev_priv, 3, 4)) 368 max_clock = 400000; 369 else 370 max_clock = 350000; 371 if (mode->clock > max_clock) 372 return MODE_CLOCK_HIGH; 373 374 if (mode->clock > max_dotclk) 375 return MODE_CLOCK_HIGH; 376 377 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 378 if (HAS_PCH_LPT(dev_priv) && 379 ilk_get_lanes_required(mode->clock, 270000, 24) > 2) 380 return MODE_CLOCK_HIGH; 381 382 /* HSW/BDW FDI limited to 4k */ 383 if (mode->hdisplay > 4096) 384 return MODE_H_ILLEGAL; 385 386 return MODE_OK; 387 } 388 389 static int intel_crt_compute_config(struct intel_encoder *encoder, 390 struct intel_crtc_state *pipe_config, 391 struct drm_connector_state *conn_state) 392 { 393 struct drm_display_mode *adjusted_mode = 394 &pipe_config->hw.adjusted_mode; 395 396 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 397 return -EINVAL; 398 399 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 400 401 return 0; 402 } 403 404 static int pch_crt_compute_config(struct intel_encoder *encoder, 405 struct intel_crtc_state *pipe_config, 406 struct drm_connector_state *conn_state) 407 { 408 struct drm_display_mode *adjusted_mode = 409 &pipe_config->hw.adjusted_mode; 410 411 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 412 return -EINVAL; 413 414 pipe_config->has_pch_encoder = true; 415 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 416 417 return 0; 418 } 419 420 static int hsw_crt_compute_config(struct intel_encoder *encoder, 421 struct intel_crtc_state *pipe_config, 422 struct drm_connector_state *conn_state) 423 { 424 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 425 struct drm_display_mode *adjusted_mode = 426 &pipe_config->hw.adjusted_mode; 427 428 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 429 return -EINVAL; 430 431 /* HSW/BDW FDI limited to 4k */ 432 if (adjusted_mode->crtc_hdisplay > 4096 || 433 adjusted_mode->crtc_hblank_start > 4096) 434 return -EINVAL; 435 436 pipe_config->has_pch_encoder = true; 437 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 438 439 /* LPT FDI RX only supports 8bpc. */ 440 if (HAS_PCH_LPT(dev_priv)) { 441 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { 442 drm_dbg_kms(&dev_priv->drm, 443 "LPT only supports 24bpp\n"); 444 return -EINVAL; 445 } 446 447 pipe_config->pipe_bpp = 24; 448 } 449 450 /* FDI must always be 2.7 GHz */ 451 pipe_config->port_clock = 135000 * 2; 452 453 adjusted_mode->crtc_clock = lpt_iclkip(pipe_config); 454 455 return 0; 456 } 457 458 static bool ilk_crt_detect_hotplug(struct drm_connector *connector) 459 { 460 struct drm_device *dev = connector->dev; 461 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 462 struct drm_i915_private *dev_priv = to_i915(dev); 463 u32 adpa; 464 bool ret; 465 466 /* The first time through, trigger an explicit detection cycle */ 467 if (crt->force_hotplug_required) { 468 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); 469 u32 save_adpa; 470 471 crt->force_hotplug_required = false; 472 473 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); 474 drm_dbg_kms(&dev_priv->drm, 475 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); 476 477 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 478 if (turn_off_dac) 479 adpa &= ~ADPA_DAC_ENABLE; 480 481 intel_de_write(dev_priv, crt->adpa_reg, adpa); 482 483 if (intel_de_wait_for_clear(dev_priv, 484 crt->adpa_reg, 485 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 486 1000)) 487 drm_dbg_kms(&dev_priv->drm, 488 "timed out waiting for FORCE_TRIGGER"); 489 490 if (turn_off_dac) { 491 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); 492 intel_de_posting_read(dev_priv, crt->adpa_reg); 493 } 494 } 495 496 /* Check the status to see if both blue and green are on now */ 497 adpa = intel_de_read(dev_priv, crt->adpa_reg); 498 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 499 ret = true; 500 else 501 ret = false; 502 drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n", 503 adpa, ret); 504 505 return ret; 506 } 507 508 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 509 { 510 struct drm_device *dev = connector->dev; 511 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 512 struct drm_i915_private *dev_priv = to_i915(dev); 513 bool reenable_hpd; 514 u32 adpa; 515 bool ret; 516 u32 save_adpa; 517 518 /* 519 * Doing a force trigger causes a hpd interrupt to get sent, which can 520 * get us stuck in a loop if we're polling: 521 * - We enable power wells and reset the ADPA 522 * - output_poll_exec does force probe on VGA, triggering a hpd 523 * - HPD handler waits for poll to unlock dev->mode_config.mutex 524 * - output_poll_exec shuts off the ADPA, unlocks 525 * dev->mode_config.mutex 526 * - HPD handler runs, resets ADPA and brings us back to the start 527 * 528 * Just disable HPD interrupts here to prevent this 529 */ 530 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); 531 532 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); 533 drm_dbg_kms(&dev_priv->drm, 534 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); 535 536 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 537 538 intel_de_write(dev_priv, crt->adpa_reg, adpa); 539 540 if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg, 541 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) { 542 drm_dbg_kms(&dev_priv->drm, 543 "timed out waiting for FORCE_TRIGGER"); 544 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); 545 } 546 547 /* Check the status to see if both blue and green are on now */ 548 adpa = intel_de_read(dev_priv, crt->adpa_reg); 549 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 550 ret = true; 551 else 552 ret = false; 553 554 drm_dbg_kms(&dev_priv->drm, 555 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 556 557 if (reenable_hpd) 558 intel_hpd_enable(dev_priv, crt->base.hpd_pin); 559 560 return ret; 561 } 562 563 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 564 { 565 struct drm_device *dev = connector->dev; 566 struct drm_i915_private *dev_priv = to_i915(dev); 567 u32 stat; 568 bool ret = false; 569 int i, tries = 0; 570 571 if (HAS_PCH_SPLIT(dev_priv)) 572 return ilk_crt_detect_hotplug(connector); 573 574 if (IS_VALLEYVIEW(dev_priv)) 575 return valleyview_crt_detect_hotplug(connector); 576 577 /* 578 * On 4 series desktop, CRT detect sequence need to be done twice 579 * to get a reliable result. 580 */ 581 582 if (IS_G45(dev_priv)) 583 tries = 2; 584 else 585 tries = 1; 586 587 for (i = 0; i < tries ; i++) { 588 /* turn on the FORCE_DETECT */ 589 i915_hotplug_interrupt_update(dev_priv, 590 CRT_HOTPLUG_FORCE_DETECT, 591 CRT_HOTPLUG_FORCE_DETECT); 592 /* wait for FORCE_DETECT to go off */ 593 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN, 594 CRT_HOTPLUG_FORCE_DETECT, 1000)) 595 drm_dbg_kms(&dev_priv->drm, 596 "timed out waiting for FORCE_DETECT to go off"); 597 } 598 599 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT); 600 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 601 ret = true; 602 603 /* clear the interrupt we just generated, if any */ 604 intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 605 606 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); 607 608 return ret; 609 } 610 611 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 612 struct i2c_adapter *i2c) 613 { 614 struct edid *edid; 615 616 edid = drm_get_edid(connector, i2c); 617 618 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 619 drm_dbg_kms(connector->dev, 620 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 621 intel_gmbus_force_bit(i2c, true); 622 edid = drm_get_edid(connector, i2c); 623 intel_gmbus_force_bit(i2c, false); 624 } 625 626 return edid; 627 } 628 629 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 630 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 631 struct i2c_adapter *adapter) 632 { 633 struct edid *edid; 634 int ret; 635 636 edid = intel_crt_get_edid(connector, adapter); 637 if (!edid) 638 return 0; 639 640 ret = intel_connector_update_modes(connector, edid); 641 kfree(edid); 642 643 return ret; 644 } 645 646 static bool intel_crt_detect_ddc(struct drm_connector *connector) 647 { 648 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 649 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); 650 struct edid *edid; 651 struct i2c_adapter *i2c; 652 bool ret = false; 653 654 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin); 655 edid = intel_crt_get_edid(connector, i2c); 656 657 if (edid) { 658 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 659 660 /* 661 * This may be a DVI-I connector with a shared DDC 662 * link between analog and digital outputs, so we 663 * have to check the EDID input spec of the attached device. 664 */ 665 if (!is_digital) { 666 drm_dbg_kms(&dev_priv->drm, 667 "CRT detected via DDC:0x50 [EDID]\n"); 668 ret = true; 669 } else { 670 drm_dbg_kms(&dev_priv->drm, 671 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 672 } 673 } else { 674 drm_dbg_kms(&dev_priv->drm, 675 "CRT not detected via DDC:0x50 [no valid EDID found]\n"); 676 } 677 678 kfree(edid); 679 680 return ret; 681 } 682 683 static enum drm_connector_status 684 intel_crt_load_detect(struct intel_crt *crt, u32 pipe) 685 { 686 struct drm_device *dev = crt->base.base.dev; 687 struct drm_i915_private *dev_priv = to_i915(dev); 688 struct intel_uncore *uncore = &dev_priv->uncore; 689 u32 save_bclrpat; 690 u32 save_vtotal; 691 u32 vtotal, vactive; 692 u32 vsample; 693 u32 vblank, vblank_start, vblank_end; 694 u32 dsl; 695 i915_reg_t bclrpat_reg, vtotal_reg, 696 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; 697 u8 st00; 698 enum drm_connector_status status; 699 700 drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n"); 701 702 bclrpat_reg = BCLRPAT(pipe); 703 vtotal_reg = VTOTAL(pipe); 704 vblank_reg = VBLANK(pipe); 705 vsync_reg = VSYNC(pipe); 706 pipeconf_reg = PIPECONF(pipe); 707 pipe_dsl_reg = PIPEDSL(pipe); 708 709 save_bclrpat = intel_uncore_read(uncore, bclrpat_reg); 710 save_vtotal = intel_uncore_read(uncore, vtotal_reg); 711 vblank = intel_uncore_read(uncore, vblank_reg); 712 713 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 714 vactive = (save_vtotal & 0x7ff) + 1; 715 716 vblank_start = (vblank & 0xfff) + 1; 717 vblank_end = ((vblank >> 16) & 0xfff) + 1; 718 719 /* Set the border color to purple. */ 720 intel_uncore_write(uncore, bclrpat_reg, 0x500050); 721 722 if (DISPLAY_VER(dev_priv) != 2) { 723 u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg); 724 intel_uncore_write(uncore, 725 pipeconf_reg, 726 pipeconf | PIPECONF_FORCE_BORDER); 727 intel_uncore_posting_read(uncore, pipeconf_reg); 728 /* Wait for next Vblank to substitue 729 * border color for Color info */ 730 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); 731 st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE); 732 status = ((st00 & (1 << 4)) != 0) ? 733 connector_status_connected : 734 connector_status_disconnected; 735 736 intel_uncore_write(uncore, pipeconf_reg, pipeconf); 737 } else { 738 bool restore_vblank = false; 739 int count, detect; 740 741 /* 742 * If there isn't any border, add some. 743 * Yes, this will flicker 744 */ 745 if (vblank_start <= vactive && vblank_end >= vtotal) { 746 u32 vsync = intel_de_read(dev_priv, vsync_reg); 747 u32 vsync_start = (vsync & 0xffff) + 1; 748 749 vblank_start = vsync_start; 750 intel_uncore_write(uncore, 751 vblank_reg, 752 (vblank_start - 1) | 753 ((vblank_end - 1) << 16)); 754 restore_vblank = true; 755 } 756 /* sample in the vertical border, selecting the larger one */ 757 if (vblank_start - vactive >= vtotal - vblank_end) 758 vsample = (vblank_start + vactive) >> 1; 759 else 760 vsample = (vtotal + vblank_end) >> 1; 761 762 /* 763 * Wait for the border to be displayed 764 */ 765 while (intel_uncore_read(uncore, pipe_dsl_reg) >= vactive) 766 ; 767 while ((dsl = intel_uncore_read(uncore, pipe_dsl_reg)) <= 768 vsample) 769 ; 770 /* 771 * Watch ST00 for an entire scanline 772 */ 773 detect = 0; 774 count = 0; 775 do { 776 count++; 777 /* Read the ST00 VGA status register */ 778 st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE); 779 if (st00 & (1 << 4)) 780 detect++; 781 } while ((intel_uncore_read(uncore, pipe_dsl_reg) == dsl)); 782 783 /* restore vblank if necessary */ 784 if (restore_vblank) 785 intel_uncore_write(uncore, vblank_reg, vblank); 786 /* 787 * If more than 3/4 of the scanline detected a monitor, 788 * then it is assumed to be present. This works even on i830, 789 * where there isn't any way to force the border color across 790 * the screen 791 */ 792 status = detect * 4 > count * 3 ? 793 connector_status_connected : 794 connector_status_disconnected; 795 } 796 797 /* Restore previous settings */ 798 intel_uncore_write(uncore, bclrpat_reg, save_bclrpat); 799 800 return status; 801 } 802 803 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) 804 { 805 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); 806 return 1; 807 } 808 809 static const struct dmi_system_id intel_spurious_crt_detect[] = { 810 { 811 .callback = intel_spurious_crt_detect_dmi_callback, 812 .ident = "ACER ZGB", 813 .matches = { 814 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 815 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 816 }, 817 }, 818 { 819 .callback = intel_spurious_crt_detect_dmi_callback, 820 .ident = "Intel DZ77BH-55K", 821 .matches = { 822 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), 823 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), 824 }, 825 }, 826 { } 827 }; 828 829 static int 830 intel_crt_detect(struct drm_connector *connector, 831 struct drm_modeset_acquire_ctx *ctx, 832 bool force) 833 { 834 struct drm_i915_private *dev_priv = to_i915(connector->dev); 835 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 836 struct intel_encoder *intel_encoder = &crt->base; 837 intel_wakeref_t wakeref; 838 int status, ret; 839 struct intel_load_detect_pipe tmp; 840 841 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n", 842 connector->base.id, connector->name, 843 force); 844 845 if (!INTEL_DISPLAY_ENABLED(dev_priv)) 846 return connector_status_disconnected; 847 848 if (dev_priv->params.load_detect_test) { 849 wakeref = intel_display_power_get(dev_priv, 850 intel_encoder->power_domain); 851 goto load_detect; 852 } 853 854 /* Skip machines without VGA that falsely report hotplug events */ 855 if (dmi_check_system(intel_spurious_crt_detect)) 856 return connector_status_disconnected; 857 858 wakeref = intel_display_power_get(dev_priv, 859 intel_encoder->power_domain); 860 861 if (I915_HAS_HOTPLUG(dev_priv)) { 862 /* We can not rely on the HPD pin always being correctly wired 863 * up, for example many KVM do not pass it through, and so 864 * only trust an assertion that the monitor is connected. 865 */ 866 if (intel_crt_detect_hotplug(connector)) { 867 drm_dbg_kms(&dev_priv->drm, 868 "CRT detected via hotplug\n"); 869 status = connector_status_connected; 870 goto out; 871 } else 872 drm_dbg_kms(&dev_priv->drm, 873 "CRT not detected via hotplug\n"); 874 } 875 876 if (intel_crt_detect_ddc(connector)) { 877 status = connector_status_connected; 878 goto out; 879 } 880 881 /* Load detection is broken on HPD capable machines. Whoever wants a 882 * broken monitor (without edid) to work behind a broken kvm (that fails 883 * to have the right resistors for HP detection) needs to fix this up. 884 * For now just bail out. */ 885 if (I915_HAS_HOTPLUG(dev_priv)) { 886 status = connector_status_disconnected; 887 goto out; 888 } 889 890 load_detect: 891 if (!force) { 892 status = connector->status; 893 goto out; 894 } 895 896 /* for pre-945g platforms use load detect */ 897 ret = intel_get_load_detect_pipe(connector, &tmp, ctx); 898 if (ret > 0) { 899 if (intel_crt_detect_ddc(connector)) 900 status = connector_status_connected; 901 else if (DISPLAY_VER(dev_priv) < 4) 902 status = intel_crt_load_detect(crt, 903 to_intel_crtc(connector->state->crtc)->pipe); 904 else if (dev_priv->params.load_detect_test) 905 status = connector_status_disconnected; 906 else 907 status = connector_status_unknown; 908 intel_release_load_detect_pipe(connector, &tmp, ctx); 909 } else if (ret == 0) { 910 status = connector_status_unknown; 911 } else { 912 status = ret; 913 } 914 915 out: 916 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 917 918 /* 919 * Make sure the refs for power wells enabled during detect are 920 * dropped to avoid a new detect cycle triggered by HPD polling. 921 */ 922 intel_display_power_flush_work(dev_priv); 923 924 return status; 925 } 926 927 static int intel_crt_get_modes(struct drm_connector *connector) 928 { 929 struct drm_device *dev = connector->dev; 930 struct drm_i915_private *dev_priv = to_i915(dev); 931 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 932 struct intel_encoder *intel_encoder = &crt->base; 933 intel_wakeref_t wakeref; 934 struct i2c_adapter *i2c; 935 int ret; 936 937 wakeref = intel_display_power_get(dev_priv, 938 intel_encoder->power_domain); 939 940 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin); 941 ret = intel_crt_ddc_get_modes(connector, i2c); 942 if (ret || !IS_G4X(dev_priv)) 943 goto out; 944 945 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 946 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); 947 ret = intel_crt_ddc_get_modes(connector, i2c); 948 949 out: 950 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 951 952 return ret; 953 } 954 955 void intel_crt_reset(struct drm_encoder *encoder) 956 { 957 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 958 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); 959 960 if (DISPLAY_VER(dev_priv) >= 5) { 961 u32 adpa; 962 963 adpa = intel_de_read(dev_priv, crt->adpa_reg); 964 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 965 adpa |= ADPA_HOTPLUG_BITS; 966 intel_de_write(dev_priv, crt->adpa_reg, adpa); 967 intel_de_posting_read(dev_priv, crt->adpa_reg); 968 969 drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa); 970 crt->force_hotplug_required = true; 971 } 972 973 } 974 975 /* 976 * Routines for controlling stuff on the analog port 977 */ 978 979 static const struct drm_connector_funcs intel_crt_connector_funcs = { 980 .fill_modes = drm_helper_probe_single_connector_modes, 981 .late_register = intel_connector_register, 982 .early_unregister = intel_connector_unregister, 983 .destroy = intel_connector_destroy, 984 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 985 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 986 }; 987 988 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 989 .detect_ctx = intel_crt_detect, 990 .mode_valid = intel_crt_mode_valid, 991 .get_modes = intel_crt_get_modes, 992 }; 993 994 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 995 .reset = intel_crt_reset, 996 .destroy = intel_encoder_destroy, 997 }; 998 999 void intel_crt_init(struct drm_i915_private *dev_priv) 1000 { 1001 struct drm_connector *connector; 1002 struct intel_crt *crt; 1003 struct intel_connector *intel_connector; 1004 i915_reg_t adpa_reg; 1005 u32 adpa; 1006 1007 if (HAS_PCH_SPLIT(dev_priv)) 1008 adpa_reg = PCH_ADPA; 1009 else if (IS_VALLEYVIEW(dev_priv)) 1010 adpa_reg = VLV_ADPA; 1011 else 1012 adpa_reg = ADPA; 1013 1014 adpa = intel_de_read(dev_priv, adpa_reg); 1015 if ((adpa & ADPA_DAC_ENABLE) == 0) { 1016 /* 1017 * On some machines (some IVB at least) CRT can be 1018 * fused off, but there's no known fuse bit to 1019 * indicate that. On these machine the ADPA register 1020 * works normally, except the DAC enable bit won't 1021 * take. So the only way to tell is attempt to enable 1022 * it and see what happens. 1023 */ 1024 intel_de_write(dev_priv, adpa_reg, 1025 adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 1026 if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0) 1027 return; 1028 intel_de_write(dev_priv, adpa_reg, adpa); 1029 } 1030 1031 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 1032 if (!crt) 1033 return; 1034 1035 intel_connector = intel_connector_alloc(); 1036 if (!intel_connector) { 1037 kfree(crt); 1038 return; 1039 } 1040 1041 connector = &intel_connector->base; 1042 crt->connector = intel_connector; 1043 drm_connector_init(&dev_priv->drm, &intel_connector->base, 1044 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 1045 1046 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, 1047 DRM_MODE_ENCODER_DAC, "CRT"); 1048 1049 intel_connector_attach_encoder(intel_connector, &crt->base); 1050 1051 crt->base.type = INTEL_OUTPUT_ANALOG; 1052 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 1053 if (IS_I830(dev_priv)) 1054 crt->base.pipe_mask = BIT(PIPE_A); 1055 else 1056 crt->base.pipe_mask = ~0; 1057 1058 if (DISPLAY_VER(dev_priv) == 2) 1059 connector->interlace_allowed = 0; 1060 else 1061 connector->interlace_allowed = 1; 1062 connector->doublescan_allowed = 0; 1063 1064 crt->adpa_reg = adpa_reg; 1065 1066 crt->base.power_domain = POWER_DOMAIN_PORT_CRT; 1067 1068 if (I915_HAS_HOTPLUG(dev_priv) && 1069 !dmi_check_system(intel_spurious_crt_detect)) { 1070 crt->base.hpd_pin = HPD_CRT; 1071 crt->base.hotplug = intel_encoder_hotplug; 1072 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 1073 } else { 1074 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1075 } 1076 1077 if (HAS_DDI(dev_priv)) { 1078 crt->base.port = PORT_E; 1079 crt->base.get_config = hsw_crt_get_config; 1080 crt->base.get_hw_state = intel_ddi_get_hw_state; 1081 crt->base.compute_config = hsw_crt_compute_config; 1082 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; 1083 crt->base.pre_enable = hsw_pre_enable_crt; 1084 crt->base.enable = hsw_enable_crt; 1085 crt->base.disable = hsw_disable_crt; 1086 crt->base.post_disable = hsw_post_disable_crt; 1087 crt->base.enable_clock = hsw_ddi_enable_clock; 1088 crt->base.disable_clock = hsw_ddi_disable_clock; 1089 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled; 1090 1091 intel_ddi_buf_trans_init(&crt->base); 1092 } else { 1093 if (HAS_PCH_SPLIT(dev_priv)) { 1094 crt->base.compute_config = pch_crt_compute_config; 1095 crt->base.disable = pch_disable_crt; 1096 crt->base.post_disable = pch_post_disable_crt; 1097 } else { 1098 crt->base.compute_config = intel_crt_compute_config; 1099 crt->base.disable = intel_disable_crt; 1100 } 1101 crt->base.port = PORT_NONE; 1102 crt->base.get_config = intel_crt_get_config; 1103 crt->base.get_hw_state = intel_crt_get_hw_state; 1104 crt->base.enable = intel_enable_crt; 1105 } 1106 intel_connector->get_hw_state = intel_connector_get_hw_state; 1107 1108 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 1109 1110 /* 1111 * TODO: find a proper way to discover whether we need to set the the 1112 * polarity and link reversal bits or not, instead of relying on the 1113 * BIOS. 1114 */ 1115 if (HAS_PCH_LPT(dev_priv)) { 1116 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 1117 FDI_RX_LINK_REVERSAL_OVERRIDE; 1118 1119 dev_priv->display.fdi.rx_config = intel_de_read(dev_priv, 1120 FDI_RX_CTL(PIPE_A)) & fdi_config; 1121 } 1122 1123 intel_crt_reset(&crt->base.base); 1124 } 1125