1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 30 #define drm_i915_private inteldrm_softc 31 32 enum link_m_n_set; 33 struct dpll; 34 struct drm_connector; 35 struct drm_device; 36 struct drm_display_mode; 37 struct drm_encoder; 38 struct drm_file; 39 struct drm_format_info; 40 struct drm_framebuffer; 41 struct drm_i915_error_state_buf; 42 struct drm_i915_gem_object; 43 struct drm_i915_private; 44 struct drm_mode_fb_cmd2; 45 struct drm_modeset_acquire_ctx; 46 struct drm_plane; 47 struct drm_plane_state; 48 struct i915_ggtt_view; 49 struct intel_atomic_state; 50 struct intel_crtc; 51 struct intel_crtc_state; 52 struct intel_crtc_state; 53 struct intel_digital_port; 54 struct intel_dp; 55 struct intel_encoder; 56 struct intel_load_detect_pipe; 57 struct intel_plane; 58 struct intel_plane_state; 59 struct intel_remapped_info; 60 struct intel_rotation_info; 61 62 enum i915_gpio { 63 GPIOA, 64 GPIOB, 65 GPIOC, 66 GPIOD, 67 GPIOE, 68 GPIOF, 69 GPIOG, 70 GPIOH, 71 __GPIOI_UNUSED, 72 GPIOJ, 73 GPIOK, 74 GPIOL, 75 GPIOM, 76 GPION, 77 GPIOO, 78 }; 79 80 /* 81 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 82 * rest have consecutive values and match the enum values of transcoders 83 * with a 1:1 transcoder -> pipe mapping. 84 */ 85 enum pipe { 86 INVALID_PIPE = -1, 87 88 PIPE_A = 0, 89 PIPE_B, 90 PIPE_C, 91 PIPE_D, 92 _PIPE_EDP, 93 94 I915_MAX_PIPES = _PIPE_EDP 95 }; 96 97 #define pipe_name(p) ((p) + 'A') 98 99 enum transcoder { 100 INVALID_TRANSCODER = -1, 101 /* 102 * The following transcoders have a 1:1 transcoder -> pipe mapping, 103 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 104 * rest have consecutive values and match the enum values of the pipes 105 * they map to. 106 */ 107 TRANSCODER_A = PIPE_A, 108 TRANSCODER_B = PIPE_B, 109 TRANSCODER_C = PIPE_C, 110 TRANSCODER_D = PIPE_D, 111 112 /* 113 * The following transcoders can map to any pipe, their enum value 114 * doesn't need to stay fixed. 115 */ 116 TRANSCODER_EDP, 117 TRANSCODER_DSI_0, 118 TRANSCODER_DSI_1, 119 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 120 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 121 122 I915_MAX_TRANSCODERS 123 }; 124 125 static inline const char *transcoder_name(enum transcoder transcoder) 126 { 127 switch (transcoder) { 128 case TRANSCODER_A: 129 return "A"; 130 case TRANSCODER_B: 131 return "B"; 132 case TRANSCODER_C: 133 return "C"; 134 case TRANSCODER_D: 135 return "D"; 136 case TRANSCODER_EDP: 137 return "EDP"; 138 case TRANSCODER_DSI_A: 139 return "DSI A"; 140 case TRANSCODER_DSI_C: 141 return "DSI C"; 142 default: 143 return "<invalid>"; 144 } 145 } 146 147 static inline bool transcoder_is_dsi(enum transcoder transcoder) 148 { 149 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 150 } 151 152 /* 153 * Global legacy plane identifier. Valid only for primary/sprite 154 * planes on pre-g4x, and only for primary planes on g4x-bdw. 155 */ 156 enum i9xx_plane_id { 157 PLANE_A, 158 PLANE_B, 159 PLANE_C, 160 }; 161 162 #define plane_name(p) ((p) + 'A') 163 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 164 165 /* 166 * Per-pipe plane identifier. 167 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 168 * number of planes per CRTC. Not all platforms really have this many planes, 169 * which means some arrays of size I915_MAX_PLANES may have unused entries 170 * between the topmost sprite plane and the cursor plane. 171 * 172 * This is expected to be passed to various register macros 173 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 174 */ 175 enum plane_id { 176 PLANE_PRIMARY, 177 PLANE_SPRITE0, 178 PLANE_SPRITE1, 179 PLANE_SPRITE2, 180 PLANE_SPRITE3, 181 PLANE_SPRITE4, 182 PLANE_SPRITE5, 183 PLANE_CURSOR, 184 185 I915_MAX_PLANES, 186 }; 187 188 #define for_each_plane_id_on_crtc(__crtc, __p) \ 189 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 190 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 191 192 #define for_each_dbuf_slice_in_mask(__slice, __mask) \ 193 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \ 194 for_each_if((BIT(__slice)) & (__mask)) 195 196 #define for_each_dbuf_slice(__slice) \ 197 for_each_dbuf_slice_in_mask(__slice, BIT(I915_MAX_DBUF_SLICES) - 1) 198 199 enum port { 200 PORT_NONE = -1, 201 202 PORT_A = 0, 203 PORT_B, 204 PORT_C, 205 PORT_D, 206 PORT_E, 207 PORT_F, 208 PORT_G, 209 PORT_H, 210 PORT_I, 211 212 I915_MAX_PORTS 213 }; 214 215 #define port_name(p) ((p) + 'A') 216 217 /* 218 * Ports identifier referenced from other drivers. 219 * Expected to remain stable over time 220 */ 221 static inline const char *port_identifier(enum port port) 222 { 223 switch (port) { 224 case PORT_A: 225 return "Port A"; 226 case PORT_B: 227 return "Port B"; 228 case PORT_C: 229 return "Port C"; 230 case PORT_D: 231 return "Port D"; 232 case PORT_E: 233 return "Port E"; 234 case PORT_F: 235 return "Port F"; 236 case PORT_G: 237 return "Port G"; 238 case PORT_H: 239 return "Port H"; 240 case PORT_I: 241 return "Port I"; 242 default: 243 return "<invalid>"; 244 } 245 } 246 247 enum tc_port { 248 PORT_TC_NONE = -1, 249 250 PORT_TC1 = 0, 251 PORT_TC2, 252 PORT_TC3, 253 PORT_TC4, 254 PORT_TC5, 255 PORT_TC6, 256 257 I915_MAX_TC_PORTS 258 }; 259 260 enum tc_port_mode { 261 TC_PORT_TBT_ALT, 262 TC_PORT_DP_ALT, 263 TC_PORT_LEGACY, 264 }; 265 266 enum dpio_channel { 267 DPIO_CH0, 268 DPIO_CH1 269 }; 270 271 enum dpio_phy { 272 DPIO_PHY0, 273 DPIO_PHY1, 274 DPIO_PHY2, 275 }; 276 277 enum aux_ch { 278 AUX_CH_A, 279 AUX_CH_B, 280 AUX_CH_C, 281 AUX_CH_D, 282 AUX_CH_E, /* ICL+ */ 283 AUX_CH_F, 284 AUX_CH_G, 285 AUX_CH_H, 286 AUX_CH_I, 287 }; 288 289 #define aux_ch_name(a) ((a) + 'A') 290 291 /* Used by dp and fdi links */ 292 struct intel_link_m_n { 293 u32 tu; 294 u32 gmch_m; 295 u32 gmch_n; 296 u32 link_m; 297 u32 link_n; 298 }; 299 300 enum phy { 301 PHY_NONE = -1, 302 303 PHY_A = 0, 304 PHY_B, 305 PHY_C, 306 PHY_D, 307 PHY_E, 308 PHY_F, 309 PHY_G, 310 PHY_H, 311 PHY_I, 312 313 I915_MAX_PHYS 314 }; 315 316 #define phy_name(a) ((a) + 'A') 317 318 enum phy_fia { 319 FIA1, 320 FIA2, 321 FIA3, 322 }; 323 324 #define for_each_pipe(__dev_priv, __p) \ 325 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ 326 for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p)) 327 328 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 329 for_each_pipe(__dev_priv, __p) \ 330 for_each_if((__mask) & BIT(__p)) 331 332 #define for_each_cpu_transcoder(__dev_priv, __t) \ 333 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 334 for_each_if (INTEL_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t)) 335 336 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 337 for_each_cpu_transcoder(__dev_priv, __t) \ 338 for_each_if ((__mask) & BIT(__t)) 339 340 #define for_each_universal_plane(__dev_priv, __pipe, __p) \ 341 for ((__p) = 0; \ 342 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ 343 (__p)++) 344 345 #define for_each_sprite(__dev_priv, __p, __s) \ 346 for ((__s) = 0; \ 347 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 348 (__s)++) 349 350 #define for_each_port(__port) \ 351 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 352 353 #define for_each_port_masked(__port, __ports_mask) \ 354 for_each_port(__port) \ 355 for_each_if((__ports_mask) & BIT(__port)) 356 357 #define for_each_phy_masked(__phy, __phys_mask) \ 358 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 359 for_each_if((__phys_mask) & BIT(__phy)) 360 361 #define for_each_crtc(dev, crtc) \ 362 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 363 364 #define for_each_intel_plane(dev, intel_plane) \ 365 list_for_each_entry(intel_plane, \ 366 &(dev)->mode_config.plane_list, \ 367 base.head) 368 369 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 370 list_for_each_entry(intel_plane, \ 371 &(dev)->mode_config.plane_list, \ 372 base.head) \ 373 for_each_if((plane_mask) & \ 374 drm_plane_mask(&intel_plane->base)) 375 376 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 377 list_for_each_entry(intel_plane, \ 378 &(dev)->mode_config.plane_list, \ 379 base.head) \ 380 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 381 382 #define for_each_intel_crtc(dev, intel_crtc) \ 383 list_for_each_entry(intel_crtc, \ 384 &(dev)->mode_config.crtc_list, \ 385 base.head) 386 387 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ 388 list_for_each_entry(intel_crtc, \ 389 &(dev)->mode_config.crtc_list, \ 390 base.head) \ 391 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base)) 392 393 #define for_each_intel_encoder(dev, intel_encoder) \ 394 list_for_each_entry(intel_encoder, \ 395 &(dev)->mode_config.encoder_list, \ 396 base.head) 397 398 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 399 list_for_each_entry(intel_encoder, \ 400 &(dev)->mode_config.encoder_list, \ 401 base.head) \ 402 for_each_if((encoder_mask) & \ 403 drm_encoder_mask(&intel_encoder->base)) 404 405 #define for_each_intel_dp(dev, intel_encoder) \ 406 for_each_intel_encoder(dev, intel_encoder) \ 407 for_each_if(intel_encoder_is_dp(intel_encoder)) 408 409 #define for_each_intel_connector_iter(intel_connector, iter) \ 410 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 411 412 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 413 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 414 for_each_if((intel_encoder)->base.crtc == (__crtc)) 415 416 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 417 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 418 for_each_if((intel_connector)->base.encoder == (__encoder)) 419 420 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 421 for ((__i) = 0; \ 422 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 423 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 424 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 425 (__i)++) \ 426 for_each_if(plane) 427 428 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 429 for ((__i) = 0; \ 430 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 431 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 432 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 433 (__i)++) \ 434 for_each_if(plane) 435 436 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 437 for ((__i) = 0; \ 438 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 439 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 440 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 441 (__i)++) \ 442 for_each_if(crtc) 443 444 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 445 for ((__i) = 0; \ 446 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 447 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 448 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 449 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 450 (__i)++) \ 451 for_each_if(plane) 452 453 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 454 for ((__i) = 0; \ 455 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 456 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 457 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 458 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 459 (__i)++) \ 460 for_each_if(crtc) 461 462 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 463 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 464 (__i) >= 0 && \ 465 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 466 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 467 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 468 (__i)--) \ 469 for_each_if(crtc) 470 471 #define intel_atomic_crtc_state_for_each_plane_state( \ 472 plane, plane_state, \ 473 crtc_state) \ 474 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 475 ((crtc_state)->uapi.plane_mask)) \ 476 for_each_if ((plane_state = \ 477 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) 478 479 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 480 for ((__i) = 0; \ 481 (__i) < (__state)->base.num_connector; \ 482 (__i)++) \ 483 for_each_if ((__state)->base.connectors[__i].ptr && \ 484 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 485 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 486 487 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 488 u8 active_pipes); 489 void intel_link_compute_m_n(u16 bpp, int nlanes, 490 int pixel_clock, int link_clock, 491 struct intel_link_m_n *m_n, 492 bool constant_n, bool fec_enable); 493 bool is_ccs_modifier(u64 modifier); 494 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane); 495 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); 496 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 497 u32 pixel_format, u64 modifier); 498 bool intel_plane_can_remap(const struct intel_plane_state *plane_state); 499 enum drm_mode_status 500 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 501 const struct drm_display_mode *mode); 502 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 503 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 504 505 void intel_plane_destroy(struct drm_plane *plane); 506 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state); 507 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state); 508 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 509 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 510 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); 511 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 512 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 513 const char *name, u32 reg, int ref_freq); 514 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 515 const char *name, u32 reg); 516 void lpt_pch_enable(const struct intel_crtc_state *crtc_state); 517 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); 518 void lpt_disable_iclkip(struct drm_i915_private *dev_priv); 519 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 520 unsigned int intel_fb_xy_to_linear(int x, int y, 521 const struct intel_plane_state *state, 522 int plane); 523 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, 524 int color_plane, unsigned int height); 525 void intel_add_fb_offsets(int *x, int *y, 526 const struct intel_plane_state *state, int plane); 527 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 528 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); 529 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 530 int intel_display_suspend(struct drm_device *dev); 531 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); 532 void intel_encoder_destroy(struct drm_encoder *encoder); 533 struct drm_display_mode * 534 intel_encoder_current_mode(struct intel_encoder *encoder); 535 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); 536 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); 537 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, 538 enum port port); 539 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 540 struct drm_file *file_priv); 541 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); 542 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state); 543 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state); 544 545 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 546 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 547 struct intel_digital_port *dig_port, 548 unsigned int expected_mask); 549 int intel_get_load_detect_pipe(struct drm_connector *connector, 550 struct intel_load_detect_pipe *old, 551 struct drm_modeset_acquire_ctx *ctx); 552 void intel_release_load_detect_pipe(struct drm_connector *connector, 553 struct intel_load_detect_pipe *old, 554 struct drm_modeset_acquire_ctx *ctx); 555 struct i915_vma * 556 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, 557 const struct i915_ggtt_view *view, 558 bool uses_fence, 559 unsigned long *out_flags); 560 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags); 561 struct drm_framebuffer * 562 intel_framebuffer_create(struct drm_i915_gem_object *obj, 563 struct drm_mode_fb_cmd2 *mode_cmd); 564 int intel_prepare_plane_fb(struct drm_plane *plane, 565 struct drm_plane_state *new_state); 566 void intel_cleanup_plane_fb(struct drm_plane *plane, 567 struct drm_plane_state *old_state); 568 569 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 570 enum pipe pipe); 571 572 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 573 const struct dpll *dpll); 574 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); 575 int lpt_get_iclkip(struct drm_i915_private *dev_priv); 576 bool intel_fuzzy_clock_check(int clock1, int clock2); 577 578 void intel_prepare_reset(struct drm_i915_private *dev_priv); 579 void intel_finish_reset(struct drm_i915_private *dev_priv); 580 void intel_dp_get_m_n(struct intel_crtc *crtc, 581 struct intel_crtc_state *pipe_config); 582 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, 583 enum link_m_n_set m_n); 584 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 585 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 586 struct dpll *best_clock); 587 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); 588 589 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); 590 void hsw_enable_ips(const struct intel_crtc_state *crtc_state); 591 void hsw_disable_ips(const struct intel_crtc_state *crtc_state); 592 enum intel_display_power_domain intel_port_to_power_domain(enum port port); 593 enum intel_display_power_domain 594 intel_aux_power_domain(struct intel_digital_port *dig_port); 595 enum intel_display_power_domain 596 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch); 597 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 598 struct intel_crtc_state *pipe_config); 599 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 600 struct intel_crtc_state *crtc_state); 601 602 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center); 603 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); 604 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); 605 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, 606 const struct intel_plane_state *plane_state); 607 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state); 608 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 609 const struct intel_plane_state *plane_state); 610 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state); 611 u32 skl_plane_stride(const struct intel_plane_state *plane_state, 612 int plane); 613 int skl_check_plane_surface(struct intel_plane_state *plane_state); 614 int i9xx_check_plane_surface(struct intel_plane_state *plane_state); 615 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); 616 unsigned int i9xx_plane_max_stride(struct intel_plane *plane, 617 u32 pixel_format, u64 modifier, 618 unsigned int rotation); 619 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); 620 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state); 621 622 struct intel_display_error_state * 623 intel_display_capture_error_state(struct drm_i915_private *dev_priv); 624 void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 625 struct intel_display_error_state *error); 626 627 bool 628 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, 629 uint64_t modifier); 630 631 /* modesetting */ 632 void intel_modeset_init_hw(struct drm_i915_private *i915); 633 int intel_modeset_init_noirq(struct drm_i915_private *i915); 634 int intel_modeset_init_nogem(struct drm_i915_private *i915); 635 int intel_modeset_init(struct drm_i915_private *i915); 636 void intel_modeset_driver_remove(struct drm_i915_private *i915); 637 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915); 638 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915); 639 void intel_display_resume(struct drm_device *dev); 640 void intel_init_pch_refclk(struct drm_i915_private *dev_priv); 641 642 /* modesetting asserts */ 643 void assert_panel_unlocked(struct drm_i915_private *dev_priv, 644 enum pipe pipe); 645 void assert_pll(struct drm_i915_private *dev_priv, 646 enum pipe pipe, bool state); 647 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 648 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 649 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); 650 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) 651 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) 652 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 653 enum pipe pipe, bool state); 654 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) 655 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) 656 void assert_pipe(struct drm_i915_private *dev_priv, 657 enum transcoder cpu_transcoder, bool state); 658 #define assert_pipe_enabled(d, t) assert_pipe(d, t, true) 659 #define assert_pipe_disabled(d, t) assert_pipe(d, t, false) 660 661 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 662 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 663 * which may not necessarily be a user visible problem. This will either 664 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 665 * enable distros and users to tailor their preferred amount of i915 abrt 666 * spam. 667 */ 668 #define I915_STATE_WARN(condition, format...) ({ \ 669 int __ret_warn_on = !!(condition); \ 670 if (unlikely(__ret_warn_on)) \ 671 if (!WARN(i915_modparams.verbose_state_checks, format)) \ 672 DRM_ERROR(format); \ 673 unlikely(__ret_warn_on); \ 674 }) 675 676 #define I915_STATE_WARN_ON(x) \ 677 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 678 679 #endif 680