1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_IRQ_H__ 7 #define __INTEL_DISPLAY_IRQ_H__ 8 9 #include <linux/types.h> 10 11 #include "intel_display_limits.h" 12 13 enum pipe; 14 #define drm_i915_private inteldrm_softc 15 struct drm_i915_private; 16 struct drm_crtc; 17 18 void valleyview_enable_display_irqs(struct drm_i915_private *i915); 19 void valleyview_disable_display_irqs(struct drm_i915_private *i915); 20 21 void ilk_update_display_irq(struct drm_i915_private *i915, 22 u32 interrupt_mask, u32 enabled_irq_mask); 23 void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits); 24 void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits); 25 26 void bdw_update_port_irq(struct drm_i915_private *i915, u32 interrupt_mask, u32 enabled_irq_mask); 27 void bdw_enable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits); 28 void bdw_disable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits); 29 30 void ibx_display_interrupt_update(struct drm_i915_private *i915, 31 u32 interrupt_mask, u32 enabled_irq_mask); 32 void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits); 33 void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits); 34 35 void gen8_irq_power_well_post_enable(struct drm_i915_private *i915, u8 pipe_mask); 36 void gen8_irq_power_well_pre_disable(struct drm_i915_private *i915, u8 pipe_mask); 37 u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *i915); 38 39 int i8xx_enable_vblank(struct drm_crtc *crtc); 40 int i915gm_enable_vblank(struct drm_crtc *crtc); 41 int i965_enable_vblank(struct drm_crtc *crtc); 42 int ilk_enable_vblank(struct drm_crtc *crtc); 43 int bdw_enable_vblank(struct drm_crtc *crtc); 44 void i8xx_disable_vblank(struct drm_crtc *crtc); 45 void i915gm_disable_vblank(struct drm_crtc *crtc); 46 void i965_disable_vblank(struct drm_crtc *crtc); 47 void ilk_disable_vblank(struct drm_crtc *crtc); 48 void bdw_disable_vblank(struct drm_crtc *crtc); 49 50 void ivb_display_irq_handler(struct drm_i915_private *i915, u32 de_iir); 51 void ilk_display_irq_handler(struct drm_i915_private *i915, u32 de_iir); 52 void gen8_de_irq_handler(struct drm_i915_private *i915, u32 master_ctl); 53 void gen11_display_irq_handler(struct drm_i915_private *i915); 54 55 u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl); 56 void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir); 57 58 void vlv_display_irq_reset(struct drm_i915_private *i915); 59 void gen8_display_irq_reset(struct drm_i915_private *i915); 60 void gen11_display_irq_reset(struct drm_i915_private *i915); 61 62 void vlv_display_irq_postinstall(struct drm_i915_private *i915); 63 void ilk_de_irq_postinstall(struct drm_i915_private *i915); 64 void gen8_de_irq_postinstall(struct drm_i915_private *i915); 65 void gen11_de_irq_postinstall(struct drm_i915_private *i915); 66 void dg1_de_irq_postinstall(struct drm_i915_private *i915); 67 68 u32 i915_pipestat_enable_mask(struct drm_i915_private *i915, enum pipe pipe); 69 void i915_enable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask); 70 void i915_disable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask); 71 void i915_enable_asle_pipestat(struct drm_i915_private *i915); 72 void i9xx_pipestat_irq_reset(struct drm_i915_private *i915); 73 74 void i9xx_pipestat_irq_ack(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 75 76 void i915_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 77 void i965_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 78 void valleyview_pipestat_irq_handler(struct drm_i915_private *i915, u32 pipe_stats[I915_MAX_PIPES]); 79 void i8xx_pipestat_irq_handler(struct drm_i915_private *i915, u16 iir, u32 pipe_stats[I915_MAX_PIPES]); 80 81 void intel_display_irq_init(struct drm_i915_private *i915); 82 83 #endif /* __INTEL_DISPLAY_IRQ_H__ */ 84