1*f005ef32Sjsg // SPDX-License-Identifier: MIT
2*f005ef32Sjsg /*
3*f005ef32Sjsg * Copyright © 2023 Intel Corporation
4*f005ef32Sjsg */
5*f005ef32Sjsg
6*f005ef32Sjsg #include <drm/drm_crtc.h>
7*f005ef32Sjsg #include <drm/drm_vblank.h>
8*f005ef32Sjsg
9*f005ef32Sjsg #include "gt/intel_rps.h"
10*f005ef32Sjsg #include "i915_drv.h"
11*f005ef32Sjsg #include "intel_display_rps.h"
12*f005ef32Sjsg #include "intel_display_types.h"
13*f005ef32Sjsg
14*f005ef32Sjsg struct wait_rps_boost {
15*f005ef32Sjsg struct wait_queue_entry wait;
16*f005ef32Sjsg
17*f005ef32Sjsg struct drm_crtc *crtc;
18*f005ef32Sjsg struct i915_request *request;
19*f005ef32Sjsg };
20*f005ef32Sjsg
do_rps_boost(struct wait_queue_entry * _wait,unsigned mode,int sync,void * key)21*f005ef32Sjsg static int do_rps_boost(struct wait_queue_entry *_wait,
22*f005ef32Sjsg unsigned mode, int sync, void *key)
23*f005ef32Sjsg {
24*f005ef32Sjsg struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
25*f005ef32Sjsg struct i915_request *rq = wait->request;
26*f005ef32Sjsg
27*f005ef32Sjsg /*
28*f005ef32Sjsg * If we missed the vblank, but the request is already running it
29*f005ef32Sjsg * is reasonable to assume that it will complete before the next
30*f005ef32Sjsg * vblank without our intervention, so leave RPS alone.
31*f005ef32Sjsg */
32*f005ef32Sjsg if (!i915_request_started(rq))
33*f005ef32Sjsg intel_rps_boost(rq);
34*f005ef32Sjsg i915_request_put(rq);
35*f005ef32Sjsg
36*f005ef32Sjsg drm_crtc_vblank_put(wait->crtc);
37*f005ef32Sjsg
38*f005ef32Sjsg list_del(&wait->wait.entry);
39*f005ef32Sjsg kfree(wait);
40*f005ef32Sjsg return 1;
41*f005ef32Sjsg }
42*f005ef32Sjsg
intel_display_rps_boost_after_vblank(struct drm_crtc * crtc,struct dma_fence * fence)43*f005ef32Sjsg void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc,
44*f005ef32Sjsg struct dma_fence *fence)
45*f005ef32Sjsg {
46*f005ef32Sjsg struct wait_rps_boost *wait;
47*f005ef32Sjsg
48*f005ef32Sjsg if (!dma_fence_is_i915(fence))
49*f005ef32Sjsg return;
50*f005ef32Sjsg
51*f005ef32Sjsg if (DISPLAY_VER(to_i915(crtc->dev)) < 6)
52*f005ef32Sjsg return;
53*f005ef32Sjsg
54*f005ef32Sjsg if (drm_crtc_vblank_get(crtc))
55*f005ef32Sjsg return;
56*f005ef32Sjsg
57*f005ef32Sjsg wait = kmalloc(sizeof(*wait), GFP_KERNEL);
58*f005ef32Sjsg if (!wait) {
59*f005ef32Sjsg drm_crtc_vblank_put(crtc);
60*f005ef32Sjsg return;
61*f005ef32Sjsg }
62*f005ef32Sjsg
63*f005ef32Sjsg wait->request = to_request(dma_fence_get(fence));
64*f005ef32Sjsg wait->crtc = crtc;
65*f005ef32Sjsg
66*f005ef32Sjsg wait->wait.func = do_rps_boost;
67*f005ef32Sjsg wait->wait.flags = 0;
68*f005ef32Sjsg
69*f005ef32Sjsg add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
70*f005ef32Sjsg }
71*f005ef32Sjsg
intel_display_rps_mark_interactive(struct drm_i915_private * i915,struct intel_atomic_state * state,bool interactive)72*f005ef32Sjsg void intel_display_rps_mark_interactive(struct drm_i915_private *i915,
73*f005ef32Sjsg struct intel_atomic_state *state,
74*f005ef32Sjsg bool interactive)
75*f005ef32Sjsg {
76*f005ef32Sjsg if (state->rps_interactive == interactive)
77*f005ef32Sjsg return;
78*f005ef32Sjsg
79*f005ef32Sjsg intel_rps_mark_interactive(&to_gt(i915)->rps, interactive);
80*f005ef32Sjsg state->rps_interactive = interactive;
81*f005ef32Sjsg }
82