1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Shobhit Kumar <shobhit.kumar@intel.com> 24 * 25 */ 26 27 #include <linux/gpio/consumer.h> 28 #ifdef notyet 29 #include <linux/gpio/machine.h> 30 #include <linux/mfd/intel_soc_pmic.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pinctrl/machine.h> 33 #endif 34 #include <linux/slab.h> 35 36 #include <asm/intel-mid.h> 37 #include <asm/unaligned.h> 38 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_edid.h> 41 42 #include <video/mipi_display.h> 43 44 #include "i915_drv.h" 45 #include "intel_display_types.h" 46 #include "intel_dsi.h" 47 #include "intel_sideband.h" 48 49 #define MIPI_TRANSFER_MODE_SHIFT 0 50 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 51 #define MIPI_PORT_SHIFT 3 52 53 /* base offsets for gpio pads */ 54 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 55 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 56 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 57 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 58 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 59 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 60 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 61 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 62 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 63 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 64 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 65 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 66 67 #define VLV_GPIO_PCONF0(base_offset) (base_offset) 68 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) 69 70 struct gpio_map { 71 u16 base_offset; 72 bool init; 73 }; 74 75 static struct gpio_map vlv_gpio_table[] = { 76 { VLV_GPIO_NC_0_HV_DDI0_HPD }, 77 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, 78 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, 79 { VLV_GPIO_NC_3_PANEL0_VDDEN }, 80 { VLV_GPIO_NC_4_PANEL0_BKLTEN }, 81 { VLV_GPIO_NC_5_PANEL0_BKLTCTL }, 82 { VLV_GPIO_NC_6_HV_DDI1_HPD }, 83 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA }, 84 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL }, 85 { VLV_GPIO_NC_9_PANEL1_VDDEN }, 86 { VLV_GPIO_NC_10_PANEL1_BKLTEN }, 87 { VLV_GPIO_NC_11_PANEL1_BKLTCTL }, 88 }; 89 90 struct i2c_adapter_lookup { 91 u16 slave_addr; 92 struct intel_dsi *intel_dsi; 93 #ifdef notyet 94 acpi_handle dev_handle; 95 #endif 96 }; 97 98 #define CHV_GPIO_IDX_START_N 0 99 #define CHV_GPIO_IDX_START_E 73 100 #define CHV_GPIO_IDX_START_SW 100 101 #define CHV_GPIO_IDX_START_SE 198 102 103 #define CHV_VBT_MAX_PINS_PER_FMLY 15 104 105 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8) 106 #define CHV_GPIO_GPIOEN (1 << 15) 107 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8) 108 #define CHV_GPIO_GPIOCFG_GPO (1 << 8) 109 #define CHV_GPIO_GPIOCFG_GPI (2 << 8) 110 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8) 111 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1) 112 113 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4) 114 #define CHV_GPIO_CFGLOCK (1 << 31) 115 116 /* ICL DSI Display GPIO Pins */ 117 #define ICL_GPIO_DDSP_HPD_A 0 118 #define ICL_GPIO_L_VDDEN_1 1 119 #define ICL_GPIO_L_BKLTEN_1 2 120 #define ICL_GPIO_DDPA_CTRLCLK_1 3 121 #define ICL_GPIO_DDPA_CTRLDATA_1 4 122 #define ICL_GPIO_DDSP_HPD_B 5 123 #define ICL_GPIO_L_VDDEN_2 6 124 #define ICL_GPIO_L_BKLTEN_2 7 125 #define ICL_GPIO_DDPA_CTRLCLK_2 8 126 #define ICL_GPIO_DDPA_CTRLDATA_2 9 127 128 static inline enum port intel_dsi_seq_port_to_port(u8 port) 129 { 130 return port ? PORT_C : PORT_A; 131 } 132 133 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 134 const u8 *data) 135 { 136 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 137 struct mipi_dsi_device *dsi_device; 138 u8 type, flags, seq_port; 139 u16 len; 140 enum port port; 141 142 drm_dbg_kms(&dev_priv->drm, "\n"); 143 144 flags = *data++; 145 type = *data++; 146 147 len = *((u16 *) data); 148 data += 2; 149 150 seq_port = (flags >> MIPI_PORT_SHIFT) & 3; 151 152 /* For DSI single link on Port A & C, the seq_port value which is 153 * parsed from Sequence Block#53 of VBT has been set to 0 154 * Now, read/write of packets for the DSI single link on Port A and 155 * Port C will based on the DVO port from VBT block 2. 156 */ 157 if (intel_dsi->ports == (1 << PORT_C)) 158 port = PORT_C; 159 else 160 port = intel_dsi_seq_port_to_port(seq_port); 161 162 dsi_device = intel_dsi->dsi_hosts[port]->device; 163 if (!dsi_device) { 164 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n", 165 port_name(port)); 166 goto out; 167 } 168 169 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) 170 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; 171 else 172 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; 173 174 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; 175 176 switch (type) { 177 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 178 mipi_dsi_generic_write(dsi_device, NULL, 0); 179 break; 180 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 181 mipi_dsi_generic_write(dsi_device, data, 1); 182 break; 183 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 184 mipi_dsi_generic_write(dsi_device, data, 2); 185 break; 186 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 187 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 188 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 189 drm_dbg(&dev_priv->drm, 190 "Generic Read not yet implemented or used\n"); 191 break; 192 case MIPI_DSI_GENERIC_LONG_WRITE: 193 mipi_dsi_generic_write(dsi_device, data, len); 194 break; 195 case MIPI_DSI_DCS_SHORT_WRITE: 196 mipi_dsi_dcs_write_buffer(dsi_device, data, 1); 197 break; 198 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 199 mipi_dsi_dcs_write_buffer(dsi_device, data, 2); 200 break; 201 case MIPI_DSI_DCS_READ: 202 drm_dbg(&dev_priv->drm, 203 "DCS Read not yet implemented or used\n"); 204 break; 205 case MIPI_DSI_DCS_LONG_WRITE: 206 mipi_dsi_dcs_write_buffer(dsi_device, data, len); 207 break; 208 } 209 210 if (INTEL_GEN(dev_priv) < 11) 211 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 212 213 out: 214 data += len; 215 216 return data; 217 } 218 219 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) 220 { 221 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 222 u32 delay = *((const u32 *) data); 223 224 drm_dbg_kms(&i915->drm, "\n"); 225 226 usleep_range(delay, delay + 10); 227 data += 4; 228 229 return data; 230 } 231 232 static void vlv_exec_gpio(struct drm_i915_private *dev_priv, 233 u8 gpio_source, u8 gpio_index, bool value) 234 { 235 struct gpio_map *map; 236 u16 pconf0, padval; 237 u32 tmp; 238 u8 port; 239 240 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { 241 drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n", 242 gpio_index); 243 return; 244 } 245 246 map = &vlv_gpio_table[gpio_index]; 247 248 if (dev_priv->vbt.dsi.seq_version >= 3) { 249 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ 250 port = IOSF_PORT_GPIO_NC; 251 } else { 252 if (gpio_source == 0) { 253 port = IOSF_PORT_GPIO_NC; 254 } else if (gpio_source == 1) { 255 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n"); 256 return; 257 } else { 258 drm_dbg_kms(&dev_priv->drm, 259 "unknown gpio source %u\n", gpio_source); 260 return; 261 } 262 } 263 264 pconf0 = VLV_GPIO_PCONF0(map->base_offset); 265 padval = VLV_GPIO_PAD_VAL(map->base_offset); 266 267 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 268 if (!map->init) { 269 /* FIXME: remove constant below */ 270 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); 271 map->init = true; 272 } 273 274 tmp = 0x4 | value; 275 vlv_iosf_sb_write(dev_priv, port, padval, tmp); 276 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 277 } 278 279 static void chv_exec_gpio(struct drm_i915_private *dev_priv, 280 u8 gpio_source, u8 gpio_index, bool value) 281 { 282 u16 cfg0, cfg1; 283 u16 family_num; 284 u8 port; 285 286 if (dev_priv->vbt.dsi.seq_version >= 3) { 287 if (gpio_index >= CHV_GPIO_IDX_START_SE) { 288 /* XXX: it's unclear whether 255->57 is part of SE. */ 289 gpio_index -= CHV_GPIO_IDX_START_SE; 290 port = CHV_IOSF_PORT_GPIO_SE; 291 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { 292 gpio_index -= CHV_GPIO_IDX_START_SW; 293 port = CHV_IOSF_PORT_GPIO_SW; 294 } else if (gpio_index >= CHV_GPIO_IDX_START_E) { 295 gpio_index -= CHV_GPIO_IDX_START_E; 296 port = CHV_IOSF_PORT_GPIO_E; 297 } else { 298 port = CHV_IOSF_PORT_GPIO_N; 299 } 300 } else { 301 /* XXX: The spec is unclear about CHV GPIO on seq v2 */ 302 if (gpio_source != 0) { 303 drm_dbg_kms(&dev_priv->drm, 304 "unknown gpio source %u\n", gpio_source); 305 return; 306 } 307 308 if (gpio_index >= CHV_GPIO_IDX_START_E) { 309 drm_dbg_kms(&dev_priv->drm, 310 "invalid gpio index %u for GPIO N\n", 311 gpio_index); 312 return; 313 } 314 315 port = CHV_IOSF_PORT_GPIO_N; 316 } 317 318 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY; 319 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY; 320 321 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); 322 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index); 323 324 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 325 vlv_iosf_sb_write(dev_priv, port, cfg1, 0); 326 vlv_iosf_sb_write(dev_priv, port, cfg0, 327 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO | 328 CHV_GPIO_GPIOTXSTATE(value)); 329 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 330 } 331 332 static void bxt_exec_gpio(struct drm_i915_private *dev_priv, 333 u8 gpio_source, u8 gpio_index, bool value) 334 { 335 STUB(); 336 #ifdef __linux__ 337 /* XXX: this table is a quick ugly hack. */ 338 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1]; 339 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index]; 340 341 if (!gpio_desc) { 342 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, 343 NULL, gpio_index, 344 value ? GPIOD_OUT_LOW : 345 GPIOD_OUT_HIGH); 346 347 if (IS_ERR_OR_NULL(gpio_desc)) { 348 drm_err(&dev_priv->drm, 349 "GPIO index %u request failed (%ld)\n", 350 gpio_index, PTR_ERR(gpio_desc)); 351 return; 352 } 353 354 bxt_gpio_table[gpio_index] = gpio_desc; 355 } 356 357 gpiod_set_value(gpio_desc, value); 358 #endif 359 } 360 361 static void icl_exec_gpio(struct drm_i915_private *dev_priv, 362 u8 gpio_source, u8 gpio_index, bool value) 363 { 364 drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n"); 365 } 366 367 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 368 { 369 struct drm_device *dev = intel_dsi->base.base.dev; 370 struct drm_i915_private *dev_priv = to_i915(dev); 371 u8 gpio_source, gpio_index = 0, gpio_number; 372 bool value; 373 374 drm_dbg_kms(&dev_priv->drm, "\n"); 375 376 if (dev_priv->vbt.dsi.seq_version >= 3) 377 gpio_index = *data++; 378 379 gpio_number = *data++; 380 381 /* gpio source in sequence v2 only */ 382 if (dev_priv->vbt.dsi.seq_version == 2) 383 gpio_source = (*data >> 1) & 3; 384 else 385 gpio_source = 0; 386 387 /* pull up/down */ 388 value = *data++ & 1; 389 390 if (INTEL_GEN(dev_priv) >= 11) 391 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value); 392 else if (IS_VALLEYVIEW(dev_priv)) 393 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 394 else if (IS_CHERRYVIEW(dev_priv)) 395 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 396 else 397 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value); 398 399 return data; 400 } 401 402 #if defined(CONFIG_ACPI) && defined(__linux__) 403 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data) 404 { 405 struct i2c_adapter_lookup *lookup = data; 406 struct intel_dsi *intel_dsi = lookup->intel_dsi; 407 struct acpi_resource_i2c_serialbus *sb; 408 struct i2c_adapter *adapter; 409 acpi_handle adapter_handle; 410 acpi_status status; 411 412 if (!i2c_acpi_get_i2c_resource(ares, &sb)) 413 return 1; 414 415 if (lookup->slave_addr != sb->slave_address) 416 return 1; 417 418 status = acpi_get_handle(lookup->dev_handle, 419 sb->resource_source.string_ptr, 420 &adapter_handle); 421 if (ACPI_FAILURE(status)) 422 return 1; 423 424 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle); 425 if (adapter) 426 intel_dsi->i2c_bus_num = adapter->nr; 427 428 return 1; 429 } 430 431 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 432 const u16 slave_addr) 433 { 434 struct drm_device *drm_dev = intel_dsi->base.base.dev; 435 struct device *dev = &drm_dev->pdev->dev; 436 struct acpi_device *acpi_dev; 437 struct list_head resource_list; 438 struct i2c_adapter_lookup lookup; 439 440 acpi_dev = ACPI_COMPANION(dev); 441 if (acpi_dev) { 442 memset(&lookup, 0, sizeof(lookup)); 443 lookup.slave_addr = slave_addr; 444 lookup.intel_dsi = intel_dsi; 445 lookup.dev_handle = acpi_device_handle(acpi_dev); 446 447 INIT_LIST_HEAD(&resource_list); 448 acpi_dev_get_resources(acpi_dev, &resource_list, 449 i2c_adapter_lookup, 450 &lookup); 451 acpi_dev_free_resource_list(&resource_list); 452 } 453 } 454 #else 455 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 456 const u16 slave_addr) 457 { 458 } 459 #endif 460 461 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) 462 { 463 STUB(); 464 return NULL; 465 #ifdef notyet 466 struct drm_device *drm_dev = intel_dsi->base.base.dev; 467 struct device *dev = &drm_dev->pdev->dev; 468 struct i2c_adapter *adapter; 469 struct i2c_msg msg; 470 int ret; 471 u8 vbt_i2c_bus_num = *(data + 2); 472 u16 slave_addr = *(u16 *)(data + 3); 473 u8 reg_offset = *(data + 5); 474 u8 payload_size = *(data + 6); 475 u8 *payload_data; 476 477 if (intel_dsi->i2c_bus_num < 0) { 478 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 479 i2c_acpi_find_adapter(intel_dsi, slave_addr); 480 } 481 482 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); 483 if (!adapter) { 484 DRM_DEV_ERROR(dev, "Cannot find a valid i2c bus for xfer\n"); 485 goto err_bus; 486 } 487 488 payload_data = kzalloc(payload_size + 1, GFP_KERNEL); 489 if (!payload_data) 490 goto err_alloc; 491 492 payload_data[0] = reg_offset; 493 memcpy(&payload_data[1], (data + 7), payload_size); 494 495 msg.addr = slave_addr; 496 msg.flags = 0; 497 msg.len = payload_size + 1; 498 msg.buf = payload_data; 499 500 ret = i2c_transfer(adapter, &msg, 1); 501 if (ret < 0) 502 DRM_DEV_ERROR(dev, 503 "Failed to xfer payload of size (%u) to reg (%u)\n", 504 payload_size, reg_offset); 505 506 kfree(payload_data); 507 err_alloc: 508 i2c_put_adapter(adapter); 509 err_bus: 510 return data + payload_size + 7; 511 #endif 512 } 513 514 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) 515 { 516 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 517 518 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n"); 519 520 return data + *(data + 5) + 6; 521 } 522 523 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) 524 { 525 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 526 #ifdef CONFIG_PMIC_OPREGION 527 u32 value, mask, reg_address; 528 u16 i2c_address; 529 int ret; 530 531 /* byte 0 aka PMIC Flag is reserved */ 532 i2c_address = get_unaligned_le16(data + 1); 533 reg_address = get_unaligned_le32(data + 3); 534 value = get_unaligned_le32(data + 7); 535 mask = get_unaligned_le32(data + 11); 536 537 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address, 538 reg_address, 539 value, mask); 540 if (ret) 541 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret); 542 #else 543 drm_err(&i915->drm, 544 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); 545 #endif 546 547 return data + 15; 548 } 549 550 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, 551 const u8 *data); 552 static const fn_mipi_elem_exec exec_elem[] = { 553 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, 554 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, 555 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, 556 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c, 557 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi, 558 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic, 559 }; 560 561 /* 562 * MIPI Sequence from VBT #53 parsing logic 563 * We have already separated each seqence during bios parsing 564 * Following is generic execution function for any sequence 565 */ 566 567 static const char * const seq_name[] = { 568 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 569 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 570 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 571 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 572 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 573 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 574 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 575 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 576 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", 577 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", 578 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", 579 }; 580 581 static const char *sequence_name(enum mipi_seq seq_id) 582 { 583 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) 584 return seq_name[seq_id]; 585 else 586 return "(unknown)"; 587 } 588 589 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, 590 enum mipi_seq seq_id) 591 { 592 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 593 const u8 *data; 594 fn_mipi_elem_exec mipi_elem_exec; 595 596 if (drm_WARN_ON(&dev_priv->drm, 597 seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) 598 return; 599 600 data = dev_priv->vbt.dsi.sequence[seq_id]; 601 if (!data) 602 return; 603 604 drm_WARN_ON(&dev_priv->drm, *data != seq_id); 605 606 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n", 607 seq_id, sequence_name(seq_id)); 608 609 /* Skip Sequence Byte. */ 610 data++; 611 612 /* Skip Size of Sequence. */ 613 if (dev_priv->vbt.dsi.seq_version >= 3) 614 data += 4; 615 616 while (1) { 617 u8 operation_byte = *data++; 618 u8 operation_size = 0; 619 620 if (operation_byte == MIPI_SEQ_ELEM_END) 621 break; 622 623 if (operation_byte < ARRAY_SIZE(exec_elem)) 624 mipi_elem_exec = exec_elem[operation_byte]; 625 else 626 mipi_elem_exec = NULL; 627 628 /* Size of Operation. */ 629 if (dev_priv->vbt.dsi.seq_version >= 3) 630 operation_size = *data++; 631 632 if (mipi_elem_exec) { 633 const u8 *next = data + operation_size; 634 635 data = mipi_elem_exec(intel_dsi, data); 636 637 /* Consistency check if we have size. */ 638 if (operation_size && data != next) { 639 drm_err(&dev_priv->drm, 640 "Inconsistent operation size\n"); 641 return; 642 } 643 } else if (operation_size) { 644 /* We have size, skip. */ 645 drm_dbg_kms(&dev_priv->drm, 646 "Unsupported MIPI operation byte %u\n", 647 operation_byte); 648 data += operation_size; 649 } else { 650 /* No size, can't skip without parsing. */ 651 drm_err(&dev_priv->drm, 652 "Unsupported MIPI operation byte %u\n", 653 operation_byte); 654 return; 655 } 656 } 657 } 658 659 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 660 enum mipi_seq seq_id) 661 { 662 STUB(); 663 #ifdef notyet 664 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel) 665 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 666 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight) 667 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1); 668 669 intel_dsi_vbt_exec(intel_dsi, seq_id); 670 671 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel) 672 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 673 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight) 674 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 675 #endif 676 } 677 678 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) 679 { 680 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 681 682 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */ 683 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3) 684 return; 685 686 drm_msleep(msec); 687 } 688 689 void intel_dsi_log_params(struct intel_dsi *intel_dsi) 690 { 691 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 692 693 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk); 694 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n", 695 intel_dsi->pixel_overlap); 696 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count); 697 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg); 698 drm_dbg_kms(&i915->drm, "Video mode format %s\n", 699 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ? 700 "non-burst with sync pulse" : 701 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ? 702 "non-burst with sync events" : 703 intel_dsi->video_mode_format == VIDEO_MODE_BURST ? 704 "burst" : "<unknown>"); 705 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n", 706 intel_dsi->burst_mode_ratio); 707 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val); 708 drm_dbg_kms(&i915->drm, "Eot %s\n", 709 enableddisabled(intel_dsi->eotp_pkt)); 710 drm_dbg_kms(&i915->drm, "Clockstop %s\n", 711 enableddisabled(!intel_dsi->clock_stop)); 712 drm_dbg_kms(&i915->drm, "Mode %s\n", 713 intel_dsi->operation_mode ? "command" : "video"); 714 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 715 drm_dbg_kms(&i915->drm, 716 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); 717 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) 718 drm_dbg_kms(&i915->drm, 719 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); 720 else 721 drm_dbg_kms(&i915->drm, "Dual link: NONE\n"); 722 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format); 723 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div); 724 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n", 725 intel_dsi->lp_rx_timeout); 726 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n", 727 intel_dsi->turn_arnd_val); 728 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count); 729 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n", 730 intel_dsi->hs_to_lp_count); 731 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk); 732 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer); 733 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n", 734 intel_dsi->clk_lp_to_hs_count); 735 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n", 736 intel_dsi->clk_hs_to_lp_count); 737 drm_dbg_kms(&i915->drm, "BTA %s\n", 738 enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 739 } 740 741 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 742 { 743 struct drm_device *dev = intel_dsi->base.base.dev; 744 struct drm_i915_private *dev_priv = to_i915(dev); 745 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 746 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; 747 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; 748 u16 burst_mode_ratio; 749 enum port port; 750 751 drm_dbg_kms(&dev_priv->drm, "\n"); 752 753 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; 754 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 755 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 756 intel_dsi->pixel_format = 757 pixel_format_from_register_bits( 758 mipi_config->videomode_color_format << 7); 759 760 intel_dsi->dual_link = mipi_config->dual_link; 761 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 762 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 763 intel_dsi->video_mode_format = mipi_config->video_transfer_mode; 764 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 765 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; 766 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout; 767 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; 768 intel_dsi->rst_timer_val = mipi_config->device_reset_timer; 769 intel_dsi->init_count = mipi_config->master_init_timer; 770 intel_dsi->bw_timer = mipi_config->dbi_bw_timer; 771 intel_dsi->video_frmt_cfg_bits = 772 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; 773 intel_dsi->bgr_enabled = mipi_config->rgb_flip; 774 775 /* Starting point, adjusted depending on dual link and burst mode */ 776 intel_dsi->pclk = mode->clock; 777 778 /* In dual link mode each port needs half of pixel clock */ 779 if (intel_dsi->dual_link) { 780 intel_dsi->pclk /= 2; 781 782 /* we can enable pixel_overlap if needed by panel. In this 783 * case we need to increase the pixelclock for extra pixels 784 */ 785 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 786 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); 787 } 788 } 789 790 /* Burst Mode Ratio 791 * Target ddr frequency from VBT / non burst ddr freq 792 * multiply by 100 to preserve remainder 793 */ 794 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 795 if (mipi_config->target_burst_mode_freq) { 796 u32 bitrate = intel_dsi_bitrate(intel_dsi); 797 798 /* 799 * Sometimes the VBT contains a slightly lower clock, 800 * then the bitrate we have calculated, in this case 801 * just replace it with the calculated bitrate. 802 */ 803 if (mipi_config->target_burst_mode_freq < bitrate && 804 intel_fuzzy_clock_check( 805 mipi_config->target_burst_mode_freq, 806 bitrate)) 807 mipi_config->target_burst_mode_freq = bitrate; 808 809 if (mipi_config->target_burst_mode_freq < bitrate) { 810 drm_err(&dev_priv->drm, 811 "Burst mode freq is less than computed\n"); 812 return false; 813 } 814 815 burst_mode_ratio = DIV_ROUND_UP( 816 mipi_config->target_burst_mode_freq * 100, 817 bitrate); 818 819 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); 820 } else { 821 drm_err(&dev_priv->drm, 822 "Burst mode target is not set\n"); 823 return false; 824 } 825 } else 826 burst_mode_ratio = 100; 827 828 intel_dsi->burst_mode_ratio = burst_mode_ratio; 829 830 /* delays in VBT are in unit of 100us, so need to convert 831 * here in ms 832 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ 833 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; 834 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; 835 intel_dsi->panel_on_delay = pps->panel_on_delay / 10; 836 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 837 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 838 839 intel_dsi->i2c_bus_num = -1; 840 841 /* a regular driver would get the device in probe */ 842 for_each_dsi_port(port, intel_dsi->ports) { 843 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); 844 } 845 846 return true; 847 } 848 849 #ifdef notyet 850 851 /* 852 * On some BYT/CHT devs some sequences are incomplete and we need to manually 853 * control some GPIOs. We need to add a GPIO lookup table before we get these. 854 * If the GOP did not initialize the panel (HDMI inserted) we may need to also 855 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM. 856 */ 857 static struct gpiod_lookup_table pmic_panel_gpio_table = { 858 /* Intel GFX is consumer */ 859 .dev_id = "0000:00:02.0", 860 .table = { 861 /* Panel EN/DISABLE */ 862 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH), 863 { } 864 }, 865 }; 866 867 static struct gpiod_lookup_table soc_panel_gpio_table = { 868 .dev_id = "0000:00:02.0", 869 .table = { 870 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH), 871 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH), 872 { } 873 }, 874 }; 875 876 static const struct pinctrl_map soc_pwm_pinctrl_map[] = { 877 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00", 878 "pwm0_grp", "pwm"), 879 }; 880 881 #endif /* notyet */ 882 883 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) 884 { 885 STUB(); 886 #ifdef notyet 887 struct drm_device *dev = intel_dsi->base.base.dev; 888 struct drm_i915_private *dev_priv = to_i915(dev); 889 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 890 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 891 bool want_backlight_gpio = false; 892 bool want_panel_gpio = false; 893 struct pinctrl *pinctrl; 894 int ret; 895 896 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 897 mipi_config->pwm_blc == PPS_BLC_PMIC) { 898 gpiod_add_lookup_table(&pmic_panel_gpio_table); 899 want_panel_gpio = true; 900 } 901 902 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 903 gpiod_add_lookup_table(&soc_panel_gpio_table); 904 want_panel_gpio = true; 905 want_backlight_gpio = true; 906 907 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */ 908 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, 909 ARRAY_SIZE(soc_pwm_pinctrl_map)); 910 if (ret) 911 drm_err(&dev_priv->drm, 912 "Failed to register pwm0 pinmux mapping\n"); 913 914 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0"); 915 if (IS_ERR(pinctrl)) 916 drm_err(&dev_priv->drm, 917 "Failed to set pinmux to PWM\n"); 918 } 919 920 if (want_panel_gpio) { 921 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags); 922 if (IS_ERR(intel_dsi->gpio_panel)) { 923 drm_err(&dev_priv->drm, 924 "Failed to own gpio for panel control\n"); 925 intel_dsi->gpio_panel = NULL; 926 } 927 } 928 929 if (want_backlight_gpio) { 930 intel_dsi->gpio_backlight = 931 gpiod_get(dev->dev, "backlight", flags); 932 if (IS_ERR(intel_dsi->gpio_backlight)) { 933 drm_err(&dev_priv->drm, 934 "Failed to own gpio for backlight control\n"); 935 intel_dsi->gpio_backlight = NULL; 936 } 937 } 938 #endif 939 } 940 941 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi) 942 { 943 STUB(); 944 #ifdef notyet 945 struct drm_device *dev = intel_dsi->base.base.dev; 946 struct drm_i915_private *dev_priv = to_i915(dev); 947 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 948 949 if (intel_dsi->gpio_panel) { 950 gpiod_put(intel_dsi->gpio_panel); 951 intel_dsi->gpio_panel = NULL; 952 } 953 954 if (intel_dsi->gpio_backlight) { 955 gpiod_put(intel_dsi->gpio_backlight); 956 intel_dsi->gpio_backlight = NULL; 957 } 958 959 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 960 mipi_config->pwm_blc == PPS_BLC_PMIC) 961 gpiod_remove_lookup_table(&pmic_panel_gpio_table); 962 963 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 964 pinctrl_unregister_mappings(soc_pwm_pinctrl_map); 965 gpiod_remove_lookup_table(&soc_panel_gpio_table); 966 } 967 #endif 968 } 969