1c349dbc7Sjsg /*
2c349dbc7Sjsg  * Copyright © 2015 Intel Corporation
3c349dbc7Sjsg  *
4c349dbc7Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
5c349dbc7Sjsg  * copy of this software and associated documentation files (the "Software"),
6c349dbc7Sjsg  * to deal in the Software without restriction, including without limitation
7c349dbc7Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8c349dbc7Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
9c349dbc7Sjsg  * Software is furnished to do so, subject to the following conditions:
10c349dbc7Sjsg  *
11c349dbc7Sjsg  * The above copyright notice and this permission notice (including the next
12c349dbc7Sjsg  * paragraph) shall be included in all copies or substantial portions of the
13c349dbc7Sjsg  * Software.
14c349dbc7Sjsg  *
15c349dbc7Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16c349dbc7Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17c349dbc7Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18c349dbc7Sjsg  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19c349dbc7Sjsg  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20c349dbc7Sjsg  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21c349dbc7Sjsg  * IN THE SOFTWARE.
22c349dbc7Sjsg  */
23c349dbc7Sjsg 
24c349dbc7Sjsg #include <linux/kernel.h>
25c349dbc7Sjsg 
26c349dbc7Sjsg #include "i915_drv.h"
271bb76ff1Sjsg #include "i915_irq.h"
28c349dbc7Sjsg #include "intel_display_types.h"
29c349dbc7Sjsg #include "intel_hotplug.h"
30*f005ef32Sjsg #include "intel_hotplug_irq.h"
31c349dbc7Sjsg 
32c349dbc7Sjsg /**
33c349dbc7Sjsg  * DOC: Hotplug
34c349dbc7Sjsg  *
35c349dbc7Sjsg  * Simply put, hotplug occurs when a display is connected to or disconnected
36c349dbc7Sjsg  * from the system. However, there may be adapters and docking stations and
37c349dbc7Sjsg  * Display Port short pulses and MST devices involved, complicating matters.
38c349dbc7Sjsg  *
39c349dbc7Sjsg  * Hotplug in i915 is handled in many different levels of abstraction.
40c349dbc7Sjsg  *
41c349dbc7Sjsg  * The platform dependent interrupt handling code in i915_irq.c enables,
42c349dbc7Sjsg  * disables, and does preliminary handling of the interrupts. The interrupt
43c349dbc7Sjsg  * handlers gather the hotplug detect (HPD) information from relevant registers
44c349dbc7Sjsg  * into a platform independent mask of hotplug pins that have fired.
45c349dbc7Sjsg  *
46c349dbc7Sjsg  * The platform independent interrupt handler intel_hpd_irq_handler() in
47c349dbc7Sjsg  * intel_hotplug.c does hotplug irq storm detection and mitigation, and passes
48c349dbc7Sjsg  * further processing to appropriate bottom halves (Display Port specific and
49c349dbc7Sjsg  * regular hotplug).
50c349dbc7Sjsg  *
51c349dbc7Sjsg  * The Display Port work function i915_digport_work_func() calls into
52c349dbc7Sjsg  * intel_dp_hpd_pulse() via hooks, which handles DP short pulses and DP MST long
53c349dbc7Sjsg  * pulses, with failures and non-MST long pulses triggering regular hotplug
54c349dbc7Sjsg  * processing on the connector.
55c349dbc7Sjsg  *
56c349dbc7Sjsg  * The regular hotplug work function i915_hotplug_work_func() calls connector
57c349dbc7Sjsg  * detect hooks, and, if connector status changes, triggers sending of hotplug
58c349dbc7Sjsg  * uevent to userspace via drm_kms_helper_hotplug_event().
59c349dbc7Sjsg  *
60c349dbc7Sjsg  * Finally, the userspace is responsible for triggering a modeset upon receiving
61c349dbc7Sjsg  * the hotplug uevent, disabling or enabling the crtc as needed.
62c349dbc7Sjsg  *
63c349dbc7Sjsg  * The hotplug interrupt storm detection and mitigation code keeps track of the
64c349dbc7Sjsg  * number of interrupts per hotplug pin per a period of time, and if the number
65c349dbc7Sjsg  * of interrupts exceeds a certain threshold, the interrupt is disabled for a
66c349dbc7Sjsg  * while before being re-enabled. The intention is to mitigate issues raising
67c349dbc7Sjsg  * from broken hardware triggering massive amounts of interrupts and grinding
68c349dbc7Sjsg  * the system to a halt.
69c349dbc7Sjsg  *
70c349dbc7Sjsg  * Current implementation expects that hotplug interrupt storm will not be
71c349dbc7Sjsg  * seen when display port sink is connected, hence on platforms whose DP
72c349dbc7Sjsg  * callback is handled by i915_digport_work_func reenabling of hpd is not
73c349dbc7Sjsg  * performed (it was never expected to be disabled in the first place ;) )
74c349dbc7Sjsg  * this is specific to DP sinks handled by this routine and any other display
75c349dbc7Sjsg  * such as HDMI or DVI enabled on the same port will have proper logic since
76c349dbc7Sjsg  * it will use i915_hotplug_work_func where this logic is handled.
77c349dbc7Sjsg  */
78c349dbc7Sjsg 
79c349dbc7Sjsg /**
80c349dbc7Sjsg  * intel_hpd_pin_default - return default pin associated with certain port.
81c349dbc7Sjsg  * @dev_priv: private driver data pointer
82c349dbc7Sjsg  * @port: the hpd port to get associated pin
83c349dbc7Sjsg  *
84c349dbc7Sjsg  * It is only valid and used by digital port encoder.
85c349dbc7Sjsg  *
86ad8b1aafSjsg  * Return pin that is associatade with @port.
87c349dbc7Sjsg  */
intel_hpd_pin_default(struct drm_i915_private * dev_priv,enum port port)88c349dbc7Sjsg enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
89c349dbc7Sjsg 				   enum port port)
90c349dbc7Sjsg {
91ad8b1aafSjsg 	return HPD_PORT_A + port - PORT_A;
92c349dbc7Sjsg }
93c349dbc7Sjsg 
94*f005ef32Sjsg /* Threshold == 5 for long IRQs, 50 for short */
95*f005ef32Sjsg #define HPD_STORM_DEFAULT_THRESHOLD	50
96*f005ef32Sjsg 
97c349dbc7Sjsg #define HPD_STORM_DETECT_PERIOD		1000
98c349dbc7Sjsg #define HPD_STORM_REENABLE_DELAY	(2 * 60 * 1000)
99c349dbc7Sjsg #define HPD_RETRY_DELAY			1000
100c349dbc7Sjsg 
101c349dbc7Sjsg static enum hpd_pin
intel_connector_hpd_pin(struct intel_connector * connector)102c349dbc7Sjsg intel_connector_hpd_pin(struct intel_connector *connector)
103c349dbc7Sjsg {
104c349dbc7Sjsg 	struct intel_encoder *encoder = intel_attached_encoder(connector);
105c349dbc7Sjsg 
106c349dbc7Sjsg 	/*
107c349dbc7Sjsg 	 * MST connectors get their encoder attached dynamically
108c349dbc7Sjsg 	 * so need to make sure we have an encoder here. But since
109c349dbc7Sjsg 	 * MST encoders have their hpd_pin set to HPD_NONE we don't
110c349dbc7Sjsg 	 * have to special case them beyond that.
111c349dbc7Sjsg 	 */
112c349dbc7Sjsg 	return encoder ? encoder->hpd_pin : HPD_NONE;
113c349dbc7Sjsg }
114c349dbc7Sjsg 
115c349dbc7Sjsg /**
116c349dbc7Sjsg  * intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ storm on a pin
117c349dbc7Sjsg  * @dev_priv: private driver data pointer
118c349dbc7Sjsg  * @pin: the pin to gather stats on
119c349dbc7Sjsg  * @long_hpd: whether the HPD IRQ was long or short
120c349dbc7Sjsg  *
121c349dbc7Sjsg  * Gather stats about HPD IRQs from the specified @pin, and detect IRQ
122c349dbc7Sjsg  * storms. Only the pin specific stats and state are changed, the caller is
123c349dbc7Sjsg  * responsible for further action.
124c349dbc7Sjsg  *
125c349dbc7Sjsg  * The number of IRQs that are allowed within @HPD_STORM_DETECT_PERIOD is
1261bb76ff1Sjsg  * stored in @dev_priv->display.hotplug.hpd_storm_threshold which defaults to
127c349dbc7Sjsg  * @HPD_STORM_DEFAULT_THRESHOLD. Long IRQs count as +10 to this threshold, and
128c349dbc7Sjsg  * short IRQs count as +1. If this threshold is exceeded, it's considered an
129c349dbc7Sjsg  * IRQ storm and the IRQ state is set to @HPD_MARK_DISABLED.
130c349dbc7Sjsg  *
131c349dbc7Sjsg  * By default, most systems will only count long IRQs towards
1321bb76ff1Sjsg  * &dev_priv->display.hotplug.hpd_storm_threshold. However, some older systems also
133c349dbc7Sjsg  * suffer from short IRQ storms and must also track these. Because short IRQ
134c349dbc7Sjsg  * storms are naturally caused by sideband interactions with DP MST devices,
135c349dbc7Sjsg  * short IRQ detection is only enabled for systems without DP MST support.
136c349dbc7Sjsg  * Systems which are new enough to support DP MST are far less likely to
137c349dbc7Sjsg  * suffer from IRQ storms at all, so this is fine.
138c349dbc7Sjsg  *
139c349dbc7Sjsg  * The HPD threshold can be controlled through i915_hpd_storm_ctl in debugfs,
140c349dbc7Sjsg  * and should only be adjusted for automated hotplug testing.
141c349dbc7Sjsg  *
142c349dbc7Sjsg  * Return true if an IRQ storm was detected on @pin.
143c349dbc7Sjsg  */
intel_hpd_irq_storm_detect(struct drm_i915_private * dev_priv,enum hpd_pin pin,bool long_hpd)144c349dbc7Sjsg static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
145c349dbc7Sjsg 				       enum hpd_pin pin, bool long_hpd)
146c349dbc7Sjsg {
1471bb76ff1Sjsg 	struct intel_hotplug *hpd = &dev_priv->display.hotplug;
148c349dbc7Sjsg 	unsigned long start = hpd->stats[pin].last_jiffies;
149c349dbc7Sjsg 	unsigned long end = start + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD);
150c349dbc7Sjsg 	const int increment = long_hpd ? 10 : 1;
151c349dbc7Sjsg 	const int threshold = hpd->hpd_storm_threshold;
152c349dbc7Sjsg 	bool storm = false;
153c349dbc7Sjsg 
154c349dbc7Sjsg 	if (!threshold ||
1551bb76ff1Sjsg 	    (!long_hpd && !dev_priv->display.hotplug.hpd_short_storm_enabled))
156c349dbc7Sjsg 		return false;
157c349dbc7Sjsg 
158c349dbc7Sjsg 	if (!time_in_range(jiffies, start, end)) {
159c349dbc7Sjsg 		hpd->stats[pin].last_jiffies = jiffies;
160c349dbc7Sjsg 		hpd->stats[pin].count = 0;
161c349dbc7Sjsg 	}
162c349dbc7Sjsg 
163c349dbc7Sjsg 	hpd->stats[pin].count += increment;
164c349dbc7Sjsg 	if (hpd->stats[pin].count > threshold) {
165c349dbc7Sjsg 		hpd->stats[pin].state = HPD_MARK_DISABLED;
166c349dbc7Sjsg 		drm_dbg_kms(&dev_priv->drm,
167c349dbc7Sjsg 			    "HPD interrupt storm detected on PIN %d\n", pin);
168c349dbc7Sjsg 		storm = true;
169c349dbc7Sjsg 	} else {
170c349dbc7Sjsg 		drm_dbg_kms(&dev_priv->drm,
171c349dbc7Sjsg 			    "Received HPD interrupt on PIN %d - cnt: %d\n",
172c349dbc7Sjsg 			      pin,
173c349dbc7Sjsg 			      hpd->stats[pin].count);
174c349dbc7Sjsg 	}
175c349dbc7Sjsg 
176c349dbc7Sjsg 	return storm;
177c349dbc7Sjsg }
178c349dbc7Sjsg 
179c349dbc7Sjsg static void
intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private * dev_priv)180c349dbc7Sjsg intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
181c349dbc7Sjsg {
182c349dbc7Sjsg 	struct drm_connector_list_iter conn_iter;
183c349dbc7Sjsg 	struct intel_connector *connector;
184c349dbc7Sjsg 	bool hpd_disabled = false;
185c349dbc7Sjsg 
186c349dbc7Sjsg 	lockdep_assert_held(&dev_priv->irq_lock);
187c349dbc7Sjsg 
188*f005ef32Sjsg 	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
189c349dbc7Sjsg 	for_each_intel_connector_iter(connector, &conn_iter) {
190c349dbc7Sjsg 		enum hpd_pin pin;
191c349dbc7Sjsg 
192c349dbc7Sjsg 		if (connector->base.polled != DRM_CONNECTOR_POLL_HPD)
193c349dbc7Sjsg 			continue;
194c349dbc7Sjsg 
195c349dbc7Sjsg 		pin = intel_connector_hpd_pin(connector);
196c349dbc7Sjsg 		if (pin == HPD_NONE ||
1971bb76ff1Sjsg 		    dev_priv->display.hotplug.stats[pin].state != HPD_MARK_DISABLED)
198c349dbc7Sjsg 			continue;
199c349dbc7Sjsg 
200c349dbc7Sjsg 		drm_info(&dev_priv->drm,
201c349dbc7Sjsg 			 "HPD interrupt storm detected on connector %s: "
202c349dbc7Sjsg 			 "switching from hotplug detection to polling\n",
203c349dbc7Sjsg 			 connector->base.name);
204c349dbc7Sjsg 
2051bb76ff1Sjsg 		dev_priv->display.hotplug.stats[pin].state = HPD_DISABLED;
206c349dbc7Sjsg 		connector->base.polled = DRM_CONNECTOR_POLL_CONNECT |
207c349dbc7Sjsg 			DRM_CONNECTOR_POLL_DISCONNECT;
208c349dbc7Sjsg 		hpd_disabled = true;
209c349dbc7Sjsg 	}
210c349dbc7Sjsg 	drm_connector_list_iter_end(&conn_iter);
211c349dbc7Sjsg 
212c349dbc7Sjsg 	/* Enable polling and queue hotplug re-enabling. */
213c349dbc7Sjsg 	if (hpd_disabled) {
214*f005ef32Sjsg 		drm_kms_helper_poll_reschedule(&dev_priv->drm);
215*f005ef32Sjsg 		mod_delayed_work(dev_priv->unordered_wq,
216*f005ef32Sjsg 				 &dev_priv->display.hotplug.reenable_work,
217c349dbc7Sjsg 				 msecs_to_jiffies(HPD_STORM_REENABLE_DELAY));
218c349dbc7Sjsg 	}
219c349dbc7Sjsg }
220c349dbc7Sjsg 
intel_hpd_irq_storm_reenable_work(struct work_struct * work)221c349dbc7Sjsg static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
222c349dbc7Sjsg {
223c349dbc7Sjsg 	struct drm_i915_private *dev_priv =
224c349dbc7Sjsg 		container_of(work, typeof(*dev_priv),
2251bb76ff1Sjsg 			     display.hotplug.reenable_work.work);
226c349dbc7Sjsg 	struct drm_connector_list_iter conn_iter;
227c349dbc7Sjsg 	struct intel_connector *connector;
228c349dbc7Sjsg 	intel_wakeref_t wakeref;
229c349dbc7Sjsg 	enum hpd_pin pin;
230c349dbc7Sjsg 
231c349dbc7Sjsg 	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
232c349dbc7Sjsg 
233c349dbc7Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
234c349dbc7Sjsg 
235*f005ef32Sjsg 	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
236c349dbc7Sjsg 	for_each_intel_connector_iter(connector, &conn_iter) {
237c349dbc7Sjsg 		pin = intel_connector_hpd_pin(connector);
238c349dbc7Sjsg 		if (pin == HPD_NONE ||
2391bb76ff1Sjsg 		    dev_priv->display.hotplug.stats[pin].state != HPD_DISABLED)
240c349dbc7Sjsg 			continue;
241c349dbc7Sjsg 
242c349dbc7Sjsg 		if (connector->base.polled != connector->polled)
243c349dbc7Sjsg 			drm_dbg(&dev_priv->drm,
244c349dbc7Sjsg 				"Reenabling HPD on connector %s\n",
245c349dbc7Sjsg 				connector->base.name);
246c349dbc7Sjsg 		connector->base.polled = connector->polled;
247c349dbc7Sjsg 	}
248c349dbc7Sjsg 	drm_connector_list_iter_end(&conn_iter);
249c349dbc7Sjsg 
250c349dbc7Sjsg 	for_each_hpd_pin(pin) {
2511bb76ff1Sjsg 		if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED)
2521bb76ff1Sjsg 			dev_priv->display.hotplug.stats[pin].state = HPD_ENABLED;
253c349dbc7Sjsg 	}
254c349dbc7Sjsg 
2555ca02815Sjsg 	intel_hpd_irq_setup(dev_priv);
256c349dbc7Sjsg 
257c349dbc7Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
258c349dbc7Sjsg 
259c349dbc7Sjsg 	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
260c349dbc7Sjsg }
261c349dbc7Sjsg 
262c349dbc7Sjsg enum intel_hotplug_state
intel_encoder_hotplug(struct intel_encoder * encoder,struct intel_connector * connector)263c349dbc7Sjsg intel_encoder_hotplug(struct intel_encoder *encoder,
264ad8b1aafSjsg 		      struct intel_connector *connector)
265c349dbc7Sjsg {
266c349dbc7Sjsg 	struct drm_device *dev = connector->base.dev;
267c349dbc7Sjsg 	enum drm_connector_status old_status;
268ad8b1aafSjsg 	u64 old_epoch_counter;
269ad8b1aafSjsg 	bool ret = false;
270c349dbc7Sjsg 
271c349dbc7Sjsg 	drm_WARN_ON(dev, !mutex_is_locked(&dev->mode_config.mutex));
272c349dbc7Sjsg 	old_status = connector->base.status;
273ad8b1aafSjsg 	old_epoch_counter = connector->base.epoch_counter;
274c349dbc7Sjsg 
275c349dbc7Sjsg 	connector->base.status =
276c349dbc7Sjsg 		drm_helper_probe_detect(&connector->base, NULL, false);
277c349dbc7Sjsg 
278ad8b1aafSjsg 	if (old_epoch_counter != connector->base.epoch_counter)
279ad8b1aafSjsg 		ret = true;
280c349dbc7Sjsg 
281ad8b1aafSjsg 	if (ret) {
2821bb76ff1Sjsg 		drm_dbg_kms(dev, "[CONNECTOR:%d:%s] status updated from %s to %s (epoch counter %llu->%llu)\n",
283c349dbc7Sjsg 			    connector->base.base.id,
284c349dbc7Sjsg 			    connector->base.name,
285c349dbc7Sjsg 			    drm_get_connector_status_name(old_status),
286ad8b1aafSjsg 			    drm_get_connector_status_name(connector->base.status),
287ad8b1aafSjsg 			    old_epoch_counter,
288ad8b1aafSjsg 			    connector->base.epoch_counter);
289c349dbc7Sjsg 		return INTEL_HOTPLUG_CHANGED;
290c349dbc7Sjsg 	}
291ad8b1aafSjsg 	return INTEL_HOTPLUG_UNCHANGED;
292ad8b1aafSjsg }
293c349dbc7Sjsg 
intel_encoder_has_hpd_pulse(struct intel_encoder * encoder)294c349dbc7Sjsg static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder)
295c349dbc7Sjsg {
296c349dbc7Sjsg 	return intel_encoder_is_dig_port(encoder) &&
297c349dbc7Sjsg 		enc_to_dig_port(encoder)->hpd_pulse != NULL;
298c349dbc7Sjsg }
299c349dbc7Sjsg 
i915_digport_work_func(struct work_struct * work)300c349dbc7Sjsg static void i915_digport_work_func(struct work_struct *work)
301c349dbc7Sjsg {
302c349dbc7Sjsg 	struct drm_i915_private *dev_priv =
3031bb76ff1Sjsg 		container_of(work, struct drm_i915_private, display.hotplug.dig_port_work);
304c349dbc7Sjsg 	u32 long_port_mask, short_port_mask;
305c349dbc7Sjsg 	struct intel_encoder *encoder;
306c349dbc7Sjsg 	u32 old_bits = 0;
307c349dbc7Sjsg 
308c349dbc7Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
3091bb76ff1Sjsg 	long_port_mask = dev_priv->display.hotplug.long_port_mask;
3101bb76ff1Sjsg 	dev_priv->display.hotplug.long_port_mask = 0;
3111bb76ff1Sjsg 	short_port_mask = dev_priv->display.hotplug.short_port_mask;
3121bb76ff1Sjsg 	dev_priv->display.hotplug.short_port_mask = 0;
313c349dbc7Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
314c349dbc7Sjsg 
315c349dbc7Sjsg 	for_each_intel_encoder(&dev_priv->drm, encoder) {
316c349dbc7Sjsg 		struct intel_digital_port *dig_port;
317c349dbc7Sjsg 		enum port port = encoder->port;
318c349dbc7Sjsg 		bool long_hpd, short_hpd;
319c349dbc7Sjsg 		enum irqreturn ret;
320c349dbc7Sjsg 
321c349dbc7Sjsg 		if (!intel_encoder_has_hpd_pulse(encoder))
322c349dbc7Sjsg 			continue;
323c349dbc7Sjsg 
324c349dbc7Sjsg 		long_hpd = long_port_mask & BIT(port);
325c349dbc7Sjsg 		short_hpd = short_port_mask & BIT(port);
326c349dbc7Sjsg 
327c349dbc7Sjsg 		if (!long_hpd && !short_hpd)
328c349dbc7Sjsg 			continue;
329c349dbc7Sjsg 
330c349dbc7Sjsg 		dig_port = enc_to_dig_port(encoder);
331c349dbc7Sjsg 
332c349dbc7Sjsg 		ret = dig_port->hpd_pulse(dig_port, long_hpd);
333c349dbc7Sjsg 		if (ret == IRQ_NONE) {
334c349dbc7Sjsg 			/* fall back to old school hpd */
335c349dbc7Sjsg 			old_bits |= BIT(encoder->hpd_pin);
336c349dbc7Sjsg 		}
337c349dbc7Sjsg 	}
338c349dbc7Sjsg 
339c349dbc7Sjsg 	if (old_bits) {
340c349dbc7Sjsg 		spin_lock_irq(&dev_priv->irq_lock);
3411bb76ff1Sjsg 		dev_priv->display.hotplug.event_bits |= old_bits;
342c349dbc7Sjsg 		spin_unlock_irq(&dev_priv->irq_lock);
343*f005ef32Sjsg 		queue_delayed_work(dev_priv->unordered_wq,
344*f005ef32Sjsg 				   &dev_priv->display.hotplug.hotplug_work, 0);
345c349dbc7Sjsg 	}
346c349dbc7Sjsg }
347c349dbc7Sjsg 
348ad8b1aafSjsg /**
349ad8b1aafSjsg  * intel_hpd_trigger_irq - trigger an hpd irq event for a port
350ad8b1aafSjsg  * @dig_port: digital port
351ad8b1aafSjsg  *
352ad8b1aafSjsg  * Trigger an HPD interrupt event for the given port, emulating a short pulse
353ad8b1aafSjsg  * generated by the sink, and schedule the dig port work to handle it.
354ad8b1aafSjsg  */
intel_hpd_trigger_irq(struct intel_digital_port * dig_port)355ad8b1aafSjsg void intel_hpd_trigger_irq(struct intel_digital_port *dig_port)
356ad8b1aafSjsg {
357ad8b1aafSjsg 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
358ad8b1aafSjsg 
359ad8b1aafSjsg 	spin_lock_irq(&i915->irq_lock);
3601bb76ff1Sjsg 	i915->display.hotplug.short_port_mask |= BIT(dig_port->base.port);
361ad8b1aafSjsg 	spin_unlock_irq(&i915->irq_lock);
362ad8b1aafSjsg 
3631bb76ff1Sjsg 	queue_work(i915->display.hotplug.dp_wq, &i915->display.hotplug.dig_port_work);
364ad8b1aafSjsg }
365ad8b1aafSjsg 
366c349dbc7Sjsg /*
367c349dbc7Sjsg  * Handle hotplug events outside the interrupt handler proper.
368c349dbc7Sjsg  */
i915_hotplug_work_func(struct work_struct * work)369c349dbc7Sjsg static void i915_hotplug_work_func(struct work_struct *work)
370c349dbc7Sjsg {
371c349dbc7Sjsg 	struct drm_i915_private *dev_priv =
372c349dbc7Sjsg 		container_of(work, struct drm_i915_private,
3731bb76ff1Sjsg 			     display.hotplug.hotplug_work.work);
374c349dbc7Sjsg 	struct drm_connector_list_iter conn_iter;
375c349dbc7Sjsg 	struct intel_connector *connector;
376c349dbc7Sjsg 	u32 changed = 0, retry = 0;
377c349dbc7Sjsg 	u32 hpd_event_bits;
378c349dbc7Sjsg 	u32 hpd_retry_bits;
379*f005ef32Sjsg 	struct drm_connector *first_changed_connector = NULL;
380*f005ef32Sjsg 	int changed_connectors = 0;
381c349dbc7Sjsg 
382*f005ef32Sjsg 	mutex_lock(&dev_priv->drm.mode_config.mutex);
383c349dbc7Sjsg 	drm_dbg_kms(&dev_priv->drm, "running encoder hotplug functions\n");
384c349dbc7Sjsg 
385c349dbc7Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
386c349dbc7Sjsg 
3871bb76ff1Sjsg 	hpd_event_bits = dev_priv->display.hotplug.event_bits;
3881bb76ff1Sjsg 	dev_priv->display.hotplug.event_bits = 0;
3891bb76ff1Sjsg 	hpd_retry_bits = dev_priv->display.hotplug.retry_bits;
3901bb76ff1Sjsg 	dev_priv->display.hotplug.retry_bits = 0;
391c349dbc7Sjsg 
392c349dbc7Sjsg 	/* Enable polling for connectors which had HPD IRQ storms */
393c349dbc7Sjsg 	intel_hpd_irq_storm_switch_to_polling(dev_priv);
394c349dbc7Sjsg 
395c349dbc7Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
396c349dbc7Sjsg 
397*f005ef32Sjsg 	/* Skip calling encode hotplug handlers if ignore long HPD set*/
398*f005ef32Sjsg 	if (dev_priv->display.hotplug.ignore_long_hpd) {
399*f005ef32Sjsg 		drm_dbg_kms(&dev_priv->drm, "Ignore HPD flag on - skip encoder hotplug handlers\n");
400*f005ef32Sjsg 		mutex_unlock(&dev_priv->drm.mode_config.mutex);
401*f005ef32Sjsg 		return;
402*f005ef32Sjsg 	}
403*f005ef32Sjsg 
404*f005ef32Sjsg 	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
405c349dbc7Sjsg 	for_each_intel_connector_iter(connector, &conn_iter) {
406c349dbc7Sjsg 		enum hpd_pin pin;
407c349dbc7Sjsg 		u32 hpd_bit;
408c349dbc7Sjsg 
409c349dbc7Sjsg 		pin = intel_connector_hpd_pin(connector);
410c349dbc7Sjsg 		if (pin == HPD_NONE)
411c349dbc7Sjsg 			continue;
412c349dbc7Sjsg 
413c349dbc7Sjsg 		hpd_bit = BIT(pin);
414c349dbc7Sjsg 		if ((hpd_event_bits | hpd_retry_bits) & hpd_bit) {
415c349dbc7Sjsg 			struct intel_encoder *encoder =
416c349dbc7Sjsg 				intel_attached_encoder(connector);
417c349dbc7Sjsg 
418ad8b1aafSjsg 			if (hpd_event_bits & hpd_bit)
419ad8b1aafSjsg 				connector->hotplug_retries = 0;
420ad8b1aafSjsg 			else
421ad8b1aafSjsg 				connector->hotplug_retries++;
422c349dbc7Sjsg 
423ad8b1aafSjsg 			drm_dbg_kms(&dev_priv->drm,
424ad8b1aafSjsg 				    "Connector %s (pin %i) received hotplug event. (retry %d)\n",
425ad8b1aafSjsg 				    connector->base.name, pin,
426ad8b1aafSjsg 				    connector->hotplug_retries);
427ad8b1aafSjsg 
428ad8b1aafSjsg 			switch (encoder->hotplug(encoder, connector)) {
429c349dbc7Sjsg 			case INTEL_HOTPLUG_UNCHANGED:
430c349dbc7Sjsg 				break;
431c349dbc7Sjsg 			case INTEL_HOTPLUG_CHANGED:
432c349dbc7Sjsg 				changed |= hpd_bit;
433*f005ef32Sjsg 				changed_connectors++;
434*f005ef32Sjsg 				if (!first_changed_connector) {
435*f005ef32Sjsg 					drm_connector_get(&connector->base);
436*f005ef32Sjsg 					first_changed_connector = &connector->base;
437*f005ef32Sjsg 				}
438c349dbc7Sjsg 				break;
439c349dbc7Sjsg 			case INTEL_HOTPLUG_RETRY:
440c349dbc7Sjsg 				retry |= hpd_bit;
441c349dbc7Sjsg 				break;
442c349dbc7Sjsg 			}
443c349dbc7Sjsg 		}
444c349dbc7Sjsg 	}
445c349dbc7Sjsg 	drm_connector_list_iter_end(&conn_iter);
446*f005ef32Sjsg 	mutex_unlock(&dev_priv->drm.mode_config.mutex);
447c349dbc7Sjsg 
448*f005ef32Sjsg 	if (changed_connectors == 1)
449*f005ef32Sjsg 		drm_kms_helper_connector_hotplug_event(first_changed_connector);
450*f005ef32Sjsg 	else if (changed_connectors > 0)
451*f005ef32Sjsg 		drm_kms_helper_hotplug_event(&dev_priv->drm);
452*f005ef32Sjsg 
453*f005ef32Sjsg 	if (first_changed_connector)
454*f005ef32Sjsg 		drm_connector_put(first_changed_connector);
455c349dbc7Sjsg 
456c349dbc7Sjsg 	/* Remove shared HPD pins that have changed */
457c349dbc7Sjsg 	retry &= ~changed;
458c349dbc7Sjsg 	if (retry) {
459c349dbc7Sjsg 		spin_lock_irq(&dev_priv->irq_lock);
4601bb76ff1Sjsg 		dev_priv->display.hotplug.retry_bits |= retry;
461c349dbc7Sjsg 		spin_unlock_irq(&dev_priv->irq_lock);
462c349dbc7Sjsg 
463*f005ef32Sjsg 		mod_delayed_work(dev_priv->unordered_wq,
464*f005ef32Sjsg 				 &dev_priv->display.hotplug.hotplug_work,
465c349dbc7Sjsg 				 msecs_to_jiffies(HPD_RETRY_DELAY));
466c349dbc7Sjsg 	}
467c349dbc7Sjsg }
468c349dbc7Sjsg 
469c349dbc7Sjsg 
470c349dbc7Sjsg /**
471c349dbc7Sjsg  * intel_hpd_irq_handler - main hotplug irq handler
472c349dbc7Sjsg  * @dev_priv: drm_i915_private
473c349dbc7Sjsg  * @pin_mask: a mask of hpd pins that have triggered the irq
474c349dbc7Sjsg  * @long_mask: a mask of hpd pins that may be long hpd pulses
475c349dbc7Sjsg  *
476c349dbc7Sjsg  * This is the main hotplug irq handler for all platforms. The platform specific
477c349dbc7Sjsg  * irq handlers call the platform specific hotplug irq handlers, which read and
478c349dbc7Sjsg  * decode the appropriate registers into bitmasks about hpd pins that have
479c349dbc7Sjsg  * triggered (@pin_mask), and which of those pins may be long pulses
480c349dbc7Sjsg  * (@long_mask). The @long_mask is ignored if the port corresponding to the pin
481c349dbc7Sjsg  * is not a digital port.
482c349dbc7Sjsg  *
483c349dbc7Sjsg  * Here, we do hotplug irq storm detection and mitigation, and pass further
484c349dbc7Sjsg  * processing to appropriate bottom halves.
485c349dbc7Sjsg  */
intel_hpd_irq_handler(struct drm_i915_private * dev_priv,u32 pin_mask,u32 long_mask)486c349dbc7Sjsg void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
487c349dbc7Sjsg 			   u32 pin_mask, u32 long_mask)
488c349dbc7Sjsg {
489c349dbc7Sjsg 	struct intel_encoder *encoder;
490c349dbc7Sjsg 	bool storm_detected = false;
491c349dbc7Sjsg 	bool queue_dig = false, queue_hp = false;
492c349dbc7Sjsg 	u32 long_hpd_pulse_mask = 0;
493c349dbc7Sjsg 	u32 short_hpd_pulse_mask = 0;
494c349dbc7Sjsg 	enum hpd_pin pin;
495c349dbc7Sjsg 
496c349dbc7Sjsg 	if (!pin_mask)
497c349dbc7Sjsg 		return;
498c349dbc7Sjsg 
499c349dbc7Sjsg 	spin_lock(&dev_priv->irq_lock);
500c349dbc7Sjsg 
501c349dbc7Sjsg 	/*
502c349dbc7Sjsg 	 * Determine whether ->hpd_pulse() exists for each pin, and
503c349dbc7Sjsg 	 * whether we have a short or a long pulse. This is needed
504c349dbc7Sjsg 	 * as each pin may have up to two encoders (HDMI and DP) and
505c349dbc7Sjsg 	 * only the one of them (DP) will have ->hpd_pulse().
506c349dbc7Sjsg 	 */
507c349dbc7Sjsg 	for_each_intel_encoder(&dev_priv->drm, encoder) {
508c349dbc7Sjsg 		enum port port = encoder->port;
509c349dbc7Sjsg 		bool long_hpd;
510c349dbc7Sjsg 
511c349dbc7Sjsg 		pin = encoder->hpd_pin;
512c349dbc7Sjsg 		if (!(BIT(pin) & pin_mask))
513c349dbc7Sjsg 			continue;
514c349dbc7Sjsg 
515ad8b1aafSjsg 		if (!intel_encoder_has_hpd_pulse(encoder))
516c349dbc7Sjsg 			continue;
517c349dbc7Sjsg 
518c349dbc7Sjsg 		long_hpd = long_mask & BIT(pin);
519c349dbc7Sjsg 
520c349dbc7Sjsg 		drm_dbg(&dev_priv->drm,
521c349dbc7Sjsg 			"digital hpd on [ENCODER:%d:%s] - %s\n",
522c349dbc7Sjsg 			encoder->base.base.id, encoder->base.name,
523c349dbc7Sjsg 			long_hpd ? "long" : "short");
524c349dbc7Sjsg 		queue_dig = true;
525c349dbc7Sjsg 
526c349dbc7Sjsg 		if (long_hpd) {
527c349dbc7Sjsg 			long_hpd_pulse_mask |= BIT(pin);
5281bb76ff1Sjsg 			dev_priv->display.hotplug.long_port_mask |= BIT(port);
529c349dbc7Sjsg 		} else {
530c349dbc7Sjsg 			short_hpd_pulse_mask |= BIT(pin);
5311bb76ff1Sjsg 			dev_priv->display.hotplug.short_port_mask |= BIT(port);
532c349dbc7Sjsg 		}
533c349dbc7Sjsg 	}
534c349dbc7Sjsg 
535c349dbc7Sjsg 	/* Now process each pin just once */
536c349dbc7Sjsg 	for_each_hpd_pin(pin) {
537c349dbc7Sjsg 		bool long_hpd;
538c349dbc7Sjsg 
539c349dbc7Sjsg 		if (!(BIT(pin) & pin_mask))
540c349dbc7Sjsg 			continue;
541c349dbc7Sjsg 
5421bb76ff1Sjsg 		if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED) {
543c349dbc7Sjsg 			/*
544c349dbc7Sjsg 			 * On GMCH platforms the interrupt mask bits only
545c349dbc7Sjsg 			 * prevent irq generation, not the setting of the
546c349dbc7Sjsg 			 * hotplug bits itself. So only WARN about unexpected
547c349dbc7Sjsg 			 * interrupts on saner platforms.
548c349dbc7Sjsg 			 */
549c349dbc7Sjsg 			drm_WARN_ONCE(&dev_priv->drm, !HAS_GMCH(dev_priv),
550c349dbc7Sjsg 				      "Received HPD interrupt on pin %d although disabled\n",
551c349dbc7Sjsg 				      pin);
552c349dbc7Sjsg 			continue;
553c349dbc7Sjsg 		}
554c349dbc7Sjsg 
5551bb76ff1Sjsg 		if (dev_priv->display.hotplug.stats[pin].state != HPD_ENABLED)
556c349dbc7Sjsg 			continue;
557c349dbc7Sjsg 
558c349dbc7Sjsg 		/*
559c349dbc7Sjsg 		 * Delegate to ->hpd_pulse() if one of the encoders for this
560c349dbc7Sjsg 		 * pin has it, otherwise let the hotplug_work deal with this
561c349dbc7Sjsg 		 * pin directly.
562c349dbc7Sjsg 		 */
563c349dbc7Sjsg 		if (((short_hpd_pulse_mask | long_hpd_pulse_mask) & BIT(pin))) {
564c349dbc7Sjsg 			long_hpd = long_hpd_pulse_mask & BIT(pin);
565c349dbc7Sjsg 		} else {
5661bb76ff1Sjsg 			dev_priv->display.hotplug.event_bits |= BIT(pin);
567c349dbc7Sjsg 			long_hpd = true;
568c349dbc7Sjsg 			queue_hp = true;
569c349dbc7Sjsg 		}
570c349dbc7Sjsg 
571c349dbc7Sjsg 		if (intel_hpd_irq_storm_detect(dev_priv, pin, long_hpd)) {
5721bb76ff1Sjsg 			dev_priv->display.hotplug.event_bits &= ~BIT(pin);
573c349dbc7Sjsg 			storm_detected = true;
574c349dbc7Sjsg 			queue_hp = true;
575c349dbc7Sjsg 		}
576c349dbc7Sjsg 	}
577c349dbc7Sjsg 
578c349dbc7Sjsg 	/*
579c349dbc7Sjsg 	 * Disable any IRQs that storms were detected on. Polling enablement
580c349dbc7Sjsg 	 * happens later in our hotplug work.
581c349dbc7Sjsg 	 */
5825ca02815Sjsg 	if (storm_detected)
5835ca02815Sjsg 		intel_hpd_irq_setup(dev_priv);
584c349dbc7Sjsg 	spin_unlock(&dev_priv->irq_lock);
585c349dbc7Sjsg 
586c349dbc7Sjsg 	/*
587c349dbc7Sjsg 	 * Our hotplug handler can grab modeset locks (by calling down into the
588c349dbc7Sjsg 	 * fb helpers). Hence it must not be run on our own dev-priv->wq work
589c349dbc7Sjsg 	 * queue for otherwise the flush_work in the pageflip code will
590c349dbc7Sjsg 	 * deadlock.
591c349dbc7Sjsg 	 */
592c349dbc7Sjsg 	if (queue_dig)
5931bb76ff1Sjsg 		queue_work(dev_priv->display.hotplug.dp_wq, &dev_priv->display.hotplug.dig_port_work);
594c349dbc7Sjsg 	if (queue_hp)
595*f005ef32Sjsg 		queue_delayed_work(dev_priv->unordered_wq,
596*f005ef32Sjsg 				   &dev_priv->display.hotplug.hotplug_work, 0);
597c349dbc7Sjsg }
598c349dbc7Sjsg 
599c349dbc7Sjsg /**
600c349dbc7Sjsg  * intel_hpd_init - initializes and enables hpd support
601c349dbc7Sjsg  * @dev_priv: i915 device instance
602c349dbc7Sjsg  *
603c349dbc7Sjsg  * This function enables the hotplug support. It requires that interrupts have
604c349dbc7Sjsg  * already been enabled with intel_irq_init_hw(). From this point on hotplug and
605c349dbc7Sjsg  * poll request can run concurrently to other code, so locking rules must be
606c349dbc7Sjsg  * obeyed.
607c349dbc7Sjsg  *
608c349dbc7Sjsg  * This is a separate step from interrupt enabling to simplify the locking rules
609c349dbc7Sjsg  * in the driver load and resume code.
610c349dbc7Sjsg  *
6115ca02815Sjsg  * Also see: intel_hpd_poll_enable() and intel_hpd_poll_disable().
612c349dbc7Sjsg  */
intel_hpd_init(struct drm_i915_private * dev_priv)613c349dbc7Sjsg void intel_hpd_init(struct drm_i915_private *dev_priv)
614c349dbc7Sjsg {
615c349dbc7Sjsg 	int i;
616c349dbc7Sjsg 
6175ca02815Sjsg 	if (!HAS_DISPLAY(dev_priv))
6185ca02815Sjsg 		return;
6195ca02815Sjsg 
620c349dbc7Sjsg 	for_each_hpd_pin(i) {
6211bb76ff1Sjsg 		dev_priv->display.hotplug.stats[i].count = 0;
6221bb76ff1Sjsg 		dev_priv->display.hotplug.stats[i].state = HPD_ENABLED;
623c349dbc7Sjsg 	}
624c349dbc7Sjsg 
625c349dbc7Sjsg 	/*
626c349dbc7Sjsg 	 * Interrupt setup is already guaranteed to be single-threaded, this is
627c349dbc7Sjsg 	 * just to make the assert_spin_locked checks happy.
628c349dbc7Sjsg 	 */
629c349dbc7Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
6305ca02815Sjsg 	intel_hpd_irq_setup(dev_priv);
631c349dbc7Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
632c349dbc7Sjsg }
633c349dbc7Sjsg 
i915_hpd_poll_init_work(struct work_struct * work)634c349dbc7Sjsg static void i915_hpd_poll_init_work(struct work_struct *work)
635c349dbc7Sjsg {
636c349dbc7Sjsg 	struct drm_i915_private *dev_priv =
637c349dbc7Sjsg 		container_of(work, struct drm_i915_private,
6381bb76ff1Sjsg 			     display.hotplug.poll_init_work);
639c349dbc7Sjsg 	struct drm_connector_list_iter conn_iter;
640c349dbc7Sjsg 	struct intel_connector *connector;
641c349dbc7Sjsg 	bool enabled;
642c349dbc7Sjsg 
643*f005ef32Sjsg 	mutex_lock(&dev_priv->drm.mode_config.mutex);
644c349dbc7Sjsg 
6451bb76ff1Sjsg 	enabled = READ_ONCE(dev_priv->display.hotplug.poll_enabled);
646c349dbc7Sjsg 
647*f005ef32Sjsg 	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
648c349dbc7Sjsg 	for_each_intel_connector_iter(connector, &conn_iter) {
649c349dbc7Sjsg 		enum hpd_pin pin;
650c349dbc7Sjsg 
651c349dbc7Sjsg 		pin = intel_connector_hpd_pin(connector);
652c349dbc7Sjsg 		if (pin == HPD_NONE)
653c349dbc7Sjsg 			continue;
654c349dbc7Sjsg 
655c349dbc7Sjsg 		connector->base.polled = connector->polled;
656c349dbc7Sjsg 
657c349dbc7Sjsg 		if (enabled && connector->base.polled == DRM_CONNECTOR_POLL_HPD)
658c349dbc7Sjsg 			connector->base.polled = DRM_CONNECTOR_POLL_CONNECT |
659c349dbc7Sjsg 				DRM_CONNECTOR_POLL_DISCONNECT;
660c349dbc7Sjsg 	}
661c349dbc7Sjsg 	drm_connector_list_iter_end(&conn_iter);
662c349dbc7Sjsg 
663c349dbc7Sjsg 	if (enabled)
664*f005ef32Sjsg 		drm_kms_helper_poll_reschedule(&dev_priv->drm);
665c349dbc7Sjsg 
666*f005ef32Sjsg 	mutex_unlock(&dev_priv->drm.mode_config.mutex);
667c349dbc7Sjsg 
668c349dbc7Sjsg 	/*
669c349dbc7Sjsg 	 * We might have missed any hotplugs that happened while we were
670c349dbc7Sjsg 	 * in the middle of disabling polling
671c349dbc7Sjsg 	 */
672c349dbc7Sjsg 	if (!enabled)
673*f005ef32Sjsg 		drm_helper_hpd_irq_event(&dev_priv->drm);
674c349dbc7Sjsg }
675c349dbc7Sjsg 
676c349dbc7Sjsg /**
6775ca02815Sjsg  * intel_hpd_poll_enable - enable polling for connectors with hpd
678c349dbc7Sjsg  * @dev_priv: i915 device instance
679c349dbc7Sjsg  *
6805ca02815Sjsg  * This function enables polling for all connectors which support HPD.
6815ca02815Sjsg  * Under certain conditions HPD may not be functional. On most Intel GPUs,
6825ca02815Sjsg  * this happens when we enter runtime suspend.
683c349dbc7Sjsg  * On Valleyview and Cherryview systems, this also happens when we shut off all
684c349dbc7Sjsg  * of the powerwells.
685c349dbc7Sjsg  *
686c349dbc7Sjsg  * Since this function can get called in contexts where we're already holding
687c349dbc7Sjsg  * dev->mode_config.mutex, we do the actual hotplug enabling in a seperate
688c349dbc7Sjsg  * worker.
689c349dbc7Sjsg  *
6905ca02815Sjsg  * Also see: intel_hpd_init() and intel_hpd_poll_disable().
691c349dbc7Sjsg  */
intel_hpd_poll_enable(struct drm_i915_private * dev_priv)6925ca02815Sjsg void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
693c349dbc7Sjsg {
6941bb76ff1Sjsg 	if (!HAS_DISPLAY(dev_priv) ||
6951bb76ff1Sjsg 	    !INTEL_DISPLAY_ENABLED(dev_priv))
6965ca02815Sjsg 		return;
6975ca02815Sjsg 
6981bb76ff1Sjsg 	WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, true);
699c349dbc7Sjsg 
700c349dbc7Sjsg 	/*
701c349dbc7Sjsg 	 * We might already be holding dev->mode_config.mutex, so do this in a
702c349dbc7Sjsg 	 * seperate worker
703c349dbc7Sjsg 	 * As well, there's no issue if we race here since we always reschedule
704c349dbc7Sjsg 	 * this worker anyway
705c349dbc7Sjsg 	 */
706*f005ef32Sjsg 	queue_work(dev_priv->unordered_wq,
707*f005ef32Sjsg 		   &dev_priv->display.hotplug.poll_init_work);
708c349dbc7Sjsg }
709c349dbc7Sjsg 
7105ca02815Sjsg /**
7115ca02815Sjsg  * intel_hpd_poll_disable - disable polling for connectors with hpd
7125ca02815Sjsg  * @dev_priv: i915 device instance
7135ca02815Sjsg  *
7145ca02815Sjsg  * This function disables polling for all connectors which support HPD.
7155ca02815Sjsg  * Under certain conditions HPD may not be functional. On most Intel GPUs,
7165ca02815Sjsg  * this happens when we enter runtime suspend.
7175ca02815Sjsg  * On Valleyview and Cherryview systems, this also happens when we shut off all
7185ca02815Sjsg  * of the powerwells.
7195ca02815Sjsg  *
7205ca02815Sjsg  * Since this function can get called in contexts where we're already holding
7215ca02815Sjsg  * dev->mode_config.mutex, we do the actual hotplug enabling in a seperate
7225ca02815Sjsg  * worker.
7235ca02815Sjsg  *
7245ca02815Sjsg  * Also used during driver init to initialize connector->polled
7255ca02815Sjsg  * appropriately for all connectors.
7265ca02815Sjsg  *
7275ca02815Sjsg  * Also see: intel_hpd_init() and intel_hpd_poll_enable().
7285ca02815Sjsg  */
intel_hpd_poll_disable(struct drm_i915_private * dev_priv)7295ca02815Sjsg void intel_hpd_poll_disable(struct drm_i915_private *dev_priv)
7305ca02815Sjsg {
7315ca02815Sjsg 	if (!HAS_DISPLAY(dev_priv))
7325ca02815Sjsg 		return;
7335ca02815Sjsg 
7341bb76ff1Sjsg 	WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, false);
735*f005ef32Sjsg 	queue_work(dev_priv->unordered_wq,
736*f005ef32Sjsg 		   &dev_priv->display.hotplug.poll_init_work);
7375ca02815Sjsg }
7385ca02815Sjsg 
intel_hpd_init_early(struct drm_i915_private * i915)739*f005ef32Sjsg void intel_hpd_init_early(struct drm_i915_private *i915)
740c349dbc7Sjsg {
741*f005ef32Sjsg 	INIT_DELAYED_WORK(&i915->display.hotplug.hotplug_work,
742c349dbc7Sjsg 			  i915_hotplug_work_func);
743*f005ef32Sjsg 	INIT_WORK(&i915->display.hotplug.dig_port_work, i915_digport_work_func);
744*f005ef32Sjsg 	INIT_WORK(&i915->display.hotplug.poll_init_work, i915_hpd_poll_init_work);
745*f005ef32Sjsg 	INIT_DELAYED_WORK(&i915->display.hotplug.reenable_work,
746c349dbc7Sjsg 			  intel_hpd_irq_storm_reenable_work);
747*f005ef32Sjsg 
748*f005ef32Sjsg 	i915->display.hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
749*f005ef32Sjsg 	/* If we have MST support, we want to avoid doing short HPD IRQ storm
750*f005ef32Sjsg 	 * detection, as short HPD storms will occur as a natural part of
751*f005ef32Sjsg 	 * sideband messaging with MST.
752*f005ef32Sjsg 	 * On older platforms however, IRQ storms can occur with both long and
753*f005ef32Sjsg 	 * short pulses, as seen on some G4x systems.
754*f005ef32Sjsg 	 */
755*f005ef32Sjsg 	i915->display.hotplug.hpd_short_storm_enabled = !HAS_DP_MST(i915);
756c349dbc7Sjsg }
757c349dbc7Sjsg 
intel_hpd_cancel_work(struct drm_i915_private * dev_priv)758c349dbc7Sjsg void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
759c349dbc7Sjsg {
7605ca02815Sjsg 	if (!HAS_DISPLAY(dev_priv))
7615ca02815Sjsg 		return;
7625ca02815Sjsg 
763c349dbc7Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
764c349dbc7Sjsg 
7651bb76ff1Sjsg 	dev_priv->display.hotplug.long_port_mask = 0;
7661bb76ff1Sjsg 	dev_priv->display.hotplug.short_port_mask = 0;
7671bb76ff1Sjsg 	dev_priv->display.hotplug.event_bits = 0;
7681bb76ff1Sjsg 	dev_priv->display.hotplug.retry_bits = 0;
769c349dbc7Sjsg 
770c349dbc7Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
771c349dbc7Sjsg 
7721bb76ff1Sjsg 	cancel_work_sync(&dev_priv->display.hotplug.dig_port_work);
7731bb76ff1Sjsg 	cancel_delayed_work_sync(&dev_priv->display.hotplug.hotplug_work);
7741bb76ff1Sjsg 	cancel_work_sync(&dev_priv->display.hotplug.poll_init_work);
7751bb76ff1Sjsg 	cancel_delayed_work_sync(&dev_priv->display.hotplug.reenable_work);
776c349dbc7Sjsg }
777c349dbc7Sjsg 
intel_hpd_disable(struct drm_i915_private * dev_priv,enum hpd_pin pin)778c349dbc7Sjsg bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
779c349dbc7Sjsg {
780c349dbc7Sjsg 	bool ret = false;
781c349dbc7Sjsg 
782c349dbc7Sjsg 	if (pin == HPD_NONE)
783c349dbc7Sjsg 		return false;
784c349dbc7Sjsg 
785c349dbc7Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
7861bb76ff1Sjsg 	if (dev_priv->display.hotplug.stats[pin].state == HPD_ENABLED) {
7871bb76ff1Sjsg 		dev_priv->display.hotplug.stats[pin].state = HPD_DISABLED;
788c349dbc7Sjsg 		ret = true;
789c349dbc7Sjsg 	}
790c349dbc7Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
791c349dbc7Sjsg 
792c349dbc7Sjsg 	return ret;
793c349dbc7Sjsg }
794c349dbc7Sjsg 
intel_hpd_enable(struct drm_i915_private * dev_priv,enum hpd_pin pin)795c349dbc7Sjsg void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
796c349dbc7Sjsg {
797c349dbc7Sjsg 	if (pin == HPD_NONE)
798c349dbc7Sjsg 		return;
799c349dbc7Sjsg 
800c349dbc7Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
8011bb76ff1Sjsg 	dev_priv->display.hotplug.stats[pin].state = HPD_ENABLED;
802c349dbc7Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
803c349dbc7Sjsg }
804*f005ef32Sjsg 
i915_hpd_storm_ctl_show(struct seq_file * m,void * data)805*f005ef32Sjsg static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
806*f005ef32Sjsg {
807*f005ef32Sjsg 	struct drm_i915_private *dev_priv = m->private;
808*f005ef32Sjsg 	struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
809*f005ef32Sjsg 
810*f005ef32Sjsg 	/* Synchronize with everything first in case there's been an HPD
811*f005ef32Sjsg 	 * storm, but we haven't finished handling it in the kernel yet
812*f005ef32Sjsg 	 */
813*f005ef32Sjsg 	intel_synchronize_irq(dev_priv);
814*f005ef32Sjsg 	flush_work(&dev_priv->display.hotplug.dig_port_work);
815*f005ef32Sjsg 	flush_delayed_work(&dev_priv->display.hotplug.hotplug_work);
816*f005ef32Sjsg 
817*f005ef32Sjsg 	seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
818*f005ef32Sjsg 	seq_printf(m, "Detected: %s\n",
819*f005ef32Sjsg 		   str_yes_no(delayed_work_pending(&hotplug->reenable_work)));
820*f005ef32Sjsg 
821*f005ef32Sjsg 	return 0;
822*f005ef32Sjsg }
823*f005ef32Sjsg 
824*f005ef32Sjsg #ifdef notyet
825*f005ef32Sjsg 
i915_hpd_storm_ctl_write(struct file * file,const char __user * ubuf,size_t len,loff_t * offp)826*f005ef32Sjsg static ssize_t i915_hpd_storm_ctl_write(struct file *file,
827*f005ef32Sjsg 					const char __user *ubuf, size_t len,
828*f005ef32Sjsg 					loff_t *offp)
829*f005ef32Sjsg {
830*f005ef32Sjsg 	struct seq_file *m = file->private_data;
831*f005ef32Sjsg 	struct drm_i915_private *dev_priv = m->private;
832*f005ef32Sjsg 	struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
833*f005ef32Sjsg 	unsigned int new_threshold;
834*f005ef32Sjsg 	int i;
835*f005ef32Sjsg 	char *newline;
836*f005ef32Sjsg 	char tmp[16];
837*f005ef32Sjsg 
838*f005ef32Sjsg 	if (len >= sizeof(tmp))
839*f005ef32Sjsg 		return -EINVAL;
840*f005ef32Sjsg 
841*f005ef32Sjsg 	if (copy_from_user(tmp, ubuf, len))
842*f005ef32Sjsg 		return -EFAULT;
843*f005ef32Sjsg 
844*f005ef32Sjsg 	tmp[len] = '\0';
845*f005ef32Sjsg 
846*f005ef32Sjsg 	/* Strip newline, if any */
847*f005ef32Sjsg 	newline = strchr(tmp, '\n');
848*f005ef32Sjsg 	if (newline)
849*f005ef32Sjsg 		*newline = '\0';
850*f005ef32Sjsg 
851*f005ef32Sjsg 	if (strcmp(tmp, "reset") == 0)
852*f005ef32Sjsg 		new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
853*f005ef32Sjsg 	else if (kstrtouint(tmp, 10, &new_threshold) != 0)
854*f005ef32Sjsg 		return -EINVAL;
855*f005ef32Sjsg 
856*f005ef32Sjsg 	if (new_threshold > 0)
857*f005ef32Sjsg 		drm_dbg_kms(&dev_priv->drm,
858*f005ef32Sjsg 			    "Setting HPD storm detection threshold to %d\n",
859*f005ef32Sjsg 			    new_threshold);
860*f005ef32Sjsg 	else
861*f005ef32Sjsg 		drm_dbg_kms(&dev_priv->drm, "Disabling HPD storm detection\n");
862*f005ef32Sjsg 
863*f005ef32Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
864*f005ef32Sjsg 	hotplug->hpd_storm_threshold = new_threshold;
865*f005ef32Sjsg 	/* Reset the HPD storm stats so we don't accidentally trigger a storm */
866*f005ef32Sjsg 	for_each_hpd_pin(i)
867*f005ef32Sjsg 		hotplug->stats[i].count = 0;
868*f005ef32Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
869*f005ef32Sjsg 
870*f005ef32Sjsg 	/* Re-enable hpd immediately if we were in an irq storm */
871*f005ef32Sjsg 	flush_delayed_work(&dev_priv->display.hotplug.reenable_work);
872*f005ef32Sjsg 
873*f005ef32Sjsg 	return len;
874*f005ef32Sjsg }
875*f005ef32Sjsg 
i915_hpd_storm_ctl_open(struct inode * inode,struct file * file)876*f005ef32Sjsg static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
877*f005ef32Sjsg {
878*f005ef32Sjsg 	return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
879*f005ef32Sjsg }
880*f005ef32Sjsg 
881*f005ef32Sjsg static const struct file_operations i915_hpd_storm_ctl_fops = {
882*f005ef32Sjsg 	.owner = THIS_MODULE,
883*f005ef32Sjsg 	.open = i915_hpd_storm_ctl_open,
884*f005ef32Sjsg 	.read = seq_read,
885*f005ef32Sjsg 	.llseek = seq_lseek,
886*f005ef32Sjsg 	.release = single_release,
887*f005ef32Sjsg 	.write = i915_hpd_storm_ctl_write
888*f005ef32Sjsg };
889*f005ef32Sjsg 
i915_hpd_short_storm_ctl_show(struct seq_file * m,void * data)890*f005ef32Sjsg static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data)
891*f005ef32Sjsg {
892*f005ef32Sjsg 	struct drm_i915_private *dev_priv = m->private;
893*f005ef32Sjsg 
894*f005ef32Sjsg 	seq_printf(m, "Enabled: %s\n",
895*f005ef32Sjsg 		   str_yes_no(dev_priv->display.hotplug.hpd_short_storm_enabled));
896*f005ef32Sjsg 
897*f005ef32Sjsg 	return 0;
898*f005ef32Sjsg }
899*f005ef32Sjsg 
900*f005ef32Sjsg static int
i915_hpd_short_storm_ctl_open(struct inode * inode,struct file * file)901*f005ef32Sjsg i915_hpd_short_storm_ctl_open(struct inode *inode, struct file *file)
902*f005ef32Sjsg {
903*f005ef32Sjsg 	return single_open(file, i915_hpd_short_storm_ctl_show,
904*f005ef32Sjsg 			   inode->i_private);
905*f005ef32Sjsg }
906*f005ef32Sjsg 
i915_hpd_short_storm_ctl_write(struct file * file,const char __user * ubuf,size_t len,loff_t * offp)907*f005ef32Sjsg static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
908*f005ef32Sjsg 					      const char __user *ubuf,
909*f005ef32Sjsg 					      size_t len, loff_t *offp)
910*f005ef32Sjsg {
911*f005ef32Sjsg 	struct seq_file *m = file->private_data;
912*f005ef32Sjsg 	struct drm_i915_private *dev_priv = m->private;
913*f005ef32Sjsg 	struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
914*f005ef32Sjsg 	char *newline;
915*f005ef32Sjsg 	char tmp[16];
916*f005ef32Sjsg 	int i;
917*f005ef32Sjsg 	bool new_state;
918*f005ef32Sjsg 
919*f005ef32Sjsg 	if (len >= sizeof(tmp))
920*f005ef32Sjsg 		return -EINVAL;
921*f005ef32Sjsg 
922*f005ef32Sjsg 	if (copy_from_user(tmp, ubuf, len))
923*f005ef32Sjsg 		return -EFAULT;
924*f005ef32Sjsg 
925*f005ef32Sjsg 	tmp[len] = '\0';
926*f005ef32Sjsg 
927*f005ef32Sjsg 	/* Strip newline, if any */
928*f005ef32Sjsg 	newline = strchr(tmp, '\n');
929*f005ef32Sjsg 	if (newline)
930*f005ef32Sjsg 		*newline = '\0';
931*f005ef32Sjsg 
932*f005ef32Sjsg 	/* Reset to the "default" state for this system */
933*f005ef32Sjsg 	if (strcmp(tmp, "reset") == 0)
934*f005ef32Sjsg 		new_state = !HAS_DP_MST(dev_priv);
935*f005ef32Sjsg 	else if (kstrtobool(tmp, &new_state) != 0)
936*f005ef32Sjsg 		return -EINVAL;
937*f005ef32Sjsg 
938*f005ef32Sjsg 	drm_dbg_kms(&dev_priv->drm, "%sabling HPD short storm detection\n",
939*f005ef32Sjsg 		    new_state ? "En" : "Dis");
940*f005ef32Sjsg 
941*f005ef32Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
942*f005ef32Sjsg 	hotplug->hpd_short_storm_enabled = new_state;
943*f005ef32Sjsg 	/* Reset the HPD storm stats so we don't accidentally trigger a storm */
944*f005ef32Sjsg 	for_each_hpd_pin(i)
945*f005ef32Sjsg 		hotplug->stats[i].count = 0;
946*f005ef32Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
947*f005ef32Sjsg 
948*f005ef32Sjsg 	/* Re-enable hpd immediately if we were in an irq storm */
949*f005ef32Sjsg 	flush_delayed_work(&dev_priv->display.hotplug.reenable_work);
950*f005ef32Sjsg 
951*f005ef32Sjsg 	return len;
952*f005ef32Sjsg }
953*f005ef32Sjsg 
954*f005ef32Sjsg static const struct file_operations i915_hpd_short_storm_ctl_fops = {
955*f005ef32Sjsg 	.owner = THIS_MODULE,
956*f005ef32Sjsg 	.open = i915_hpd_short_storm_ctl_open,
957*f005ef32Sjsg 	.read = seq_read,
958*f005ef32Sjsg 	.llseek = seq_lseek,
959*f005ef32Sjsg 	.release = single_release,
960*f005ef32Sjsg 	.write = i915_hpd_short_storm_ctl_write,
961*f005ef32Sjsg };
962*f005ef32Sjsg 
963*f005ef32Sjsg #endif /* notyet */
964*f005ef32Sjsg 
intel_hpd_debugfs_register(struct drm_i915_private * i915)965*f005ef32Sjsg void intel_hpd_debugfs_register(struct drm_i915_private *i915)
966*f005ef32Sjsg {
967*f005ef32Sjsg 	struct drm_minor *minor = i915->drm.primary;
968*f005ef32Sjsg 
969*f005ef32Sjsg 	debugfs_create_file("i915_hpd_storm_ctl", 0644, minor->debugfs_root,
970*f005ef32Sjsg 			    i915, &i915_hpd_storm_ctl_fops);
971*f005ef32Sjsg 	debugfs_create_file("i915_hpd_short_storm_ctl", 0644, minor->debugfs_root,
972*f005ef32Sjsg 			    i915, &i915_hpd_short_storm_ctl_fops);
973*f005ef32Sjsg 	debugfs_create_bool("i915_ignore_long_hpd", 0644, minor->debugfs_root,
974*f005ef32Sjsg 			    &i915->display.hotplug.ignore_long_hpd);
975*f005ef32Sjsg }
976