1*c349dbc7Sjsg /*
2*c349dbc7Sjsg  * Copyright © 2015 Intel Corporation
3*c349dbc7Sjsg  *
4*c349dbc7Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
5*c349dbc7Sjsg  * copy of this software and associated documentation files (the "Software"),
6*c349dbc7Sjsg  * to deal in the Software without restriction, including without limitation
7*c349dbc7Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*c349dbc7Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
9*c349dbc7Sjsg  * Software is furnished to do so, subject to the following conditions:
10*c349dbc7Sjsg  *
11*c349dbc7Sjsg  * The above copyright notice and this permission notice (including the next
12*c349dbc7Sjsg  * paragraph) shall be included in all copies or substantial portions of the
13*c349dbc7Sjsg  * Software.
14*c349dbc7Sjsg  *
15*c349dbc7Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16*c349dbc7Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17*c349dbc7Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18*c349dbc7Sjsg  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19*c349dbc7Sjsg  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20*c349dbc7Sjsg  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21*c349dbc7Sjsg  * IN THE SOFTWARE.
22*c349dbc7Sjsg  */
23*c349dbc7Sjsg 
24*c349dbc7Sjsg #include <linux/kernel.h>
25*c349dbc7Sjsg 
26*c349dbc7Sjsg #include "i915_drv.h"
27*c349dbc7Sjsg #include "intel_display_types.h"
28*c349dbc7Sjsg #include "intel_hotplug.h"
29*c349dbc7Sjsg 
30*c349dbc7Sjsg /**
31*c349dbc7Sjsg  * DOC: Hotplug
32*c349dbc7Sjsg  *
33*c349dbc7Sjsg  * Simply put, hotplug occurs when a display is connected to or disconnected
34*c349dbc7Sjsg  * from the system. However, there may be adapters and docking stations and
35*c349dbc7Sjsg  * Display Port short pulses and MST devices involved, complicating matters.
36*c349dbc7Sjsg  *
37*c349dbc7Sjsg  * Hotplug in i915 is handled in many different levels of abstraction.
38*c349dbc7Sjsg  *
39*c349dbc7Sjsg  * The platform dependent interrupt handling code in i915_irq.c enables,
40*c349dbc7Sjsg  * disables, and does preliminary handling of the interrupts. The interrupt
41*c349dbc7Sjsg  * handlers gather the hotplug detect (HPD) information from relevant registers
42*c349dbc7Sjsg  * into a platform independent mask of hotplug pins that have fired.
43*c349dbc7Sjsg  *
44*c349dbc7Sjsg  * The platform independent interrupt handler intel_hpd_irq_handler() in
45*c349dbc7Sjsg  * intel_hotplug.c does hotplug irq storm detection and mitigation, and passes
46*c349dbc7Sjsg  * further processing to appropriate bottom halves (Display Port specific and
47*c349dbc7Sjsg  * regular hotplug).
48*c349dbc7Sjsg  *
49*c349dbc7Sjsg  * The Display Port work function i915_digport_work_func() calls into
50*c349dbc7Sjsg  * intel_dp_hpd_pulse() via hooks, which handles DP short pulses and DP MST long
51*c349dbc7Sjsg  * pulses, with failures and non-MST long pulses triggering regular hotplug
52*c349dbc7Sjsg  * processing on the connector.
53*c349dbc7Sjsg  *
54*c349dbc7Sjsg  * The regular hotplug work function i915_hotplug_work_func() calls connector
55*c349dbc7Sjsg  * detect hooks, and, if connector status changes, triggers sending of hotplug
56*c349dbc7Sjsg  * uevent to userspace via drm_kms_helper_hotplug_event().
57*c349dbc7Sjsg  *
58*c349dbc7Sjsg  * Finally, the userspace is responsible for triggering a modeset upon receiving
59*c349dbc7Sjsg  * the hotplug uevent, disabling or enabling the crtc as needed.
60*c349dbc7Sjsg  *
61*c349dbc7Sjsg  * The hotplug interrupt storm detection and mitigation code keeps track of the
62*c349dbc7Sjsg  * number of interrupts per hotplug pin per a period of time, and if the number
63*c349dbc7Sjsg  * of interrupts exceeds a certain threshold, the interrupt is disabled for a
64*c349dbc7Sjsg  * while before being re-enabled. The intention is to mitigate issues raising
65*c349dbc7Sjsg  * from broken hardware triggering massive amounts of interrupts and grinding
66*c349dbc7Sjsg  * the system to a halt.
67*c349dbc7Sjsg  *
68*c349dbc7Sjsg  * Current implementation expects that hotplug interrupt storm will not be
69*c349dbc7Sjsg  * seen when display port sink is connected, hence on platforms whose DP
70*c349dbc7Sjsg  * callback is handled by i915_digport_work_func reenabling of hpd is not
71*c349dbc7Sjsg  * performed (it was never expected to be disabled in the first place ;) )
72*c349dbc7Sjsg  * this is specific to DP sinks handled by this routine and any other display
73*c349dbc7Sjsg  * such as HDMI or DVI enabled on the same port will have proper logic since
74*c349dbc7Sjsg  * it will use i915_hotplug_work_func where this logic is handled.
75*c349dbc7Sjsg  */
76*c349dbc7Sjsg 
77*c349dbc7Sjsg /**
78*c349dbc7Sjsg  * intel_hpd_pin_default - return default pin associated with certain port.
79*c349dbc7Sjsg  * @dev_priv: private driver data pointer
80*c349dbc7Sjsg  * @port: the hpd port to get associated pin
81*c349dbc7Sjsg  *
82*c349dbc7Sjsg  * It is only valid and used by digital port encoder.
83*c349dbc7Sjsg  *
84*c349dbc7Sjsg  * Return pin that is associatade with @port and HDP_NONE if no pin is
85*c349dbc7Sjsg  * hard associated with that @port.
86*c349dbc7Sjsg  */
87*c349dbc7Sjsg enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
88*c349dbc7Sjsg 				   enum port port)
89*c349dbc7Sjsg {
90*c349dbc7Sjsg 	enum phy phy = intel_port_to_phy(dev_priv, port);
91*c349dbc7Sjsg 
92*c349dbc7Sjsg 	switch (phy) {
93*c349dbc7Sjsg 	case PHY_F:
94*c349dbc7Sjsg 		return IS_CNL_WITH_PORT_F(dev_priv) ? HPD_PORT_E : HPD_PORT_F;
95*c349dbc7Sjsg 	case PHY_A ... PHY_E:
96*c349dbc7Sjsg 	case PHY_G ... PHY_I:
97*c349dbc7Sjsg 		return HPD_PORT_A + phy - PHY_A;
98*c349dbc7Sjsg 	default:
99*c349dbc7Sjsg 		MISSING_CASE(phy);
100*c349dbc7Sjsg 		return HPD_NONE;
101*c349dbc7Sjsg 	}
102*c349dbc7Sjsg }
103*c349dbc7Sjsg 
104*c349dbc7Sjsg #define HPD_STORM_DETECT_PERIOD		1000
105*c349dbc7Sjsg #define HPD_STORM_REENABLE_DELAY	(2 * 60 * 1000)
106*c349dbc7Sjsg #define HPD_RETRY_DELAY			1000
107*c349dbc7Sjsg 
108*c349dbc7Sjsg static enum hpd_pin
109*c349dbc7Sjsg intel_connector_hpd_pin(struct intel_connector *connector)
110*c349dbc7Sjsg {
111*c349dbc7Sjsg 	struct intel_encoder *encoder = intel_attached_encoder(connector);
112*c349dbc7Sjsg 
113*c349dbc7Sjsg 	/*
114*c349dbc7Sjsg 	 * MST connectors get their encoder attached dynamically
115*c349dbc7Sjsg 	 * so need to make sure we have an encoder here. But since
116*c349dbc7Sjsg 	 * MST encoders have their hpd_pin set to HPD_NONE we don't
117*c349dbc7Sjsg 	 * have to special case them beyond that.
118*c349dbc7Sjsg 	 */
119*c349dbc7Sjsg 	return encoder ? encoder->hpd_pin : HPD_NONE;
120*c349dbc7Sjsg }
121*c349dbc7Sjsg 
122*c349dbc7Sjsg /**
123*c349dbc7Sjsg  * intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ storm on a pin
124*c349dbc7Sjsg  * @dev_priv: private driver data pointer
125*c349dbc7Sjsg  * @pin: the pin to gather stats on
126*c349dbc7Sjsg  * @long_hpd: whether the HPD IRQ was long or short
127*c349dbc7Sjsg  *
128*c349dbc7Sjsg  * Gather stats about HPD IRQs from the specified @pin, and detect IRQ
129*c349dbc7Sjsg  * storms. Only the pin specific stats and state are changed, the caller is
130*c349dbc7Sjsg  * responsible for further action.
131*c349dbc7Sjsg  *
132*c349dbc7Sjsg  * The number of IRQs that are allowed within @HPD_STORM_DETECT_PERIOD is
133*c349dbc7Sjsg  * stored in @dev_priv->hotplug.hpd_storm_threshold which defaults to
134*c349dbc7Sjsg  * @HPD_STORM_DEFAULT_THRESHOLD. Long IRQs count as +10 to this threshold, and
135*c349dbc7Sjsg  * short IRQs count as +1. If this threshold is exceeded, it's considered an
136*c349dbc7Sjsg  * IRQ storm and the IRQ state is set to @HPD_MARK_DISABLED.
137*c349dbc7Sjsg  *
138*c349dbc7Sjsg  * By default, most systems will only count long IRQs towards
139*c349dbc7Sjsg  * &dev_priv->hotplug.hpd_storm_threshold. However, some older systems also
140*c349dbc7Sjsg  * suffer from short IRQ storms and must also track these. Because short IRQ
141*c349dbc7Sjsg  * storms are naturally caused by sideband interactions with DP MST devices,
142*c349dbc7Sjsg  * short IRQ detection is only enabled for systems without DP MST support.
143*c349dbc7Sjsg  * Systems which are new enough to support DP MST are far less likely to
144*c349dbc7Sjsg  * suffer from IRQ storms at all, so this is fine.
145*c349dbc7Sjsg  *
146*c349dbc7Sjsg  * The HPD threshold can be controlled through i915_hpd_storm_ctl in debugfs,
147*c349dbc7Sjsg  * and should only be adjusted for automated hotplug testing.
148*c349dbc7Sjsg  *
149*c349dbc7Sjsg  * Return true if an IRQ storm was detected on @pin.
150*c349dbc7Sjsg  */
151*c349dbc7Sjsg static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
152*c349dbc7Sjsg 				       enum hpd_pin pin, bool long_hpd)
153*c349dbc7Sjsg {
154*c349dbc7Sjsg 	struct i915_hotplug *hpd = &dev_priv->hotplug;
155*c349dbc7Sjsg 	unsigned long start = hpd->stats[pin].last_jiffies;
156*c349dbc7Sjsg 	unsigned long end = start + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD);
157*c349dbc7Sjsg 	const int increment = long_hpd ? 10 : 1;
158*c349dbc7Sjsg 	const int threshold = hpd->hpd_storm_threshold;
159*c349dbc7Sjsg 	bool storm = false;
160*c349dbc7Sjsg 
161*c349dbc7Sjsg 	if (!threshold ||
162*c349dbc7Sjsg 	    (!long_hpd && !dev_priv->hotplug.hpd_short_storm_enabled))
163*c349dbc7Sjsg 		return false;
164*c349dbc7Sjsg 
165*c349dbc7Sjsg 	if (!time_in_range(jiffies, start, end)) {
166*c349dbc7Sjsg 		hpd->stats[pin].last_jiffies = jiffies;
167*c349dbc7Sjsg 		hpd->stats[pin].count = 0;
168*c349dbc7Sjsg 	}
169*c349dbc7Sjsg 
170*c349dbc7Sjsg 	hpd->stats[pin].count += increment;
171*c349dbc7Sjsg 	if (hpd->stats[pin].count > threshold) {
172*c349dbc7Sjsg 		hpd->stats[pin].state = HPD_MARK_DISABLED;
173*c349dbc7Sjsg 		drm_dbg_kms(&dev_priv->drm,
174*c349dbc7Sjsg 			    "HPD interrupt storm detected on PIN %d\n", pin);
175*c349dbc7Sjsg 		storm = true;
176*c349dbc7Sjsg 	} else {
177*c349dbc7Sjsg 		drm_dbg_kms(&dev_priv->drm,
178*c349dbc7Sjsg 			    "Received HPD interrupt on PIN %d - cnt: %d\n",
179*c349dbc7Sjsg 			      pin,
180*c349dbc7Sjsg 			      hpd->stats[pin].count);
181*c349dbc7Sjsg 	}
182*c349dbc7Sjsg 
183*c349dbc7Sjsg 	return storm;
184*c349dbc7Sjsg }
185*c349dbc7Sjsg 
186*c349dbc7Sjsg static void
187*c349dbc7Sjsg intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
188*c349dbc7Sjsg {
189*c349dbc7Sjsg 	struct drm_device *dev = &dev_priv->drm;
190*c349dbc7Sjsg 	struct drm_connector_list_iter conn_iter;
191*c349dbc7Sjsg 	struct intel_connector *connector;
192*c349dbc7Sjsg 	bool hpd_disabled = false;
193*c349dbc7Sjsg 
194*c349dbc7Sjsg 	lockdep_assert_held(&dev_priv->irq_lock);
195*c349dbc7Sjsg 
196*c349dbc7Sjsg 	drm_connector_list_iter_begin(dev, &conn_iter);
197*c349dbc7Sjsg 	for_each_intel_connector_iter(connector, &conn_iter) {
198*c349dbc7Sjsg 		enum hpd_pin pin;
199*c349dbc7Sjsg 
200*c349dbc7Sjsg 		if (connector->base.polled != DRM_CONNECTOR_POLL_HPD)
201*c349dbc7Sjsg 			continue;
202*c349dbc7Sjsg 
203*c349dbc7Sjsg 		pin = intel_connector_hpd_pin(connector);
204*c349dbc7Sjsg 		if (pin == HPD_NONE ||
205*c349dbc7Sjsg 		    dev_priv->hotplug.stats[pin].state != HPD_MARK_DISABLED)
206*c349dbc7Sjsg 			continue;
207*c349dbc7Sjsg 
208*c349dbc7Sjsg 		drm_info(&dev_priv->drm,
209*c349dbc7Sjsg 			 "HPD interrupt storm detected on connector %s: "
210*c349dbc7Sjsg 			 "switching from hotplug detection to polling\n",
211*c349dbc7Sjsg 			 connector->base.name);
212*c349dbc7Sjsg 
213*c349dbc7Sjsg 		dev_priv->hotplug.stats[pin].state = HPD_DISABLED;
214*c349dbc7Sjsg 		connector->base.polled = DRM_CONNECTOR_POLL_CONNECT |
215*c349dbc7Sjsg 			DRM_CONNECTOR_POLL_DISCONNECT;
216*c349dbc7Sjsg 		hpd_disabled = true;
217*c349dbc7Sjsg 	}
218*c349dbc7Sjsg 	drm_connector_list_iter_end(&conn_iter);
219*c349dbc7Sjsg 
220*c349dbc7Sjsg 	/* Enable polling and queue hotplug re-enabling. */
221*c349dbc7Sjsg 	if (hpd_disabled) {
222*c349dbc7Sjsg 		drm_kms_helper_poll_enable(dev);
223*c349dbc7Sjsg 		mod_delayed_work(system_wq, &dev_priv->hotplug.reenable_work,
224*c349dbc7Sjsg 				 msecs_to_jiffies(HPD_STORM_REENABLE_DELAY));
225*c349dbc7Sjsg 	}
226*c349dbc7Sjsg }
227*c349dbc7Sjsg 
228*c349dbc7Sjsg static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
229*c349dbc7Sjsg {
230*c349dbc7Sjsg 	struct drm_i915_private *dev_priv =
231*c349dbc7Sjsg 		container_of(work, typeof(*dev_priv),
232*c349dbc7Sjsg 			     hotplug.reenable_work.work);
233*c349dbc7Sjsg 	struct drm_device *dev = &dev_priv->drm;
234*c349dbc7Sjsg 	struct drm_connector_list_iter conn_iter;
235*c349dbc7Sjsg 	struct intel_connector *connector;
236*c349dbc7Sjsg 	intel_wakeref_t wakeref;
237*c349dbc7Sjsg 	enum hpd_pin pin;
238*c349dbc7Sjsg 
239*c349dbc7Sjsg 	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
240*c349dbc7Sjsg 
241*c349dbc7Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
242*c349dbc7Sjsg 
243*c349dbc7Sjsg 	drm_connector_list_iter_begin(dev, &conn_iter);
244*c349dbc7Sjsg 	for_each_intel_connector_iter(connector, &conn_iter) {
245*c349dbc7Sjsg 		pin = intel_connector_hpd_pin(connector);
246*c349dbc7Sjsg 		if (pin == HPD_NONE ||
247*c349dbc7Sjsg 		    dev_priv->hotplug.stats[pin].state != HPD_DISABLED)
248*c349dbc7Sjsg 			continue;
249*c349dbc7Sjsg 
250*c349dbc7Sjsg 		if (connector->base.polled != connector->polled)
251*c349dbc7Sjsg 			drm_dbg(&dev_priv->drm,
252*c349dbc7Sjsg 				"Reenabling HPD on connector %s\n",
253*c349dbc7Sjsg 				connector->base.name);
254*c349dbc7Sjsg 		connector->base.polled = connector->polled;
255*c349dbc7Sjsg 	}
256*c349dbc7Sjsg 	drm_connector_list_iter_end(&conn_iter);
257*c349dbc7Sjsg 
258*c349dbc7Sjsg 	for_each_hpd_pin(pin) {
259*c349dbc7Sjsg 		if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED)
260*c349dbc7Sjsg 			dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
261*c349dbc7Sjsg 	}
262*c349dbc7Sjsg 
263*c349dbc7Sjsg 	if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup)
264*c349dbc7Sjsg 		dev_priv->display.hpd_irq_setup(dev_priv);
265*c349dbc7Sjsg 
266*c349dbc7Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
267*c349dbc7Sjsg 
268*c349dbc7Sjsg 	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
269*c349dbc7Sjsg }
270*c349dbc7Sjsg 
271*c349dbc7Sjsg enum intel_hotplug_state
272*c349dbc7Sjsg intel_encoder_hotplug(struct intel_encoder *encoder,
273*c349dbc7Sjsg 		      struct intel_connector *connector,
274*c349dbc7Sjsg 		      bool irq_received)
275*c349dbc7Sjsg {
276*c349dbc7Sjsg 	struct drm_device *dev = connector->base.dev;
277*c349dbc7Sjsg 	enum drm_connector_status old_status;
278*c349dbc7Sjsg 
279*c349dbc7Sjsg 	drm_WARN_ON(dev, !mutex_is_locked(&dev->mode_config.mutex));
280*c349dbc7Sjsg 	old_status = connector->base.status;
281*c349dbc7Sjsg 
282*c349dbc7Sjsg 	connector->base.status =
283*c349dbc7Sjsg 		drm_helper_probe_detect(&connector->base, NULL, false);
284*c349dbc7Sjsg 
285*c349dbc7Sjsg 	if (old_status == connector->base.status)
286*c349dbc7Sjsg 		return INTEL_HOTPLUG_UNCHANGED;
287*c349dbc7Sjsg 
288*c349dbc7Sjsg 	drm_dbg_kms(&to_i915(dev)->drm,
289*c349dbc7Sjsg 		    "[CONNECTOR:%d:%s] status updated from %s to %s\n",
290*c349dbc7Sjsg 		    connector->base.base.id,
291*c349dbc7Sjsg 		    connector->base.name,
292*c349dbc7Sjsg 		    drm_get_connector_status_name(old_status),
293*c349dbc7Sjsg 		    drm_get_connector_status_name(connector->base.status));
294*c349dbc7Sjsg 
295*c349dbc7Sjsg 	return INTEL_HOTPLUG_CHANGED;
296*c349dbc7Sjsg }
297*c349dbc7Sjsg 
298*c349dbc7Sjsg static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder)
299*c349dbc7Sjsg {
300*c349dbc7Sjsg 	return intel_encoder_is_dig_port(encoder) &&
301*c349dbc7Sjsg 		enc_to_dig_port(encoder)->hpd_pulse != NULL;
302*c349dbc7Sjsg }
303*c349dbc7Sjsg 
304*c349dbc7Sjsg static void i915_digport_work_func(struct work_struct *work)
305*c349dbc7Sjsg {
306*c349dbc7Sjsg 	struct drm_i915_private *dev_priv =
307*c349dbc7Sjsg 		container_of(work, struct drm_i915_private, hotplug.dig_port_work);
308*c349dbc7Sjsg 	u32 long_port_mask, short_port_mask;
309*c349dbc7Sjsg 	struct intel_encoder *encoder;
310*c349dbc7Sjsg 	u32 old_bits = 0;
311*c349dbc7Sjsg 
312*c349dbc7Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
313*c349dbc7Sjsg 	long_port_mask = dev_priv->hotplug.long_port_mask;
314*c349dbc7Sjsg 	dev_priv->hotplug.long_port_mask = 0;
315*c349dbc7Sjsg 	short_port_mask = dev_priv->hotplug.short_port_mask;
316*c349dbc7Sjsg 	dev_priv->hotplug.short_port_mask = 0;
317*c349dbc7Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
318*c349dbc7Sjsg 
319*c349dbc7Sjsg 	for_each_intel_encoder(&dev_priv->drm, encoder) {
320*c349dbc7Sjsg 		struct intel_digital_port *dig_port;
321*c349dbc7Sjsg 		enum port port = encoder->port;
322*c349dbc7Sjsg 		bool long_hpd, short_hpd;
323*c349dbc7Sjsg 		enum irqreturn ret;
324*c349dbc7Sjsg 
325*c349dbc7Sjsg 		if (!intel_encoder_has_hpd_pulse(encoder))
326*c349dbc7Sjsg 			continue;
327*c349dbc7Sjsg 
328*c349dbc7Sjsg 		long_hpd = long_port_mask & BIT(port);
329*c349dbc7Sjsg 		short_hpd = short_port_mask & BIT(port);
330*c349dbc7Sjsg 
331*c349dbc7Sjsg 		if (!long_hpd && !short_hpd)
332*c349dbc7Sjsg 			continue;
333*c349dbc7Sjsg 
334*c349dbc7Sjsg 		dig_port = enc_to_dig_port(encoder);
335*c349dbc7Sjsg 
336*c349dbc7Sjsg 		ret = dig_port->hpd_pulse(dig_port, long_hpd);
337*c349dbc7Sjsg 		if (ret == IRQ_NONE) {
338*c349dbc7Sjsg 			/* fall back to old school hpd */
339*c349dbc7Sjsg 			old_bits |= BIT(encoder->hpd_pin);
340*c349dbc7Sjsg 		}
341*c349dbc7Sjsg 	}
342*c349dbc7Sjsg 
343*c349dbc7Sjsg 	if (old_bits) {
344*c349dbc7Sjsg 		spin_lock_irq(&dev_priv->irq_lock);
345*c349dbc7Sjsg 		dev_priv->hotplug.event_bits |= old_bits;
346*c349dbc7Sjsg 		spin_unlock_irq(&dev_priv->irq_lock);
347*c349dbc7Sjsg 		queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0);
348*c349dbc7Sjsg 	}
349*c349dbc7Sjsg }
350*c349dbc7Sjsg 
351*c349dbc7Sjsg /*
352*c349dbc7Sjsg  * Handle hotplug events outside the interrupt handler proper.
353*c349dbc7Sjsg  */
354*c349dbc7Sjsg static void i915_hotplug_work_func(struct work_struct *work)
355*c349dbc7Sjsg {
356*c349dbc7Sjsg 	struct drm_i915_private *dev_priv =
357*c349dbc7Sjsg 		container_of(work, struct drm_i915_private,
358*c349dbc7Sjsg 			     hotplug.hotplug_work.work);
359*c349dbc7Sjsg 	struct drm_device *dev = &dev_priv->drm;
360*c349dbc7Sjsg 	struct drm_connector_list_iter conn_iter;
361*c349dbc7Sjsg 	struct intel_connector *connector;
362*c349dbc7Sjsg 	u32 changed = 0, retry = 0;
363*c349dbc7Sjsg 	u32 hpd_event_bits;
364*c349dbc7Sjsg 	u32 hpd_retry_bits;
365*c349dbc7Sjsg 
366*c349dbc7Sjsg 	mutex_lock(&dev->mode_config.mutex);
367*c349dbc7Sjsg 	drm_dbg_kms(&dev_priv->drm, "running encoder hotplug functions\n");
368*c349dbc7Sjsg 
369*c349dbc7Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
370*c349dbc7Sjsg 
371*c349dbc7Sjsg 	hpd_event_bits = dev_priv->hotplug.event_bits;
372*c349dbc7Sjsg 	dev_priv->hotplug.event_bits = 0;
373*c349dbc7Sjsg 	hpd_retry_bits = dev_priv->hotplug.retry_bits;
374*c349dbc7Sjsg 	dev_priv->hotplug.retry_bits = 0;
375*c349dbc7Sjsg 
376*c349dbc7Sjsg 	/* Enable polling for connectors which had HPD IRQ storms */
377*c349dbc7Sjsg 	intel_hpd_irq_storm_switch_to_polling(dev_priv);
378*c349dbc7Sjsg 
379*c349dbc7Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
380*c349dbc7Sjsg 
381*c349dbc7Sjsg 	drm_connector_list_iter_begin(dev, &conn_iter);
382*c349dbc7Sjsg 	for_each_intel_connector_iter(connector, &conn_iter) {
383*c349dbc7Sjsg 		enum hpd_pin pin;
384*c349dbc7Sjsg 		u32 hpd_bit;
385*c349dbc7Sjsg 
386*c349dbc7Sjsg 		pin = intel_connector_hpd_pin(connector);
387*c349dbc7Sjsg 		if (pin == HPD_NONE)
388*c349dbc7Sjsg 			continue;
389*c349dbc7Sjsg 
390*c349dbc7Sjsg 		hpd_bit = BIT(pin);
391*c349dbc7Sjsg 		if ((hpd_event_bits | hpd_retry_bits) & hpd_bit) {
392*c349dbc7Sjsg 			struct intel_encoder *encoder =
393*c349dbc7Sjsg 				intel_attached_encoder(connector);
394*c349dbc7Sjsg 
395*c349dbc7Sjsg 			drm_dbg_kms(&dev_priv->drm,
396*c349dbc7Sjsg 				    "Connector %s (pin %i) received hotplug event.\n",
397*c349dbc7Sjsg 				    connector->base.name, pin);
398*c349dbc7Sjsg 
399*c349dbc7Sjsg 			switch (encoder->hotplug(encoder, connector,
400*c349dbc7Sjsg 						 hpd_event_bits & hpd_bit)) {
401*c349dbc7Sjsg 			case INTEL_HOTPLUG_UNCHANGED:
402*c349dbc7Sjsg 				break;
403*c349dbc7Sjsg 			case INTEL_HOTPLUG_CHANGED:
404*c349dbc7Sjsg 				changed |= hpd_bit;
405*c349dbc7Sjsg 				break;
406*c349dbc7Sjsg 			case INTEL_HOTPLUG_RETRY:
407*c349dbc7Sjsg 				retry |= hpd_bit;
408*c349dbc7Sjsg 				break;
409*c349dbc7Sjsg 			}
410*c349dbc7Sjsg 		}
411*c349dbc7Sjsg 	}
412*c349dbc7Sjsg 	drm_connector_list_iter_end(&conn_iter);
413*c349dbc7Sjsg 	mutex_unlock(&dev->mode_config.mutex);
414*c349dbc7Sjsg 
415*c349dbc7Sjsg 	if (changed)
416*c349dbc7Sjsg 		drm_kms_helper_hotplug_event(dev);
417*c349dbc7Sjsg 
418*c349dbc7Sjsg 	/* Remove shared HPD pins that have changed */
419*c349dbc7Sjsg 	retry &= ~changed;
420*c349dbc7Sjsg 	if (retry) {
421*c349dbc7Sjsg 		spin_lock_irq(&dev_priv->irq_lock);
422*c349dbc7Sjsg 		dev_priv->hotplug.retry_bits |= retry;
423*c349dbc7Sjsg 		spin_unlock_irq(&dev_priv->irq_lock);
424*c349dbc7Sjsg 
425*c349dbc7Sjsg 		mod_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work,
426*c349dbc7Sjsg 				 msecs_to_jiffies(HPD_RETRY_DELAY));
427*c349dbc7Sjsg 	}
428*c349dbc7Sjsg }
429*c349dbc7Sjsg 
430*c349dbc7Sjsg 
431*c349dbc7Sjsg /**
432*c349dbc7Sjsg  * intel_hpd_irq_handler - main hotplug irq handler
433*c349dbc7Sjsg  * @dev_priv: drm_i915_private
434*c349dbc7Sjsg  * @pin_mask: a mask of hpd pins that have triggered the irq
435*c349dbc7Sjsg  * @long_mask: a mask of hpd pins that may be long hpd pulses
436*c349dbc7Sjsg  *
437*c349dbc7Sjsg  * This is the main hotplug irq handler for all platforms. The platform specific
438*c349dbc7Sjsg  * irq handlers call the platform specific hotplug irq handlers, which read and
439*c349dbc7Sjsg  * decode the appropriate registers into bitmasks about hpd pins that have
440*c349dbc7Sjsg  * triggered (@pin_mask), and which of those pins may be long pulses
441*c349dbc7Sjsg  * (@long_mask). The @long_mask is ignored if the port corresponding to the pin
442*c349dbc7Sjsg  * is not a digital port.
443*c349dbc7Sjsg  *
444*c349dbc7Sjsg  * Here, we do hotplug irq storm detection and mitigation, and pass further
445*c349dbc7Sjsg  * processing to appropriate bottom halves.
446*c349dbc7Sjsg  */
447*c349dbc7Sjsg void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
448*c349dbc7Sjsg 			   u32 pin_mask, u32 long_mask)
449*c349dbc7Sjsg {
450*c349dbc7Sjsg 	struct intel_encoder *encoder;
451*c349dbc7Sjsg 	bool storm_detected = false;
452*c349dbc7Sjsg 	bool queue_dig = false, queue_hp = false;
453*c349dbc7Sjsg 	u32 long_hpd_pulse_mask = 0;
454*c349dbc7Sjsg 	u32 short_hpd_pulse_mask = 0;
455*c349dbc7Sjsg 	enum hpd_pin pin;
456*c349dbc7Sjsg 
457*c349dbc7Sjsg 	if (!pin_mask)
458*c349dbc7Sjsg 		return;
459*c349dbc7Sjsg 
460*c349dbc7Sjsg 	spin_lock(&dev_priv->irq_lock);
461*c349dbc7Sjsg 
462*c349dbc7Sjsg 	/*
463*c349dbc7Sjsg 	 * Determine whether ->hpd_pulse() exists for each pin, and
464*c349dbc7Sjsg 	 * whether we have a short or a long pulse. This is needed
465*c349dbc7Sjsg 	 * as each pin may have up to two encoders (HDMI and DP) and
466*c349dbc7Sjsg 	 * only the one of them (DP) will have ->hpd_pulse().
467*c349dbc7Sjsg 	 */
468*c349dbc7Sjsg 	for_each_intel_encoder(&dev_priv->drm, encoder) {
469*c349dbc7Sjsg 		bool has_hpd_pulse = intel_encoder_has_hpd_pulse(encoder);
470*c349dbc7Sjsg 		enum port port = encoder->port;
471*c349dbc7Sjsg 		bool long_hpd;
472*c349dbc7Sjsg 
473*c349dbc7Sjsg 		pin = encoder->hpd_pin;
474*c349dbc7Sjsg 		if (!(BIT(pin) & pin_mask))
475*c349dbc7Sjsg 			continue;
476*c349dbc7Sjsg 
477*c349dbc7Sjsg 		if (!has_hpd_pulse)
478*c349dbc7Sjsg 			continue;
479*c349dbc7Sjsg 
480*c349dbc7Sjsg 		long_hpd = long_mask & BIT(pin);
481*c349dbc7Sjsg 
482*c349dbc7Sjsg 		drm_dbg(&dev_priv->drm,
483*c349dbc7Sjsg 			"digital hpd on [ENCODER:%d:%s] - %s\n",
484*c349dbc7Sjsg 			encoder->base.base.id, encoder->base.name,
485*c349dbc7Sjsg 			long_hpd ? "long" : "short");
486*c349dbc7Sjsg 		queue_dig = true;
487*c349dbc7Sjsg 
488*c349dbc7Sjsg 		if (long_hpd) {
489*c349dbc7Sjsg 			long_hpd_pulse_mask |= BIT(pin);
490*c349dbc7Sjsg 			dev_priv->hotplug.long_port_mask |= BIT(port);
491*c349dbc7Sjsg 		} else {
492*c349dbc7Sjsg 			short_hpd_pulse_mask |= BIT(pin);
493*c349dbc7Sjsg 			dev_priv->hotplug.short_port_mask |= BIT(port);
494*c349dbc7Sjsg 		}
495*c349dbc7Sjsg 	}
496*c349dbc7Sjsg 
497*c349dbc7Sjsg 	/* Now process each pin just once */
498*c349dbc7Sjsg 	for_each_hpd_pin(pin) {
499*c349dbc7Sjsg 		bool long_hpd;
500*c349dbc7Sjsg 
501*c349dbc7Sjsg 		if (!(BIT(pin) & pin_mask))
502*c349dbc7Sjsg 			continue;
503*c349dbc7Sjsg 
504*c349dbc7Sjsg 		if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED) {
505*c349dbc7Sjsg 			/*
506*c349dbc7Sjsg 			 * On GMCH platforms the interrupt mask bits only
507*c349dbc7Sjsg 			 * prevent irq generation, not the setting of the
508*c349dbc7Sjsg 			 * hotplug bits itself. So only WARN about unexpected
509*c349dbc7Sjsg 			 * interrupts on saner platforms.
510*c349dbc7Sjsg 			 */
511*c349dbc7Sjsg 			drm_WARN_ONCE(&dev_priv->drm, !HAS_GMCH(dev_priv),
512*c349dbc7Sjsg 				      "Received HPD interrupt on pin %d although disabled\n",
513*c349dbc7Sjsg 				      pin);
514*c349dbc7Sjsg 			continue;
515*c349dbc7Sjsg 		}
516*c349dbc7Sjsg 
517*c349dbc7Sjsg 		if (dev_priv->hotplug.stats[pin].state != HPD_ENABLED)
518*c349dbc7Sjsg 			continue;
519*c349dbc7Sjsg 
520*c349dbc7Sjsg 		/*
521*c349dbc7Sjsg 		 * Delegate to ->hpd_pulse() if one of the encoders for this
522*c349dbc7Sjsg 		 * pin has it, otherwise let the hotplug_work deal with this
523*c349dbc7Sjsg 		 * pin directly.
524*c349dbc7Sjsg 		 */
525*c349dbc7Sjsg 		if (((short_hpd_pulse_mask | long_hpd_pulse_mask) & BIT(pin))) {
526*c349dbc7Sjsg 			long_hpd = long_hpd_pulse_mask & BIT(pin);
527*c349dbc7Sjsg 		} else {
528*c349dbc7Sjsg 			dev_priv->hotplug.event_bits |= BIT(pin);
529*c349dbc7Sjsg 			long_hpd = true;
530*c349dbc7Sjsg 			queue_hp = true;
531*c349dbc7Sjsg 		}
532*c349dbc7Sjsg 
533*c349dbc7Sjsg 		if (intel_hpd_irq_storm_detect(dev_priv, pin, long_hpd)) {
534*c349dbc7Sjsg 			dev_priv->hotplug.event_bits &= ~BIT(pin);
535*c349dbc7Sjsg 			storm_detected = true;
536*c349dbc7Sjsg 			queue_hp = true;
537*c349dbc7Sjsg 		}
538*c349dbc7Sjsg 	}
539*c349dbc7Sjsg 
540*c349dbc7Sjsg 	/*
541*c349dbc7Sjsg 	 * Disable any IRQs that storms were detected on. Polling enablement
542*c349dbc7Sjsg 	 * happens later in our hotplug work.
543*c349dbc7Sjsg 	 */
544*c349dbc7Sjsg 	if (storm_detected && dev_priv->display_irqs_enabled)
545*c349dbc7Sjsg 		dev_priv->display.hpd_irq_setup(dev_priv);
546*c349dbc7Sjsg 	spin_unlock(&dev_priv->irq_lock);
547*c349dbc7Sjsg 
548*c349dbc7Sjsg 	/*
549*c349dbc7Sjsg 	 * Our hotplug handler can grab modeset locks (by calling down into the
550*c349dbc7Sjsg 	 * fb helpers). Hence it must not be run on our own dev-priv->wq work
551*c349dbc7Sjsg 	 * queue for otherwise the flush_work in the pageflip code will
552*c349dbc7Sjsg 	 * deadlock.
553*c349dbc7Sjsg 	 */
554*c349dbc7Sjsg 	if (queue_dig)
555*c349dbc7Sjsg 		queue_work(dev_priv->hotplug.dp_wq, &dev_priv->hotplug.dig_port_work);
556*c349dbc7Sjsg 	if (queue_hp)
557*c349dbc7Sjsg 		queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0);
558*c349dbc7Sjsg }
559*c349dbc7Sjsg 
560*c349dbc7Sjsg /**
561*c349dbc7Sjsg  * intel_hpd_init - initializes and enables hpd support
562*c349dbc7Sjsg  * @dev_priv: i915 device instance
563*c349dbc7Sjsg  *
564*c349dbc7Sjsg  * This function enables the hotplug support. It requires that interrupts have
565*c349dbc7Sjsg  * already been enabled with intel_irq_init_hw(). From this point on hotplug and
566*c349dbc7Sjsg  * poll request can run concurrently to other code, so locking rules must be
567*c349dbc7Sjsg  * obeyed.
568*c349dbc7Sjsg  *
569*c349dbc7Sjsg  * This is a separate step from interrupt enabling to simplify the locking rules
570*c349dbc7Sjsg  * in the driver load and resume code.
571*c349dbc7Sjsg  *
572*c349dbc7Sjsg  * Also see: intel_hpd_poll_init(), which enables connector polling
573*c349dbc7Sjsg  */
574*c349dbc7Sjsg void intel_hpd_init(struct drm_i915_private *dev_priv)
575*c349dbc7Sjsg {
576*c349dbc7Sjsg 	int i;
577*c349dbc7Sjsg 
578*c349dbc7Sjsg 	for_each_hpd_pin(i) {
579*c349dbc7Sjsg 		dev_priv->hotplug.stats[i].count = 0;
580*c349dbc7Sjsg 		dev_priv->hotplug.stats[i].state = HPD_ENABLED;
581*c349dbc7Sjsg 	}
582*c349dbc7Sjsg 
583*c349dbc7Sjsg 	WRITE_ONCE(dev_priv->hotplug.poll_enabled, false);
584*c349dbc7Sjsg 	schedule_work(&dev_priv->hotplug.poll_init_work);
585*c349dbc7Sjsg 
586*c349dbc7Sjsg 	/*
587*c349dbc7Sjsg 	 * Interrupt setup is already guaranteed to be single-threaded, this is
588*c349dbc7Sjsg 	 * just to make the assert_spin_locked checks happy.
589*c349dbc7Sjsg 	 */
590*c349dbc7Sjsg 	if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup) {
591*c349dbc7Sjsg 		spin_lock_irq(&dev_priv->irq_lock);
592*c349dbc7Sjsg 		if (dev_priv->display_irqs_enabled)
593*c349dbc7Sjsg 			dev_priv->display.hpd_irq_setup(dev_priv);
594*c349dbc7Sjsg 		spin_unlock_irq(&dev_priv->irq_lock);
595*c349dbc7Sjsg 	}
596*c349dbc7Sjsg }
597*c349dbc7Sjsg 
598*c349dbc7Sjsg static void i915_hpd_poll_init_work(struct work_struct *work)
599*c349dbc7Sjsg {
600*c349dbc7Sjsg 	struct drm_i915_private *dev_priv =
601*c349dbc7Sjsg 		container_of(work, struct drm_i915_private,
602*c349dbc7Sjsg 			     hotplug.poll_init_work);
603*c349dbc7Sjsg 	struct drm_device *dev = &dev_priv->drm;
604*c349dbc7Sjsg 	struct drm_connector_list_iter conn_iter;
605*c349dbc7Sjsg 	struct intel_connector *connector;
606*c349dbc7Sjsg 	bool enabled;
607*c349dbc7Sjsg 
608*c349dbc7Sjsg 	mutex_lock(&dev->mode_config.mutex);
609*c349dbc7Sjsg 
610*c349dbc7Sjsg 	enabled = READ_ONCE(dev_priv->hotplug.poll_enabled);
611*c349dbc7Sjsg 
612*c349dbc7Sjsg 	drm_connector_list_iter_begin(dev, &conn_iter);
613*c349dbc7Sjsg 	for_each_intel_connector_iter(connector, &conn_iter) {
614*c349dbc7Sjsg 		enum hpd_pin pin;
615*c349dbc7Sjsg 
616*c349dbc7Sjsg 		pin = intel_connector_hpd_pin(connector);
617*c349dbc7Sjsg 		if (pin == HPD_NONE)
618*c349dbc7Sjsg 			continue;
619*c349dbc7Sjsg 
620*c349dbc7Sjsg 		connector->base.polled = connector->polled;
621*c349dbc7Sjsg 
622*c349dbc7Sjsg 		if (enabled && connector->base.polled == DRM_CONNECTOR_POLL_HPD)
623*c349dbc7Sjsg 			connector->base.polled = DRM_CONNECTOR_POLL_CONNECT |
624*c349dbc7Sjsg 				DRM_CONNECTOR_POLL_DISCONNECT;
625*c349dbc7Sjsg 	}
626*c349dbc7Sjsg 	drm_connector_list_iter_end(&conn_iter);
627*c349dbc7Sjsg 
628*c349dbc7Sjsg 	if (enabled)
629*c349dbc7Sjsg 		drm_kms_helper_poll_enable(dev);
630*c349dbc7Sjsg 
631*c349dbc7Sjsg 	mutex_unlock(&dev->mode_config.mutex);
632*c349dbc7Sjsg 
633*c349dbc7Sjsg 	/*
634*c349dbc7Sjsg 	 * We might have missed any hotplugs that happened while we were
635*c349dbc7Sjsg 	 * in the middle of disabling polling
636*c349dbc7Sjsg 	 */
637*c349dbc7Sjsg 	if (!enabled)
638*c349dbc7Sjsg 		drm_helper_hpd_irq_event(dev);
639*c349dbc7Sjsg }
640*c349dbc7Sjsg 
641*c349dbc7Sjsg /**
642*c349dbc7Sjsg  * intel_hpd_poll_init - enables/disables polling for connectors with hpd
643*c349dbc7Sjsg  * @dev_priv: i915 device instance
644*c349dbc7Sjsg  *
645*c349dbc7Sjsg  * This function enables polling for all connectors, regardless of whether or
646*c349dbc7Sjsg  * not they support hotplug detection. Under certain conditions HPD may not be
647*c349dbc7Sjsg  * functional. On most Intel GPUs, this happens when we enter runtime suspend.
648*c349dbc7Sjsg  * On Valleyview and Cherryview systems, this also happens when we shut off all
649*c349dbc7Sjsg  * of the powerwells.
650*c349dbc7Sjsg  *
651*c349dbc7Sjsg  * Since this function can get called in contexts where we're already holding
652*c349dbc7Sjsg  * dev->mode_config.mutex, we do the actual hotplug enabling in a seperate
653*c349dbc7Sjsg  * worker.
654*c349dbc7Sjsg  *
655*c349dbc7Sjsg  * Also see: intel_hpd_init(), which restores hpd handling.
656*c349dbc7Sjsg  */
657*c349dbc7Sjsg void intel_hpd_poll_init(struct drm_i915_private *dev_priv)
658*c349dbc7Sjsg {
659*c349dbc7Sjsg 	WRITE_ONCE(dev_priv->hotplug.poll_enabled, true);
660*c349dbc7Sjsg 
661*c349dbc7Sjsg 	/*
662*c349dbc7Sjsg 	 * We might already be holding dev->mode_config.mutex, so do this in a
663*c349dbc7Sjsg 	 * seperate worker
664*c349dbc7Sjsg 	 * As well, there's no issue if we race here since we always reschedule
665*c349dbc7Sjsg 	 * this worker anyway
666*c349dbc7Sjsg 	 */
667*c349dbc7Sjsg 	schedule_work(&dev_priv->hotplug.poll_init_work);
668*c349dbc7Sjsg }
669*c349dbc7Sjsg 
670*c349dbc7Sjsg void intel_hpd_init_work(struct drm_i915_private *dev_priv)
671*c349dbc7Sjsg {
672*c349dbc7Sjsg 	INIT_DELAYED_WORK(&dev_priv->hotplug.hotplug_work,
673*c349dbc7Sjsg 			  i915_hotplug_work_func);
674*c349dbc7Sjsg 	INIT_WORK(&dev_priv->hotplug.dig_port_work, i915_digport_work_func);
675*c349dbc7Sjsg 	INIT_WORK(&dev_priv->hotplug.poll_init_work, i915_hpd_poll_init_work);
676*c349dbc7Sjsg 	INIT_DELAYED_WORK(&dev_priv->hotplug.reenable_work,
677*c349dbc7Sjsg 			  intel_hpd_irq_storm_reenable_work);
678*c349dbc7Sjsg }
679*c349dbc7Sjsg 
680*c349dbc7Sjsg void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
681*c349dbc7Sjsg {
682*c349dbc7Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
683*c349dbc7Sjsg 
684*c349dbc7Sjsg 	dev_priv->hotplug.long_port_mask = 0;
685*c349dbc7Sjsg 	dev_priv->hotplug.short_port_mask = 0;
686*c349dbc7Sjsg 	dev_priv->hotplug.event_bits = 0;
687*c349dbc7Sjsg 	dev_priv->hotplug.retry_bits = 0;
688*c349dbc7Sjsg 
689*c349dbc7Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
690*c349dbc7Sjsg 
691*c349dbc7Sjsg 	cancel_work_sync(&dev_priv->hotplug.dig_port_work);
692*c349dbc7Sjsg 	cancel_delayed_work_sync(&dev_priv->hotplug.hotplug_work);
693*c349dbc7Sjsg 	cancel_work_sync(&dev_priv->hotplug.poll_init_work);
694*c349dbc7Sjsg 	cancel_delayed_work_sync(&dev_priv->hotplug.reenable_work);
695*c349dbc7Sjsg }
696*c349dbc7Sjsg 
697*c349dbc7Sjsg bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
698*c349dbc7Sjsg {
699*c349dbc7Sjsg 	bool ret = false;
700*c349dbc7Sjsg 
701*c349dbc7Sjsg 	if (pin == HPD_NONE)
702*c349dbc7Sjsg 		return false;
703*c349dbc7Sjsg 
704*c349dbc7Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
705*c349dbc7Sjsg 	if (dev_priv->hotplug.stats[pin].state == HPD_ENABLED) {
706*c349dbc7Sjsg 		dev_priv->hotplug.stats[pin].state = HPD_DISABLED;
707*c349dbc7Sjsg 		ret = true;
708*c349dbc7Sjsg 	}
709*c349dbc7Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
710*c349dbc7Sjsg 
711*c349dbc7Sjsg 	return ret;
712*c349dbc7Sjsg }
713*c349dbc7Sjsg 
714*c349dbc7Sjsg void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
715*c349dbc7Sjsg {
716*c349dbc7Sjsg 	if (pin == HPD_NONE)
717*c349dbc7Sjsg 		return;
718*c349dbc7Sjsg 
719*c349dbc7Sjsg 	spin_lock_irq(&dev_priv->irq_lock);
720*c349dbc7Sjsg 	dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
721*c349dbc7Sjsg 	spin_unlock_irq(&dev_priv->irq_lock);
722*c349dbc7Sjsg }
723