1*f005ef32Sjsg /* SPDX-License-Identifier: MIT */ 2*f005ef32Sjsg /* 3*f005ef32Sjsg * Copyright © 2023 Intel Corporation 4*f005ef32Sjsg */ 5*f005ef32Sjsg 6*f005ef32Sjsg #ifndef __INTEL_WM_H__ 7*f005ef32Sjsg #define __INTEL_WM_H__ 8*f005ef32Sjsg 9*f005ef32Sjsg #include <linux/types.h> 10*f005ef32Sjsg 11*f005ef32Sjsg struct drm_i915_private; 12*f005ef32Sjsg struct intel_atomic_state; 13*f005ef32Sjsg struct intel_crtc; 14*f005ef32Sjsg struct intel_crtc_state; 15*f005ef32Sjsg struct intel_plane_state; 16*f005ef32Sjsg 17*f005ef32Sjsg void intel_update_watermarks(struct drm_i915_private *i915); 18*f005ef32Sjsg int intel_compute_pipe_wm(struct intel_atomic_state *state, 19*f005ef32Sjsg struct intel_crtc *crtc); 20*f005ef32Sjsg int intel_compute_intermediate_wm(struct intel_atomic_state *state, 21*f005ef32Sjsg struct intel_crtc *crtc); 22*f005ef32Sjsg bool intel_initial_watermarks(struct intel_atomic_state *state, 23*f005ef32Sjsg struct intel_crtc *crtc); 24*f005ef32Sjsg void intel_atomic_update_watermarks(struct intel_atomic_state *state, 25*f005ef32Sjsg struct intel_crtc *crtc); 26*f005ef32Sjsg void intel_optimize_watermarks(struct intel_atomic_state *state, 27*f005ef32Sjsg struct intel_crtc *crtc); 28*f005ef32Sjsg int intel_compute_global_watermarks(struct intel_atomic_state *state); 29*f005ef32Sjsg void intel_wm_get_hw_state(struct drm_i915_private *i915); 30*f005ef32Sjsg bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state, 31*f005ef32Sjsg const struct intel_plane_state *plane_state); 32*f005ef32Sjsg void intel_print_wm_latency(struct drm_i915_private *i915, 33*f005ef32Sjsg const char *name, const u16 wm[]); 34*f005ef32Sjsg void intel_wm_init(struct drm_i915_private *i915); 35*f005ef32Sjsg void intel_wm_debugfs_register(struct drm_i915_private *i915); 36*f005ef32Sjsg 37*f005ef32Sjsg #endif /* __INTEL_WM_H__ */ 38