11bb76ff1Sjsg /* SPDX-License-Identifier: MIT */ 21bb76ff1Sjsg /* 31bb76ff1Sjsg * Copyright © 2022 Intel Corporation 41bb76ff1Sjsg */ 51bb76ff1Sjsg 61bb76ff1Sjsg #ifndef __INTEL_ENGINE_REGS__ 71bb76ff1Sjsg #define __INTEL_ENGINE_REGS__ 81bb76ff1Sjsg 91bb76ff1Sjsg #include "i915_reg_defs.h" 101bb76ff1Sjsg 111bb76ff1Sjsg #define RING_EXCC(base) _MMIO((base) + 0x28) 121bb76ff1Sjsg #define RING_TAIL(base) _MMIO((base) + 0x30) 131bb76ff1Sjsg #define TAIL_ADDR 0x001FFFF8 141bb76ff1Sjsg #define RING_HEAD(base) _MMIO((base) + 0x34) 151bb76ff1Sjsg #define HEAD_WRAP_COUNT 0xFFE00000 161bb76ff1Sjsg #define HEAD_WRAP_ONE 0x00200000 171bb76ff1Sjsg #define HEAD_ADDR 0x001FFFFC 181bb76ff1Sjsg #define RING_START(base) _MMIO((base) + 0x38) 191bb76ff1Sjsg #define RING_CTL(base) _MMIO((base) + 0x3c) 201bb76ff1Sjsg #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ 211bb76ff1Sjsg #define RING_NR_PAGES 0x001FF000 221bb76ff1Sjsg #define RING_REPORT_MASK 0x00000006 231bb76ff1Sjsg #define RING_REPORT_64K 0x00000002 241bb76ff1Sjsg #define RING_REPORT_128K 0x00000004 251bb76ff1Sjsg #define RING_NO_REPORT 0x00000000 261bb76ff1Sjsg #define RING_VALID_MASK 0x00000001 271bb76ff1Sjsg #define RING_VALID 0x00000001 281bb76ff1Sjsg #define RING_INVALID 0x00000000 291bb76ff1Sjsg #define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */ 301bb76ff1Sjsg #define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */ 311bb76ff1Sjsg #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */ 321bb76ff1Sjsg #define RING_SYNC_0(base) _MMIO((base) + 0x40) 331bb76ff1Sjsg #define RING_SYNC_1(base) _MMIO((base) + 0x44) 341bb76ff1Sjsg #define RING_SYNC_2(base) _MMIO((base) + 0x48) 351bb76ff1Sjsg #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 361bb76ff1Sjsg #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 371bb76ff1Sjsg #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 381bb76ff1Sjsg #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 391bb76ff1Sjsg #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 401bb76ff1Sjsg #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 411bb76ff1Sjsg #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 421bb76ff1Sjsg #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 431bb76ff1Sjsg #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 441bb76ff1Sjsg #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 451bb76ff1Sjsg #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 461bb76ff1Sjsg #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 471bb76ff1Sjsg #define RING_PSMI_CTL(base) _MMIO((base) + 0x50) 481bb76ff1Sjsg #define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12) 491bb76ff1Sjsg #define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10) 501bb76ff1Sjsg #define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7) 511bb76ff1Sjsg #define GEN6_BSD_GO_INDICATOR REG_BIT(4) 521bb76ff1Sjsg #define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3) 531bb76ff1Sjsg #define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2) 541bb76ff1Sjsg #define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0) 551bb76ff1Sjsg #define RING_MAX_IDLE(base) _MMIO((base) + 0x54) 561bb76ff1Sjsg #define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54) 571bb76ff1Sjsg #define IDLE_TIME_MASK 0xFFFFF 581bb76ff1Sjsg #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c) 591bb76ff1Sjsg #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */ 601bb76ff1Sjsg #define RING_IPEIR(base) _MMIO((base) + 0x64) 611bb76ff1Sjsg #define RING_IPEHR(base) _MMIO((base) + 0x68) 621bb76ff1Sjsg #define RING_INSTDONE(base) _MMIO((base) + 0x6c) 631bb76ff1Sjsg #define RING_INSTPS(base) _MMIO((base) + 0x70) 641bb76ff1Sjsg #define RING_DMA_FADD(base) _MMIO((base) + 0x78) 651bb76ff1Sjsg #define RING_ACTHD(base) _MMIO((base) + 0x74) 661bb76ff1Sjsg #define RING_HWS_PGA(base) _MMIO((base) + 0x80) 671bb76ff1Sjsg #define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84) 681bb76ff1Sjsg #define IPEIR(base) _MMIO((base) + 0x88) 691bb76ff1Sjsg #define IPEHR(base) _MMIO((base) + 0x8c) 701bb76ff1Sjsg #define RING_ID(base) _MMIO((base) + 0x8c) 711bb76ff1Sjsg #define RING_NOPID(base) _MMIO((base) + 0x94) 721bb76ff1Sjsg #define RING_HWSTAM(base) _MMIO((base) + 0x98) 731bb76ff1Sjsg #define RING_MI_MODE(base) _MMIO((base) + 0x9c) 741bb76ff1Sjsg #define ASYNC_FLIP_PERF_DISABLE REG_BIT(14) 751bb76ff1Sjsg #define MI_FLUSH_ENABLE REG_BIT(12) 761bb76ff1Sjsg #define TGL_NESTED_BB_EN REG_BIT(12) 771bb76ff1Sjsg #define MODE_IDLE REG_BIT(9) 781bb76ff1Sjsg #define STOP_RING REG_BIT(8) 791bb76ff1Sjsg #define VS_TIMER_DISPATCH REG_BIT(6) 801bb76ff1Sjsg #define RING_IMR(base) _MMIO((base) + 0xa8) 811bb76ff1Sjsg #define RING_EIR(base) _MMIO((base) + 0xb0) 821bb76ff1Sjsg #define RING_EMR(base) _MMIO((base) + 0xb4) 831bb76ff1Sjsg #define RING_ESR(base) _MMIO((base) + 0xb8) 84*f005ef32Sjsg #define GEN12_STATE_ACK_DEBUG(base) _MMIO((base) + 0xbc) 851bb76ff1Sjsg #define RING_INSTPM(base) _MMIO((base) + 0xc0) 861bb76ff1Sjsg #define RING_CMD_CCTL(base) _MMIO((base) + 0xc4) 871bb76ff1Sjsg #define ACTHD(base) _MMIO((base) + 0xc8) 881bb76ff1Sjsg #define GEN8_R_PWR_CLK_STATE(base) _MMIO((base) + 0xc8) 891bb76ff1Sjsg #define GEN8_RPCS_ENABLE (1 << 31) 901bb76ff1Sjsg #define GEN8_RPCS_S_CNT_ENABLE (1 << 18) 911bb76ff1Sjsg #define GEN8_RPCS_S_CNT_SHIFT 15 921bb76ff1Sjsg #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) 931bb76ff1Sjsg #define GEN11_RPCS_S_CNT_SHIFT 12 941bb76ff1Sjsg #define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT) 951bb76ff1Sjsg #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) 961bb76ff1Sjsg #define GEN8_RPCS_SS_CNT_SHIFT 8 971bb76ff1Sjsg #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) 981bb76ff1Sjsg #define GEN8_RPCS_EU_MAX_SHIFT 4 991bb76ff1Sjsg #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) 1001bb76ff1Sjsg #define GEN8_RPCS_EU_MIN_SHIFT 0 1011bb76ff1Sjsg #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) 1021bb76ff1Sjsg 1031bb76ff1Sjsg #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) 1041bb76ff1Sjsg #define RESET_CTL_CAT_ERROR REG_BIT(2) 1051bb76ff1Sjsg #define RESET_CTL_READY_TO_RESET REG_BIT(1) 1061bb76ff1Sjsg #define RESET_CTL_REQUEST_RESET REG_BIT(0) 1071bb76ff1Sjsg #define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0) 1081bb76ff1Sjsg #define RING_BBSTATE(base) _MMIO((base) + 0x110) 1091bb76ff1Sjsg #define RING_BB_PPGTT (1 << 5) 1101bb76ff1Sjsg #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */ 1111bb76ff1Sjsg #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */ 1121bb76ff1Sjsg #define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */ 1131bb76ff1Sjsg #define RING_BBADDR(base) _MMIO((base) + 0x140) 1141bb76ff1Sjsg #define RING_BB_OFFSET(base) _MMIO((base) + 0x158) 1151bb76ff1Sjsg #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */ 1161bb76ff1Sjsg #define CCID(base) _MMIO((base) + 0x180) 1171bb76ff1Sjsg #define CCID_EN BIT(0) 1181bb76ff1Sjsg #define CCID_EXTENDED_STATE_RESTORE BIT(2) 1191bb76ff1Sjsg #define CCID_EXTENDED_STATE_SAVE BIT(3) 1201bb76ff1Sjsg #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */ 1211bb76ff1Sjsg #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */ 1221bb76ff1Sjsg #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ 1231bb76ff1Sjsg #define ECOSKPD(base) _MMIO((base) + 0x1d0) 1241bb76ff1Sjsg #define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4) 1251bb76ff1Sjsg #define ECO_GATING_CX_ONLY REG_BIT(3) 1261bb76ff1Sjsg #define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3) 1271bb76ff1Sjsg #define ECO_FLIP_DONE REG_BIT(0) 1281bb76ff1Sjsg #define GEN6_BLITTER_LOCK_SHIFT 16 1291bb76ff1Sjsg 1301bb76ff1Sjsg #define BLIT_CCTL(base) _MMIO((base) + 0x204) 1311bb76ff1Sjsg #define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8) 1321bb76ff1Sjsg #define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0) 1331bb76ff1Sjsg #define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \ 1341bb76ff1Sjsg BLIT_CCTL_SRC_MOCS_MASK) 1351bb76ff1Sjsg #define BLIT_CCTL_MOCS(dst, src) \ 1361bb76ff1Sjsg (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \ 1371bb76ff1Sjsg REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1)) 1381bb76ff1Sjsg 1391bb76ff1Sjsg #define RING_CSCMDOP(base) _MMIO((base) + 0x20c) 1401bb76ff1Sjsg 1411bb76ff1Sjsg /* 1421bb76ff1Sjsg * CMD_CCTL read/write fields take a MOCS value and _not_ a table index. 1431bb76ff1Sjsg * The lsb of each can be considered a separate enabling bit for encryption. 1441bb76ff1Sjsg * 6:0 == default MOCS value for reads => 6:1 == table index for reads. 1451bb76ff1Sjsg * 13:7 == default MOCS value for writes => 13:8 == table index for writes. 1461bb76ff1Sjsg * 15:14 == Reserved => 31:30 are set to 0. 1471bb76ff1Sjsg */ 1481bb76ff1Sjsg #define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7) 1491bb76ff1Sjsg #define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0) 1501bb76ff1Sjsg #define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \ 1511bb76ff1Sjsg CMD_CCTL_READ_OVERRIDE_MASK) 1521bb76ff1Sjsg #define CMD_CCTL_MOCS_OVERRIDE(write, read) \ 1531bb76ff1Sjsg (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \ 1541bb76ff1Sjsg REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1)) 1551bb76ff1Sjsg 1561bb76ff1Sjsg #define RING_PREDICATE_RESULT(base) _MMIO((base) + 0x3b8) /* gen12+ */ 1571bb76ff1Sjsg 1581bb76ff1Sjsg #define MI_PREDICATE_RESULT_2(base) _MMIO((base) + 0x3bc) 1591bb76ff1Sjsg #define LOWER_SLICE_ENABLED (1 << 0) 1601bb76ff1Sjsg #define LOWER_SLICE_DISABLED (0 << 0) 1611bb76ff1Sjsg #define MI_PREDICATE_SRC0(base) _MMIO((base) + 0x400) 1621bb76ff1Sjsg #define MI_PREDICATE_SRC0_UDW(base) _MMIO((base) + 0x400 + 4) 1631bb76ff1Sjsg #define MI_PREDICATE_SRC1(base) _MMIO((base) + 0x408) 1641bb76ff1Sjsg #define MI_PREDICATE_SRC1_UDW(base) _MMIO((base) + 0x408 + 4) 1651bb76ff1Sjsg #define MI_PREDICATE_DATA(base) _MMIO((base) + 0x410) 1661bb76ff1Sjsg #define MI_PREDICATE_RESULT(base) _MMIO((base) + 0x418) 1671bb76ff1Sjsg #define MI_PREDICATE_RESULT_1(base) _MMIO((base) + 0x41c) 1681bb76ff1Sjsg 1691bb76ff1Sjsg #define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220) 1701bb76ff1Sjsg #define PP_DIR_DCLV_2G 0xffffffff 1711bb76ff1Sjsg #define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228) 1721bb76ff1Sjsg #define RING_ELSP(base) _MMIO((base) + 0x230) 1731bb76ff1Sjsg #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234) 1741bb76ff1Sjsg #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4) 1751bb76ff1Sjsg #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244) 1761bb76ff1Sjsg #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0) 1771bb76ff1Sjsg #define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1) 1781bb76ff1Sjsg #define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2) 1791bb76ff1Sjsg #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3) 1801bb76ff1Sjsg #define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8) 1811bb76ff1Sjsg #define RING_CTX_SR_CTL(base) _MMIO((base) + 0x244) 1821bb76ff1Sjsg #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) 1831bb76ff1Sjsg #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4) 1841bb76ff1Sjsg #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8) 1851bb76ff1Sjsg #define RING_MODE_GEN7(base) _MMIO((base) + 0x29c) 1861bb76ff1Sjsg #define GFX_RUN_LIST_ENABLE (1 << 15) 1871bb76ff1Sjsg #define GFX_INTERRUPT_STEERING (1 << 14) 1881bb76ff1Sjsg #define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13) 1891bb76ff1Sjsg #define GFX_SURFACE_FAULT_ENABLE (1 << 12) 1901bb76ff1Sjsg #define GFX_REPLAY_MODE (1 << 11) 1911bb76ff1Sjsg #define GFX_PSMI_GRANULARITY (1 << 10) 1921bb76ff1Sjsg #define GEN12_GFX_PREFETCH_DISABLE REG_BIT(10) 1931bb76ff1Sjsg #define GFX_PPGTT_ENABLE (1 << 9) 1941bb76ff1Sjsg #define GEN8_GFX_PPGTT_48B (1 << 7) 1951bb76ff1Sjsg #define GFX_FORWARD_VBLANK_MASK (3 << 5) 1961bb76ff1Sjsg #define GFX_FORWARD_VBLANK_NEVER (0 << 5) 1971bb76ff1Sjsg #define GFX_FORWARD_VBLANK_ALWAYS (1 << 5) 1981bb76ff1Sjsg #define GFX_FORWARD_VBLANK_COND (2 << 5) 1991bb76ff1Sjsg #define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3) 2001bb76ff1Sjsg #define RING_TIMESTAMP(base) _MMIO((base) + 0x358) 2011bb76ff1Sjsg #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4) 2021bb76ff1Sjsg #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0) 2031bb76ff1Sjsg #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ 2041bb76ff1Sjsg #define RING_PREDICATE_RESULT(base) _MMIO((base) + 0x3b8) 205*f005ef32Sjsg #define MI_PREDICATE_RESULT_2_ENGINE(base) _MMIO((base) + 0x3bc) 2061bb76ff1Sjsg #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4) 2071bb76ff1Sjsg #define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30) 2081bb76ff1Sjsg #define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2) 2091bb76ff1Sjsg #define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */ 2101bb76ff1Sjsg #define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28) 2111bb76ff1Sjsg #define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28) 2121bb76ff1Sjsg #define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28) 2131bb76ff1Sjsg #define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28) 2141bb76ff1Sjsg #define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */ 2151bb76ff1Sjsg #define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0) 2161bb76ff1Sjsg #define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0) 2171bb76ff1Sjsg #define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0) 2181bb76ff1Sjsg #define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0) 2191bb76ff1Sjsg #define RING_FORCE_TO_NONPRIV_MASK_VALID \ 2201bb76ff1Sjsg (RING_FORCE_TO_NONPRIV_RANGE_MASK | \ 2211bb76ff1Sjsg RING_FORCE_TO_NONPRIV_ACCESS_MASK | \ 2221bb76ff1Sjsg RING_FORCE_TO_NONPRIV_DENY) 2231bb76ff1Sjsg #define RING_MAX_NONPRIV_SLOTS 12 2241bb76ff1Sjsg 2251bb76ff1Sjsg #define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510) 2261bb76ff1Sjsg #define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518) 2271bb76ff1Sjsg #define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550) 2281bb76ff1Sjsg #define EL_CTRL_LOAD REG_BIT(0) 2291bb76ff1Sjsg 2301bb76ff1Sjsg /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */ 2311bb76ff1Sjsg #define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8) 2321bb76ff1Sjsg #define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4) 2331bb76ff1Sjsg 2341bb76ff1Sjsg #define GEN11_VCS_SFC_FORCED_LOCK(base) _MMIO((base) + 0x88c) 2351bb76ff1Sjsg #define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0) 2361bb76ff1Sjsg #define GEN11_VCS_SFC_LOCK_STATUS(base) _MMIO((base) + 0x890) 2371bb76ff1Sjsg #define GEN11_VCS_SFC_USAGE_BIT (1 << 0) 2381bb76ff1Sjsg #define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1) 2391bb76ff1Sjsg 2401bb76ff1Sjsg #define GEN11_VECS_SFC_FORCED_LOCK(base) _MMIO((base) + 0x201c) 2411bb76ff1Sjsg #define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0) 2421bb76ff1Sjsg #define GEN11_VECS_SFC_LOCK_ACK(base) _MMIO((base) + 0x2018) 2431bb76ff1Sjsg #define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0) 2441bb76ff1Sjsg #define GEN11_VECS_SFC_USAGE(base) _MMIO((base) + 0x2014) 2451bb76ff1Sjsg #define GEN11_VECS_SFC_USAGE_BIT (1 << 0) 2461bb76ff1Sjsg 2471bb76ff1Sjsg #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) 2481bb76ff1Sjsg 2491bb76ff1Sjsg #define GEN12_HCP_SFC_LOCK_STATUS(base) _MMIO((base) + 0x2914) 2501bb76ff1Sjsg #define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1) 2511bb76ff1Sjsg #define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0) 2521bb76ff1Sjsg 2531bb76ff1Sjsg #define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10) 2541bb76ff1Sjsg #define IECPUNIT_CLKGATE_DIS REG_BIT(22) 2551bb76ff1Sjsg 2561bb76ff1Sjsg #define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18) 2571bb76ff1Sjsg #define ALNUNIT_CLKGATE_DIS REG_BIT(13) 2581bb76ff1Sjsg 2591bb76ff1Sjsg 2601bb76ff1Sjsg #endif /* __INTEL_ENGINE_REGS__ */ 261