1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * Please try to maintain the following order within this file unless it makes 6 * sense to do otherwise. From top to bottom: 7 * 1. typedefs 8 * 2. #defines, and macros 9 * 3. structure definitions 10 * 4. function prototypes 11 * 12 * Within each section, please try to order by generation in ascending order, 13 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 14 */ 15 16 #ifndef __INTEL_GTT_H__ 17 #define __INTEL_GTT_H__ 18 19 #include <linux/io-mapping.h> 20 #include <linux/kref.h> 21 #include <linux/mm.h> 22 #include <linux/pagevec.h> 23 #include <linux/scatterlist.h> 24 #include <linux/workqueue.h> 25 26 #include <drm/drm_mm.h> 27 28 #include "gt/intel_reset.h" 29 #include "i915_gem_fence_reg.h" 30 #include "i915_selftest.h" 31 #include "i915_vma_types.h" 32 33 #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 34 35 #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT) 36 #define DBG(...) trace_printk(__VA_ARGS__) 37 #else 38 #define DBG(...) 39 #endif 40 41 #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */ 42 43 #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) 44 #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) 45 #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) 46 47 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 48 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 49 50 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE 51 52 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 53 54 #define I915_FENCE_REG_NONE -1 55 #define I915_MAX_NUM_FENCES 32 56 /* 32 fences + sign bit for FENCE_REG_NONE */ 57 #define I915_MAX_NUM_FENCE_BITS 6 58 59 typedef u32 gen6_pte_t; 60 typedef u64 gen8_pte_t; 61 62 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT) 63 64 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 65 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 66 #define I915_PDES 512 67 #define I915_PDE_MASK (I915_PDES - 1) 68 69 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 70 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 71 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 72 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 73 #define GEN6_PTE_CACHE_LLC (2 << 1) 74 #define GEN6_PTE_UNCACHED (1 << 1) 75 #define GEN6_PTE_VALID REG_BIT(0) 76 77 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 78 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 79 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 80 #define GEN6_PDE_SHIFT 22 81 #define GEN6_PDE_VALID REG_BIT(0) 82 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 83 84 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 85 86 #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2) 87 #define BYT_PTE_WRITEABLE REG_BIT(1) 88 89 /* 90 * Cacheability Control is a 4-bit value. The low three bits are stored in bits 91 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 92 */ 93 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 94 (((bits) & 0x8) << (11 - 3))) 95 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 96 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 97 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 98 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 99 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 100 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 101 #define HSW_PTE_UNCACHED (0) 102 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 103 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 104 105 /* 106 * GEN8 32b style address is defined as a 3 level page table: 107 * 31:30 | 29:21 | 20:12 | 11:0 108 * PDPE | PDE | PTE | offset 109 * The difference as compared to normal x86 3 level page table is the PDPEs are 110 * programmed via register. 111 * 112 * GEN8 48b style address is defined as a 4 level page table: 113 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 114 * PML4E | PDPE | PDE | PTE | offset 115 */ 116 #define GEN8_3LVL_PDPES 4 117 118 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 119 #define PPAT_CACHED_PDE 0 /* WB LLC */ 120 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 121 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 122 123 #define CHV_PPAT_SNOOP REG_BIT(6) 124 #define GEN8_PPAT_AGE(x) ((x)<<4) 125 #define GEN8_PPAT_LLCeLLC (3<<2) 126 #define GEN8_PPAT_LLCELLC (2<<2) 127 #define GEN8_PPAT_LLC (1<<2) 128 #define GEN8_PPAT_WB (3<<0) 129 #define GEN8_PPAT_WT (2<<0) 130 #define GEN8_PPAT_WC (1<<0) 131 #define GEN8_PPAT_UC (0<<0) 132 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 133 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 134 135 #define GEN8_PDE_IPS_64K BIT(11) 136 #define GEN8_PDE_PS_2M BIT(7) 137 138 #define for_each_sgt_daddr(__dp, __iter, __sgt) \ 139 __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE) 140 141 struct i915_page_dma { 142 struct vm_page *page; 143 union { 144 dma_addr_t daddr; 145 146 /* 147 * For gen6/gen7 only. This is the offset in the GGTT 148 * where the page directory entries for PPGTT begin 149 */ 150 u32 ggtt_offset; 151 }; 152 }; 153 154 struct i915_page_scratch { 155 struct i915_page_dma base; 156 u64 encode; 157 }; 158 159 struct i915_page_table { 160 struct i915_page_dma base; 161 atomic_t used; 162 }; 163 164 struct i915_page_directory { 165 struct i915_page_table pt; 166 spinlock_t lock; 167 void *entry[512]; 168 }; 169 170 #define __px_choose_expr(x, type, expr, other) \ 171 __builtin_choose_expr( \ 172 __builtin_types_compatible_p(typeof(x), type) || \ 173 __builtin_types_compatible_p(typeof(x), const type), \ 174 ({ type __x = (type)(x); expr; }), \ 175 other) 176 177 #define px_base(px) \ 178 __px_choose_expr(px, struct i915_page_dma *, __x, \ 179 __px_choose_expr(px, struct i915_page_scratch *, &__x->base, \ 180 __px_choose_expr(px, struct i915_page_table *, &__x->base, \ 181 __px_choose_expr(px, struct i915_page_directory *, &__x->pt.base, \ 182 (void)0)))) 183 #define px_dma(px) (px_base(px)->daddr) 184 185 #define px_pt(px) \ 186 __px_choose_expr(px, struct i915_page_table *, __x, \ 187 __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \ 188 (void)0)) 189 #define px_used(px) (&px_pt(px)->used) 190 191 enum i915_cache_level; 192 193 struct drm_i915_file_private; 194 struct drm_i915_gem_object; 195 struct i915_vma; 196 struct intel_gt; 197 198 struct i915_vma_ops { 199 /* Map an object into an address space with the given cache flags. */ 200 int (*bind_vma)(struct i915_vma *vma, 201 enum i915_cache_level cache_level, 202 u32 flags); 203 /* 204 * Unmap an object from an address space. This usually consists of 205 * setting the valid PTE entries to a reserved scratch page. 206 */ 207 void (*unbind_vma)(struct i915_vma *vma); 208 209 int (*set_pages)(struct i915_vma *vma); 210 void (*clear_pages)(struct i915_vma *vma); 211 }; 212 213 struct pagestash { 214 spinlock_t lock; 215 struct pagevec pvec; 216 }; 217 218 void stash_init(struct pagestash *stash); 219 220 struct i915_address_space { 221 struct kref ref; 222 struct rcu_work rcu; 223 224 struct drm_mm mm; 225 struct intel_gt *gt; 226 struct drm_i915_private *i915; 227 struct device *dma; 228 /* 229 * Every address space belongs to a struct file - except for the global 230 * GTT that is owned by the driver (and so @file is set to NULL). In 231 * principle, no information should leak from one context to another 232 * (or between files/processes etc) unless explicitly shared by the 233 * owner. Tracking the owner is important in order to free up per-file 234 * objects along with the file, to aide resource tracking, and to 235 * assign blame. 236 */ 237 struct drm_i915_file_private *file; 238 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 239 u64 reserved; /* size addr space reserved */ 240 241 unsigned int bind_async_flags; 242 243 /* 244 * Each active user context has its own address space (in full-ppgtt). 245 * Since the vm may be shared between multiple contexts, we count how 246 * many contexts keep us "open". Once open hits zero, we are closed 247 * and do not allow any new attachments, and proceed to shutdown our 248 * vma and page directories. 249 */ 250 atomic_t open; 251 252 struct rwlock mutex; /* protects vma and our lists */ 253 #define VM_CLASS_GGTT 0 254 #define VM_CLASS_PPGTT 1 255 256 struct i915_page_scratch scratch[4]; 257 unsigned int scratch_order; 258 unsigned int top; 259 260 /** 261 * List of vma currently bound. 262 */ 263 struct list_head bound_list; 264 265 struct pagestash free_pages; 266 267 /* Global GTT */ 268 bool is_ggtt:1; 269 270 /* Some systems require uncached updates of the page directories */ 271 bool pt_kmap_wc:1; 272 273 /* Some systems support read-only mappings for GGTT and/or PPGTT */ 274 bool has_read_only:1; 275 276 u64 (*pte_encode)(dma_addr_t addr, 277 enum i915_cache_level level, 278 u32 flags); /* Create a valid PTE */ 279 #define PTE_READ_ONLY BIT(0) 280 281 int (*allocate_va_range)(struct i915_address_space *vm, 282 u64 start, u64 length); 283 void (*clear_range)(struct i915_address_space *vm, 284 u64 start, u64 length); 285 void (*insert_page)(struct i915_address_space *vm, 286 dma_addr_t addr, 287 u64 offset, 288 enum i915_cache_level cache_level, 289 u32 flags); 290 void (*insert_entries)(struct i915_address_space *vm, 291 struct i915_vma *vma, 292 enum i915_cache_level cache_level, 293 u32 flags); 294 void (*cleanup)(struct i915_address_space *vm); 295 296 struct i915_vma_ops vma_ops; 297 298 I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 299 I915_SELFTEST_DECLARE(bool scrub_64K); 300 }; 301 302 /* 303 * The Graphics Translation Table is the way in which GEN hardware translates a 304 * Graphics Virtual Address into a Physical Address. In addition to the normal 305 * collateral associated with any va->pa translations GEN hardware also has a 306 * portion of the GTT which can be mapped by the CPU and remain both coherent 307 * and correct (in cases like swizzling). That region is referred to as GMADR in 308 * the spec. 309 */ 310 struct i915_ggtt { 311 struct i915_address_space vm; 312 313 #ifdef notyet 314 struct io_mapping iomap; /* Mapping to our CPU mappable region */ 315 #endif 316 struct resource gmadr; /* GMADR resource */ 317 resource_size_t mappable_end; /* End offset that we can CPU map */ 318 319 /** "Graphics Stolen Memory" holds the global PTEs */ 320 void __iomem *gsm; 321 bus_space_handle_t gsm_bsh; 322 bus_size_t gsm_size; 323 void (*invalidate)(struct i915_ggtt *ggtt); 324 325 /** PPGTT used for aliasing the PPGTT with the GTT */ 326 struct i915_ppgtt *alias; 327 328 bool do_idle_maps; 329 330 int mtrr; 331 332 /** Bit 6 swizzling required for X tiling */ 333 u32 bit_6_swizzle_x; 334 /** Bit 6 swizzling required for Y tiling */ 335 u32 bit_6_swizzle_y; 336 337 u32 pin_bias; 338 339 unsigned int num_fences; 340 struct i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; 341 struct list_head fence_list; 342 343 /** 344 * List of all objects in gtt_space, currently mmaped by userspace. 345 * All objects within this list must also be on bound_list. 346 */ 347 struct list_head userfault_list; 348 349 /* Manual runtime pm autosuspend delay for user GGTT mmaps */ 350 struct intel_wakeref_auto userfault_wakeref; 351 352 struct rwlock error_mutex; 353 struct drm_mm_node error_capture; 354 struct drm_mm_node uc_fw; 355 }; 356 357 struct i915_ppgtt { 358 struct i915_address_space vm; 359 360 struct i915_page_directory *pd; 361 }; 362 363 #define i915_is_ggtt(vm) ((vm)->is_ggtt) 364 365 static inline bool 366 i915_vm_is_4lvl(const struct i915_address_space *vm) 367 { 368 return (vm->total - 1) >> 32; 369 } 370 371 static inline bool 372 i915_vm_has_scratch_64K(struct i915_address_space *vm) 373 { 374 return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K); 375 } 376 377 static inline bool 378 i915_vm_has_cache_coloring(struct i915_address_space *vm) 379 { 380 return i915_is_ggtt(vm) && vm->mm.color_adjust; 381 } 382 383 static inline struct i915_ggtt * 384 i915_vm_to_ggtt(struct i915_address_space *vm) 385 { 386 BUILD_BUG_ON(offsetof(struct i915_ggtt, vm)); 387 GEM_BUG_ON(!i915_is_ggtt(vm)); 388 return container_of(vm, struct i915_ggtt, vm); 389 } 390 391 static inline struct i915_ppgtt * 392 i915_vm_to_ppgtt(struct i915_address_space *vm) 393 { 394 BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm)); 395 GEM_BUG_ON(i915_is_ggtt(vm)); 396 return container_of(vm, struct i915_ppgtt, vm); 397 } 398 399 static inline struct i915_address_space * 400 i915_vm_get(struct i915_address_space *vm) 401 { 402 kref_get(&vm->ref); 403 return vm; 404 } 405 406 void i915_vm_release(struct kref *kref); 407 408 static inline void i915_vm_put(struct i915_address_space *vm) 409 { 410 kref_put(&vm->ref, i915_vm_release); 411 } 412 413 static inline struct i915_address_space * 414 i915_vm_open(struct i915_address_space *vm) 415 { 416 GEM_BUG_ON(!atomic_read(&vm->open)); 417 atomic_inc(&vm->open); 418 return i915_vm_get(vm); 419 } 420 421 static inline bool 422 i915_vm_tryopen(struct i915_address_space *vm) 423 { 424 if (atomic_add_unless(&vm->open, 1, 0)) 425 return i915_vm_get(vm); 426 427 return false; 428 } 429 430 void __i915_vm_close(struct i915_address_space *vm); 431 432 static inline void 433 i915_vm_close(struct i915_address_space *vm) 434 { 435 GEM_BUG_ON(!atomic_read(&vm->open)); 436 __i915_vm_close(vm); 437 438 i915_vm_put(vm); 439 } 440 441 void i915_address_space_init(struct i915_address_space *vm, int subclass); 442 void i915_address_space_fini(struct i915_address_space *vm); 443 444 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 445 { 446 const u32 mask = NUM_PTE(pde_shift) - 1; 447 448 return (address >> PAGE_SHIFT) & mask; 449 } 450 451 /* 452 * Helper to counts the number of PTEs within the given length. This count 453 * does not cross a page table boundary, so the max value would be 454 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 455 */ 456 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 457 { 458 const u64 mask = ~((1ULL << pde_shift) - 1); 459 u64 end; 460 461 GEM_BUG_ON(length == 0); 462 GEM_BUG_ON(offset_in_page(addr | length)); 463 464 end = addr + length; 465 466 if ((addr & mask) != (end & mask)) 467 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 468 469 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 470 } 471 472 static inline u32 i915_pde_index(u64 addr, u32 shift) 473 { 474 return (addr >> shift) & I915_PDE_MASK; 475 } 476 477 static inline struct i915_page_table * 478 i915_pt_entry(const struct i915_page_directory * const pd, 479 const unsigned short n) 480 { 481 return pd->entry[n]; 482 } 483 484 static inline struct i915_page_directory * 485 i915_pd_entry(const struct i915_page_directory * const pdp, 486 const unsigned short n) 487 { 488 return pdp->entry[n]; 489 } 490 491 static inline dma_addr_t 492 i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n) 493 { 494 struct i915_page_dma *pt = ppgtt->pd->entry[n]; 495 496 return px_dma(pt ?: px_base(&ppgtt->vm.scratch[ppgtt->vm.top])); 497 } 498 499 void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt); 500 501 int i915_ggtt_probe_hw(struct drm_i915_private *i915); 502 int i915_ggtt_init_hw(struct drm_i915_private *i915); 503 int i915_ggtt_enable_hw(struct drm_i915_private *i915); 504 void i915_ggtt_enable_guc(struct i915_ggtt *ggtt); 505 void i915_ggtt_disable_guc(struct i915_ggtt *ggtt); 506 int i915_init_ggtt(struct drm_i915_private *i915); 507 void i915_ggtt_driver_release(struct drm_i915_private *i915); 508 509 static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt) 510 { 511 return ggtt->mappable_end > 0; 512 } 513 514 int i915_ppgtt_init_hw(struct intel_gt *gt); 515 516 struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt); 517 518 void i915_ggtt_suspend(struct i915_ggtt *gtt); 519 void i915_ggtt_resume(struct i915_ggtt *ggtt); 520 521 int setup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p); 522 void cleanup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p); 523 524 #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page) 525 526 void 527 fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count); 528 529 #define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64)) 530 #define fill32_px(px, v) do { \ 531 u64 v__ = lower_32_bits(v); \ 532 fill_px((px), v__ << 32 | v__); \ 533 } while (0) 534 535 int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp); 536 void cleanup_scratch_page(struct i915_address_space *vm); 537 void free_scratch(struct i915_address_space *vm); 538 539 struct i915_page_table *alloc_pt(struct i915_address_space *vm); 540 struct i915_page_directory *alloc_pd(struct i915_address_space *vm); 541 struct i915_page_directory *__alloc_pd(size_t sz); 542 543 void free_pd(struct i915_address_space *vm, struct i915_page_dma *pd); 544 545 #define free_px(vm, px) free_pd(vm, px_base(px)) 546 547 void 548 __set_pd_entry(struct i915_page_directory * const pd, 549 const unsigned short idx, 550 struct i915_page_dma * const to, 551 u64 (*encode)(const dma_addr_t, const enum i915_cache_level)); 552 553 #define set_pd_entry(pd, idx, to) \ 554 __set_pd_entry((pd), (idx), px_base(to), gen8_pde_encode) 555 556 void 557 clear_pd_entry(struct i915_page_directory * const pd, 558 const unsigned short idx, 559 const struct i915_page_scratch * const scratch); 560 561 bool 562 release_pd_entry(struct i915_page_directory * const pd, 563 const unsigned short idx, 564 struct i915_page_table * const pt, 565 const struct i915_page_scratch * const scratch); 566 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt); 567 568 int ggtt_set_pages(struct i915_vma *vma); 569 int ppgtt_set_pages(struct i915_vma *vma); 570 void clear_pages(struct i915_vma *vma); 571 572 void gtt_write_workarounds(struct intel_gt *gt); 573 574 void setup_private_pat(struct intel_uncore *uncore); 575 576 static inline struct sgt_dma { 577 struct scatterlist *sg; 578 dma_addr_t dma, max; 579 } sgt_dma(struct i915_vma *vma) { 580 struct scatterlist *sg = vma->pages->sgl; 581 dma_addr_t addr = sg_dma_address(sg); 582 583 return (struct sgt_dma){ sg, addr, addr + sg->length }; 584 } 585 586 #endif 587