1c349dbc7Sjsg /*
2c349dbc7Sjsg * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3c349dbc7Sjsg *
4c349dbc7Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
5c349dbc7Sjsg * copy of this software and associated documentation files (the "Software"),
6c349dbc7Sjsg * to deal in the Software without restriction, including without limitation
7c349dbc7Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8c349dbc7Sjsg * and/or sell copies of the Software, and to permit persons to whom the
9c349dbc7Sjsg * Software is furnished to do so, subject to the following conditions:
10c349dbc7Sjsg *
11c349dbc7Sjsg * The above copyright notice and this permission notice (including the next
12c349dbc7Sjsg * paragraph) shall be included in all copies or substantial portions of the
13c349dbc7Sjsg * Software.
14c349dbc7Sjsg *
15c349dbc7Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16c349dbc7Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17c349dbc7Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18c349dbc7Sjsg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19c349dbc7Sjsg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20c349dbc7Sjsg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21c349dbc7Sjsg * SOFTWARE.
22c349dbc7Sjsg *
23c349dbc7Sjsg * Authors:
24c349dbc7Sjsg * Ke Yu
25c349dbc7Sjsg * Zhiyuan Lv <zhiyuan.lv@intel.com>
26c349dbc7Sjsg *
27c349dbc7Sjsg * Contributors:
28c349dbc7Sjsg * Terrence Xu <terrence.xu@intel.com>
29c349dbc7Sjsg * Changbin Du <changbin.du@intel.com>
30c349dbc7Sjsg * Bing Niu <bing.niu@intel.com>
31c349dbc7Sjsg * Zhi Wang <zhi.a.wang@intel.com>
32c349dbc7Sjsg *
33c349dbc7Sjsg */
34c349dbc7Sjsg
35*f005ef32Sjsg #include "display/intel_dp_aux_regs.h"
361bb76ff1Sjsg #include "display/intel_gmbus_regs.h"
37c349dbc7Sjsg #include "gvt.h"
381bb76ff1Sjsg #include "i915_drv.h"
391bb76ff1Sjsg #include "i915_reg.h"
40c349dbc7Sjsg
41c349dbc7Sjsg #define GMBUS1_TOTAL_BYTES_SHIFT 16
42c349dbc7Sjsg #define GMBUS1_TOTAL_BYTES_MASK 0x1ff
43c349dbc7Sjsg #define gmbus1_total_byte_count(v) (((v) >> \
44c349dbc7Sjsg GMBUS1_TOTAL_BYTES_SHIFT) & GMBUS1_TOTAL_BYTES_MASK)
45c349dbc7Sjsg #define gmbus1_slave_addr(v) (((v) & 0xff) >> 1)
46c349dbc7Sjsg #define gmbus1_slave_index(v) (((v) >> 8) & 0xff)
47c349dbc7Sjsg #define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7)
48c349dbc7Sjsg
49c349dbc7Sjsg /* GMBUS0 bits definitions */
50c349dbc7Sjsg #define _GMBUS_PIN_SEL_MASK (0x7)
51c349dbc7Sjsg
edid_get_byte(struct intel_vgpu * vgpu)52c349dbc7Sjsg static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
53c349dbc7Sjsg {
54c349dbc7Sjsg struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
55c349dbc7Sjsg unsigned char chr = 0;
56c349dbc7Sjsg
57c349dbc7Sjsg if (edid->state == I2C_NOT_SPECIFIED || !edid->slave_selected) {
58c349dbc7Sjsg gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n");
59c349dbc7Sjsg return 0;
60c349dbc7Sjsg }
61c349dbc7Sjsg if (edid->current_edid_read >= EDID_SIZE) {
62c349dbc7Sjsg gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n");
63c349dbc7Sjsg return 0;
64c349dbc7Sjsg }
65c349dbc7Sjsg
66c349dbc7Sjsg if (!edid->edid_available) {
67c349dbc7Sjsg gvt_vgpu_err("Reading EDID but EDID is not available!\n");
68c349dbc7Sjsg return 0;
69c349dbc7Sjsg }
70c349dbc7Sjsg
71c349dbc7Sjsg if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {
72c349dbc7Sjsg struct intel_vgpu_edid_data *edid_data =
73c349dbc7Sjsg intel_vgpu_port(vgpu, edid->port)->edid;
74c349dbc7Sjsg
75c349dbc7Sjsg chr = edid_data->edid_block[edid->current_edid_read];
76c349dbc7Sjsg edid->current_edid_read++;
77c349dbc7Sjsg } else {
78c349dbc7Sjsg gvt_vgpu_err("No EDID available during the reading?\n");
79c349dbc7Sjsg }
80c349dbc7Sjsg return chr;
81c349dbc7Sjsg }
82c349dbc7Sjsg
cnp_get_port_from_gmbus0(u32 gmbus0)83c349dbc7Sjsg static inline int cnp_get_port_from_gmbus0(u32 gmbus0)
84c349dbc7Sjsg {
85c349dbc7Sjsg int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
86c349dbc7Sjsg int port = -EINVAL;
87c349dbc7Sjsg
88c349dbc7Sjsg if (port_select == GMBUS_PIN_1_BXT)
89c349dbc7Sjsg port = PORT_B;
90c349dbc7Sjsg else if (port_select == GMBUS_PIN_2_BXT)
91c349dbc7Sjsg port = PORT_C;
92c349dbc7Sjsg else if (port_select == GMBUS_PIN_3_BXT)
93c349dbc7Sjsg port = PORT_D;
94c349dbc7Sjsg else if (port_select == GMBUS_PIN_4_CNP)
95c349dbc7Sjsg port = PORT_E;
96c349dbc7Sjsg return port;
97c349dbc7Sjsg }
98c349dbc7Sjsg
bxt_get_port_from_gmbus0(u32 gmbus0)99c349dbc7Sjsg static inline int bxt_get_port_from_gmbus0(u32 gmbus0)
100c349dbc7Sjsg {
101c349dbc7Sjsg int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
102c349dbc7Sjsg int port = -EINVAL;
103c349dbc7Sjsg
104c349dbc7Sjsg if (port_select == GMBUS_PIN_1_BXT)
105c349dbc7Sjsg port = PORT_B;
106c349dbc7Sjsg else if (port_select == GMBUS_PIN_2_BXT)
107c349dbc7Sjsg port = PORT_C;
108c349dbc7Sjsg else if (port_select == GMBUS_PIN_3_BXT)
109c349dbc7Sjsg port = PORT_D;
110c349dbc7Sjsg return port;
111c349dbc7Sjsg }
112c349dbc7Sjsg
get_port_from_gmbus0(u32 gmbus0)113c349dbc7Sjsg static inline int get_port_from_gmbus0(u32 gmbus0)
114c349dbc7Sjsg {
115c349dbc7Sjsg int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
116c349dbc7Sjsg int port = -EINVAL;
117c349dbc7Sjsg
118c349dbc7Sjsg if (port_select == GMBUS_PIN_VGADDC)
119c349dbc7Sjsg port = PORT_E;
120c349dbc7Sjsg else if (port_select == GMBUS_PIN_DPC)
121c349dbc7Sjsg port = PORT_C;
122c349dbc7Sjsg else if (port_select == GMBUS_PIN_DPB)
123c349dbc7Sjsg port = PORT_B;
124c349dbc7Sjsg else if (port_select == GMBUS_PIN_DPD)
125c349dbc7Sjsg port = PORT_D;
126c349dbc7Sjsg return port;
127c349dbc7Sjsg }
128c349dbc7Sjsg
reset_gmbus_controller(struct intel_vgpu * vgpu)129c349dbc7Sjsg static void reset_gmbus_controller(struct intel_vgpu *vgpu)
130c349dbc7Sjsg {
131c349dbc7Sjsg vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
132c349dbc7Sjsg if (!vgpu->display.i2c_edid.edid_available)
133c349dbc7Sjsg vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
134c349dbc7Sjsg vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
135c349dbc7Sjsg }
136c349dbc7Sjsg
137c349dbc7Sjsg /* GMBUS0 */
gmbus0_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)138c349dbc7Sjsg static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
139c349dbc7Sjsg unsigned int offset, void *p_data, unsigned int bytes)
140c349dbc7Sjsg {
141c349dbc7Sjsg struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
142c349dbc7Sjsg int port, pin_select;
143c349dbc7Sjsg
144c349dbc7Sjsg memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
145c349dbc7Sjsg
146c349dbc7Sjsg pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
147c349dbc7Sjsg
148c349dbc7Sjsg intel_vgpu_init_i2c_edid(vgpu);
149c349dbc7Sjsg
150c349dbc7Sjsg if (pin_select == 0)
151c349dbc7Sjsg return 0;
152c349dbc7Sjsg
153c349dbc7Sjsg if (IS_BROXTON(i915))
154c349dbc7Sjsg port = bxt_get_port_from_gmbus0(pin_select);
155ad8b1aafSjsg else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
156c349dbc7Sjsg port = cnp_get_port_from_gmbus0(pin_select);
157c349dbc7Sjsg else
158c349dbc7Sjsg port = get_port_from_gmbus0(pin_select);
159c349dbc7Sjsg if (drm_WARN_ON(&i915->drm, port < 0))
160c349dbc7Sjsg return 0;
161c349dbc7Sjsg
162c349dbc7Sjsg vgpu->display.i2c_edid.state = I2C_GMBUS;
163c349dbc7Sjsg vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
164c349dbc7Sjsg
165c349dbc7Sjsg vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
166c349dbc7Sjsg vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
167c349dbc7Sjsg
168c349dbc7Sjsg if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
169c349dbc7Sjsg !intel_vgpu_port_is_dp(vgpu, port)) {
170c349dbc7Sjsg vgpu->display.i2c_edid.port = port;
171c349dbc7Sjsg vgpu->display.i2c_edid.edid_available = true;
172c349dbc7Sjsg vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
173c349dbc7Sjsg } else
174c349dbc7Sjsg vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
175c349dbc7Sjsg return 0;
176c349dbc7Sjsg }
177c349dbc7Sjsg
gmbus1_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)178c349dbc7Sjsg static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
179c349dbc7Sjsg void *p_data, unsigned int bytes)
180c349dbc7Sjsg {
181c349dbc7Sjsg struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
182c349dbc7Sjsg u32 slave_addr;
183c349dbc7Sjsg u32 wvalue = *(u32 *)p_data;
184c349dbc7Sjsg
185c349dbc7Sjsg if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
186c349dbc7Sjsg if (!(wvalue & GMBUS_SW_CLR_INT)) {
187c349dbc7Sjsg vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
188c349dbc7Sjsg reset_gmbus_controller(vgpu);
189c349dbc7Sjsg }
190c349dbc7Sjsg /*
191c349dbc7Sjsg * TODO: "This bit is cleared to zero when an event
192c349dbc7Sjsg * causes the HW_RDY bit transition to occur "
193c349dbc7Sjsg */
194c349dbc7Sjsg } else {
195c349dbc7Sjsg /*
196c349dbc7Sjsg * per bspec setting this bit can cause:
197c349dbc7Sjsg * 1) INT status bit cleared
198c349dbc7Sjsg * 2) HW_RDY bit asserted
199c349dbc7Sjsg */
200c349dbc7Sjsg if (wvalue & GMBUS_SW_CLR_INT) {
201c349dbc7Sjsg vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
202c349dbc7Sjsg vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
203c349dbc7Sjsg }
204c349dbc7Sjsg
205c349dbc7Sjsg /* For virtualization, we suppose that HW is always ready,
206c349dbc7Sjsg * so GMBUS_SW_RDY should always be cleared
207c349dbc7Sjsg */
208c349dbc7Sjsg if (wvalue & GMBUS_SW_RDY)
209c349dbc7Sjsg wvalue &= ~GMBUS_SW_RDY;
210c349dbc7Sjsg
211c349dbc7Sjsg i2c_edid->gmbus.total_byte_count =
212c349dbc7Sjsg gmbus1_total_byte_count(wvalue);
213c349dbc7Sjsg slave_addr = gmbus1_slave_addr(wvalue);
214c349dbc7Sjsg
215c349dbc7Sjsg /* vgpu gmbus only support EDID */
216c349dbc7Sjsg if (slave_addr == EDID_ADDR) {
217c349dbc7Sjsg i2c_edid->slave_selected = true;
218c349dbc7Sjsg } else if (slave_addr != 0) {
219c349dbc7Sjsg gvt_dbg_dpy(
220c349dbc7Sjsg "vgpu%d: unsupported gmbus slave addr(0x%x)\n"
221c349dbc7Sjsg " gmbus operations will be ignored.\n",
222c349dbc7Sjsg vgpu->id, slave_addr);
223c349dbc7Sjsg }
224c349dbc7Sjsg
225c349dbc7Sjsg if (wvalue & GMBUS_CYCLE_INDEX)
226c349dbc7Sjsg i2c_edid->current_edid_read =
227c349dbc7Sjsg gmbus1_slave_index(wvalue);
228c349dbc7Sjsg
229c349dbc7Sjsg i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);
230c349dbc7Sjsg switch (gmbus1_bus_cycle(wvalue)) {
231c349dbc7Sjsg case GMBUS_NOCYCLE:
232c349dbc7Sjsg break;
233c349dbc7Sjsg case GMBUS_STOP:
234c349dbc7Sjsg /* From spec:
235c349dbc7Sjsg * This can only cause a STOP to be generated
236c349dbc7Sjsg * if a GMBUS cycle is generated, the GMBUS is
237c349dbc7Sjsg * currently in a data/wait/idle phase, or it is in a
238c349dbc7Sjsg * WAIT phase
239c349dbc7Sjsg */
240c349dbc7Sjsg if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
241c349dbc7Sjsg != GMBUS_NOCYCLE) {
242c349dbc7Sjsg intel_vgpu_init_i2c_edid(vgpu);
243c349dbc7Sjsg /* After the 'stop' cycle, hw state would become
244c349dbc7Sjsg * 'stop phase' and then 'idle phase' after a
245c349dbc7Sjsg * few milliseconds. In emulation, we just set
246c349dbc7Sjsg * it as 'idle phase' ('stop phase' is not
247c349dbc7Sjsg * visible in gmbus interface)
248c349dbc7Sjsg */
249c349dbc7Sjsg i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
250c349dbc7Sjsg vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
251c349dbc7Sjsg }
252c349dbc7Sjsg break;
253c349dbc7Sjsg case NIDX_NS_W:
254c349dbc7Sjsg case IDX_NS_W:
255c349dbc7Sjsg case NIDX_STOP:
256c349dbc7Sjsg case IDX_STOP:
257c349dbc7Sjsg /* From hw spec the GMBUS phase
258c349dbc7Sjsg * transition like this:
259c349dbc7Sjsg * START (-->INDEX) -->DATA
260c349dbc7Sjsg */
261c349dbc7Sjsg i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;
262c349dbc7Sjsg vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
263c349dbc7Sjsg break;
264c349dbc7Sjsg default:
265c349dbc7Sjsg gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
266c349dbc7Sjsg break;
267c349dbc7Sjsg }
268c349dbc7Sjsg /*
269c349dbc7Sjsg * From hw spec the WAIT state will be
270c349dbc7Sjsg * cleared:
271c349dbc7Sjsg * (1) in a new GMBUS cycle
272c349dbc7Sjsg * (2) by generating a stop
273c349dbc7Sjsg */
274c349dbc7Sjsg vgpu_vreg(vgpu, offset) = wvalue;
275c349dbc7Sjsg }
276c349dbc7Sjsg return 0;
277c349dbc7Sjsg }
278c349dbc7Sjsg
gmbus3_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)279c349dbc7Sjsg static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
280c349dbc7Sjsg void *p_data, unsigned int bytes)
281c349dbc7Sjsg {
282c349dbc7Sjsg struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
283c349dbc7Sjsg
284c349dbc7Sjsg drm_WARN_ON(&i915->drm, 1);
285c349dbc7Sjsg return 0;
286c349dbc7Sjsg }
287c349dbc7Sjsg
gmbus3_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)288c349dbc7Sjsg static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
289c349dbc7Sjsg void *p_data, unsigned int bytes)
290c349dbc7Sjsg {
291c349dbc7Sjsg int i;
292c349dbc7Sjsg unsigned char byte_data;
293c349dbc7Sjsg struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
294c349dbc7Sjsg int byte_left = i2c_edid->gmbus.total_byte_count -
295c349dbc7Sjsg i2c_edid->current_edid_read;
296c349dbc7Sjsg int byte_count = byte_left;
297c349dbc7Sjsg u32 reg_data = 0;
298c349dbc7Sjsg
299c349dbc7Sjsg /* Data can only be recevied if previous settings correct */
300c349dbc7Sjsg if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
301c349dbc7Sjsg if (byte_left <= 0) {
302c349dbc7Sjsg memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
303c349dbc7Sjsg return 0;
304c349dbc7Sjsg }
305c349dbc7Sjsg
306c349dbc7Sjsg if (byte_count > 4)
307c349dbc7Sjsg byte_count = 4;
308c349dbc7Sjsg for (i = 0; i < byte_count; i++) {
309c349dbc7Sjsg byte_data = edid_get_byte(vgpu);
310c349dbc7Sjsg reg_data |= (byte_data << (i << 3));
311c349dbc7Sjsg }
312c349dbc7Sjsg
313c349dbc7Sjsg memcpy(&vgpu_vreg(vgpu, offset), ®_data, byte_count);
314c349dbc7Sjsg memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
315c349dbc7Sjsg
316c349dbc7Sjsg if (byte_left <= 4) {
317c349dbc7Sjsg switch (i2c_edid->gmbus.cycle_type) {
318c349dbc7Sjsg case NIDX_STOP:
319c349dbc7Sjsg case IDX_STOP:
320c349dbc7Sjsg i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
321c349dbc7Sjsg break;
322c349dbc7Sjsg case NIDX_NS_W:
323c349dbc7Sjsg case IDX_NS_W:
324c349dbc7Sjsg default:
325c349dbc7Sjsg i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE;
326c349dbc7Sjsg break;
327c349dbc7Sjsg }
328c349dbc7Sjsg intel_vgpu_init_i2c_edid(vgpu);
329c349dbc7Sjsg }
330c349dbc7Sjsg /*
331c349dbc7Sjsg * Read GMBUS3 during send operation,
332c349dbc7Sjsg * return the latest written value
333c349dbc7Sjsg */
334c349dbc7Sjsg } else {
335c349dbc7Sjsg memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
336c349dbc7Sjsg gvt_vgpu_err("warning: gmbus3 read with nothing returned\n");
337c349dbc7Sjsg }
338c349dbc7Sjsg return 0;
339c349dbc7Sjsg }
340c349dbc7Sjsg
gmbus2_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)341c349dbc7Sjsg static int gmbus2_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
342c349dbc7Sjsg void *p_data, unsigned int bytes)
343c349dbc7Sjsg {
344c349dbc7Sjsg u32 value = vgpu_vreg(vgpu, offset);
345c349dbc7Sjsg
346c349dbc7Sjsg if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))
347c349dbc7Sjsg vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;
348c349dbc7Sjsg memcpy(p_data, (void *)&value, bytes);
349c349dbc7Sjsg return 0;
350c349dbc7Sjsg }
351c349dbc7Sjsg
gmbus2_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)352c349dbc7Sjsg static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
353c349dbc7Sjsg void *p_data, unsigned int bytes)
354c349dbc7Sjsg {
355c349dbc7Sjsg u32 wvalue = *(u32 *)p_data;
356c349dbc7Sjsg
357c349dbc7Sjsg if (wvalue & GMBUS_INUSE)
358c349dbc7Sjsg vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;
359c349dbc7Sjsg /* All other bits are read-only */
360c349dbc7Sjsg return 0;
361c349dbc7Sjsg }
362c349dbc7Sjsg
363c349dbc7Sjsg /**
364c349dbc7Sjsg * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
365c349dbc7Sjsg * @vgpu: a vGPU
366c349dbc7Sjsg * @offset: reg offset
367c349dbc7Sjsg * @p_data: data return buffer
368c349dbc7Sjsg * @bytes: access data length
369c349dbc7Sjsg *
370c349dbc7Sjsg * This function is used to emulate gmbus register mmio read
371c349dbc7Sjsg *
372c349dbc7Sjsg * Returns:
373c349dbc7Sjsg * Zero on success, negative error code if failed.
374c349dbc7Sjsg *
375c349dbc7Sjsg */
intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)376c349dbc7Sjsg int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
377c349dbc7Sjsg unsigned int offset, void *p_data, unsigned int bytes)
378c349dbc7Sjsg {
379c349dbc7Sjsg struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
380c349dbc7Sjsg
381c349dbc7Sjsg if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
382c349dbc7Sjsg return -EINVAL;
383c349dbc7Sjsg
384c349dbc7Sjsg if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
385c349dbc7Sjsg return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
386c349dbc7Sjsg else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
387c349dbc7Sjsg return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
388c349dbc7Sjsg
389c349dbc7Sjsg memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
390c349dbc7Sjsg return 0;
391c349dbc7Sjsg }
392c349dbc7Sjsg
393c349dbc7Sjsg /**
394c349dbc7Sjsg * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
395c349dbc7Sjsg * @vgpu: a vGPU
396c349dbc7Sjsg * @offset: reg offset
397c349dbc7Sjsg * @p_data: data return buffer
398c349dbc7Sjsg * @bytes: access data length
399c349dbc7Sjsg *
400c349dbc7Sjsg * This function is used to emulate gmbus register mmio write
401c349dbc7Sjsg *
402c349dbc7Sjsg * Returns:
403c349dbc7Sjsg * Zero on success, negative error code if failed.
404c349dbc7Sjsg *
405c349dbc7Sjsg */
intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)406c349dbc7Sjsg int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
407c349dbc7Sjsg unsigned int offset, void *p_data, unsigned int bytes)
408c349dbc7Sjsg {
409c349dbc7Sjsg struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
410c349dbc7Sjsg
411c349dbc7Sjsg if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
412c349dbc7Sjsg return -EINVAL;
413c349dbc7Sjsg
414c349dbc7Sjsg if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
415c349dbc7Sjsg return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
416c349dbc7Sjsg else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))
417c349dbc7Sjsg return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
418c349dbc7Sjsg else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
419c349dbc7Sjsg return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
420c349dbc7Sjsg else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
421c349dbc7Sjsg return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
422c349dbc7Sjsg
423c349dbc7Sjsg memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
424c349dbc7Sjsg return 0;
425c349dbc7Sjsg }
426c349dbc7Sjsg
427c349dbc7Sjsg enum {
428c349dbc7Sjsg AUX_CH_CTL = 0,
429c349dbc7Sjsg AUX_CH_DATA1,
430c349dbc7Sjsg AUX_CH_DATA2,
431c349dbc7Sjsg AUX_CH_DATA3,
432c349dbc7Sjsg AUX_CH_DATA4,
433c349dbc7Sjsg AUX_CH_DATA5
434c349dbc7Sjsg };
435c349dbc7Sjsg
get_aux_ch_reg(unsigned int offset)436c349dbc7Sjsg static inline int get_aux_ch_reg(unsigned int offset)
437c349dbc7Sjsg {
438c349dbc7Sjsg int reg;
439c349dbc7Sjsg
440c349dbc7Sjsg switch (offset & 0xff) {
441c349dbc7Sjsg case 0x10:
442c349dbc7Sjsg reg = AUX_CH_CTL;
443c349dbc7Sjsg break;
444c349dbc7Sjsg case 0x14:
445c349dbc7Sjsg reg = AUX_CH_DATA1;
446c349dbc7Sjsg break;
447c349dbc7Sjsg case 0x18:
448c349dbc7Sjsg reg = AUX_CH_DATA2;
449c349dbc7Sjsg break;
450c349dbc7Sjsg case 0x1c:
451c349dbc7Sjsg reg = AUX_CH_DATA3;
452c349dbc7Sjsg break;
453c349dbc7Sjsg case 0x20:
454c349dbc7Sjsg reg = AUX_CH_DATA4;
455c349dbc7Sjsg break;
456c349dbc7Sjsg case 0x24:
457c349dbc7Sjsg reg = AUX_CH_DATA5;
458c349dbc7Sjsg break;
459c349dbc7Sjsg default:
460c349dbc7Sjsg reg = -1;
461c349dbc7Sjsg break;
462c349dbc7Sjsg }
463c349dbc7Sjsg return reg;
464c349dbc7Sjsg }
465c349dbc7Sjsg
466c349dbc7Sjsg /**
467c349dbc7Sjsg * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
468c349dbc7Sjsg * @vgpu: a vGPU
469c349dbc7Sjsg * @port_idx: port index
470c349dbc7Sjsg * @offset: reg offset
471c349dbc7Sjsg * @p_data: write ptr
472c349dbc7Sjsg *
473c349dbc7Sjsg * This function is used to emulate AUX channel register write
474c349dbc7Sjsg *
475c349dbc7Sjsg */
intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu * vgpu,int port_idx,unsigned int offset,void * p_data)476c349dbc7Sjsg void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
477c349dbc7Sjsg int port_idx,
478c349dbc7Sjsg unsigned int offset,
479c349dbc7Sjsg void *p_data)
480c349dbc7Sjsg {
481c349dbc7Sjsg struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
482c349dbc7Sjsg struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
483c349dbc7Sjsg int msg_length, ret_msg_size;
484c349dbc7Sjsg int msg, addr, ctrl, op;
485c349dbc7Sjsg u32 value = *(u32 *)p_data;
486c349dbc7Sjsg int aux_data_for_write = 0;
487c349dbc7Sjsg int reg = get_aux_ch_reg(offset);
488c349dbc7Sjsg
489c349dbc7Sjsg if (reg != AUX_CH_CTL) {
490c349dbc7Sjsg vgpu_vreg(vgpu, offset) = value;
491c349dbc7Sjsg return;
492c349dbc7Sjsg }
493c349dbc7Sjsg
494*f005ef32Sjsg msg_length = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, value);
495*f005ef32Sjsg
496c349dbc7Sjsg // check the msg in DATA register.
497c349dbc7Sjsg msg = vgpu_vreg(vgpu, offset + 4);
498c349dbc7Sjsg addr = (msg >> 8) & 0xffff;
499c349dbc7Sjsg ctrl = (msg >> 24) & 0xff;
500c349dbc7Sjsg op = ctrl >> 4;
501c349dbc7Sjsg if (!(value & DP_AUX_CH_CTL_SEND_BUSY)) {
502c349dbc7Sjsg /* The ctl write to clear some states */
503c349dbc7Sjsg return;
504c349dbc7Sjsg }
505c349dbc7Sjsg
506c349dbc7Sjsg /* Always set the wanted value for vms. */
507c349dbc7Sjsg ret_msg_size = (((op & 0x1) == GVT_AUX_I2C_READ) ? 2 : 1);
508c349dbc7Sjsg vgpu_vreg(vgpu, offset) =
509c349dbc7Sjsg DP_AUX_CH_CTL_DONE |
510*f005ef32Sjsg DP_AUX_CH_CTL_MESSAGE_SIZE(ret_msg_size);
511c349dbc7Sjsg
512c349dbc7Sjsg if (msg_length == 3) {
513c349dbc7Sjsg if (!(op & GVT_AUX_I2C_MOT)) {
514c349dbc7Sjsg /* stop */
515c349dbc7Sjsg intel_vgpu_init_i2c_edid(vgpu);
516c349dbc7Sjsg } else {
517c349dbc7Sjsg /* start or restart */
518c349dbc7Sjsg i2c_edid->aux_ch.i2c_over_aux_ch = true;
519c349dbc7Sjsg i2c_edid->aux_ch.aux_ch_mot = true;
520c349dbc7Sjsg if (addr == 0) {
521c349dbc7Sjsg /* reset the address */
522c349dbc7Sjsg intel_vgpu_init_i2c_edid(vgpu);
523c349dbc7Sjsg } else if (addr == EDID_ADDR) {
524c349dbc7Sjsg i2c_edid->state = I2C_AUX_CH;
525c349dbc7Sjsg i2c_edid->port = port_idx;
526c349dbc7Sjsg i2c_edid->slave_selected = true;
527c349dbc7Sjsg if (intel_vgpu_has_monitor_on_port(vgpu,
528c349dbc7Sjsg port_idx) &&
529c349dbc7Sjsg intel_vgpu_port_is_dp(vgpu, port_idx))
530c349dbc7Sjsg i2c_edid->edid_available = true;
531c349dbc7Sjsg }
532c349dbc7Sjsg }
533c349dbc7Sjsg } else if ((op & 0x1) == GVT_AUX_I2C_WRITE) {
534c349dbc7Sjsg /* TODO
535c349dbc7Sjsg * We only support EDID reading from I2C_over_AUX. And
536c349dbc7Sjsg * we do not expect the index mode to be used. Right now
537c349dbc7Sjsg * the WRITE operation is ignored. It is good enough to
538c349dbc7Sjsg * support the gfx driver to do EDID access.
539c349dbc7Sjsg */
540c349dbc7Sjsg } else {
541c349dbc7Sjsg if (drm_WARN_ON(&i915->drm, (op & 0x1) != GVT_AUX_I2C_READ))
542c349dbc7Sjsg return;
543c349dbc7Sjsg if (drm_WARN_ON(&i915->drm, msg_length != 4))
544c349dbc7Sjsg return;
545c349dbc7Sjsg if (i2c_edid->edid_available && i2c_edid->slave_selected) {
546c349dbc7Sjsg unsigned char val = edid_get_byte(vgpu);
547c349dbc7Sjsg
548c349dbc7Sjsg aux_data_for_write = (val << 16);
549c349dbc7Sjsg } else
550c349dbc7Sjsg aux_data_for_write = (0xff << 16);
551c349dbc7Sjsg }
552c349dbc7Sjsg /* write the return value in AUX_CH_DATA reg which includes:
553c349dbc7Sjsg * ACK of I2C_WRITE
554c349dbc7Sjsg * returned byte if it is READ
555c349dbc7Sjsg */
556c349dbc7Sjsg aux_data_for_write |= GVT_AUX_I2C_REPLY_ACK << 24;
557c349dbc7Sjsg vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
558c349dbc7Sjsg }
559c349dbc7Sjsg
560c349dbc7Sjsg /**
561c349dbc7Sjsg * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation
562c349dbc7Sjsg * @vgpu: a vGPU
563c349dbc7Sjsg *
564c349dbc7Sjsg * This function is used to initialize vGPU i2c edid emulation stuffs
565c349dbc7Sjsg *
566c349dbc7Sjsg */
intel_vgpu_init_i2c_edid(struct intel_vgpu * vgpu)567c349dbc7Sjsg void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu)
568c349dbc7Sjsg {
569c349dbc7Sjsg struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
570c349dbc7Sjsg
571c349dbc7Sjsg edid->state = I2C_NOT_SPECIFIED;
572c349dbc7Sjsg
573c349dbc7Sjsg edid->port = -1;
574c349dbc7Sjsg edid->slave_selected = false;
575c349dbc7Sjsg edid->edid_available = false;
576c349dbc7Sjsg edid->current_edid_read = 0;
577c349dbc7Sjsg
578c349dbc7Sjsg memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus));
579c349dbc7Sjsg
580c349dbc7Sjsg edid->aux_ch.i2c_over_aux_ch = false;
581c349dbc7Sjsg edid->aux_ch.aux_ch_mot = false;
582c349dbc7Sjsg }
583