1c349dbc7Sjsg /* SPDX-License-Identifier: MIT */ 2c349dbc7Sjsg /* 3c349dbc7Sjsg * Copyright © 2019 Intel Corporation 4c349dbc7Sjsg */ 5c349dbc7Sjsg 6c349dbc7Sjsg #ifndef __I915_IRQ_H__ 7c349dbc7Sjsg #define __I915_IRQ_H__ 8c349dbc7Sjsg 9c349dbc7Sjsg #include <linux/ktime.h> 10c349dbc7Sjsg #include <linux/types.h> 11c349dbc7Sjsg 12*f005ef32Sjsg #include "i915_reg_defs.h" 13c349dbc7Sjsg 141bb76ff1Sjsg enum pipe; 15c349dbc7Sjsg struct drm_crtc; 16c349dbc7Sjsg struct drm_device; 17c349dbc7Sjsg struct drm_display_mode; 18c349dbc7Sjsg struct drm_i915_private; 19c349dbc7Sjsg struct intel_crtc; 20*f005ef32Sjsg struct intel_encoder; 21c349dbc7Sjsg struct intel_uncore; 22c349dbc7Sjsg 23c349dbc7Sjsg void intel_irq_init(struct drm_i915_private *dev_priv); 24c349dbc7Sjsg void intel_irq_fini(struct drm_i915_private *dev_priv); 25c349dbc7Sjsg int intel_irq_install(struct drm_i915_private *dev_priv); 26c349dbc7Sjsg void intel_irq_uninstall(struct drm_i915_private *dev_priv); 27c349dbc7Sjsg 28c349dbc7Sjsg void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask); 29c349dbc7Sjsg void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask); 30c349dbc7Sjsg void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv); 31c349dbc7Sjsg void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv); 32c349dbc7Sjsg void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv); 33c349dbc7Sjsg void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv); 34c349dbc7Sjsg void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); 35c349dbc7Sjsg u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask); 36c349dbc7Sjsg 37c349dbc7Sjsg void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); 38c349dbc7Sjsg void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); 39c349dbc7Sjsg bool intel_irqs_enabled(struct drm_i915_private *dev_priv); 40c349dbc7Sjsg void intel_synchronize_irq(struct drm_i915_private *i915); 415ca02815Sjsg void intel_synchronize_hardirq(struct drm_i915_private *i915); 42c349dbc7Sjsg 43*f005ef32Sjsg void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg); 44c349dbc7Sjsg 45c349dbc7Sjsg void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, 46c349dbc7Sjsg i915_reg_t iir, i915_reg_t ier); 47c349dbc7Sjsg 48c349dbc7Sjsg void gen3_irq_init(struct intel_uncore *uncore, 49c349dbc7Sjsg i915_reg_t imr, u32 imr_val, 50c349dbc7Sjsg i915_reg_t ier, u32 ier_val, 51c349dbc7Sjsg i915_reg_t iir); 52c349dbc7Sjsg 53c349dbc7Sjsg #define GEN8_IRQ_RESET_NDX(uncore, type, which) \ 54c349dbc7Sjsg ({ \ 55c349dbc7Sjsg unsigned int which_ = which; \ 56c349dbc7Sjsg gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \ 57c349dbc7Sjsg GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \ 58c349dbc7Sjsg }) 59c349dbc7Sjsg 60c349dbc7Sjsg #define GEN3_IRQ_RESET(uncore, type) \ 61c349dbc7Sjsg gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER) 62c349dbc7Sjsg 63c349dbc7Sjsg #define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \ 64c349dbc7Sjsg ({ \ 65c349dbc7Sjsg unsigned int which_ = which; \ 66c349dbc7Sjsg gen3_irq_init((uncore), \ 67c349dbc7Sjsg GEN8_##type##_IMR(which_), imr_val, \ 68c349dbc7Sjsg GEN8_##type##_IER(which_), ier_val, \ 69c349dbc7Sjsg GEN8_##type##_IIR(which_)); \ 70c349dbc7Sjsg }) 71c349dbc7Sjsg 72c349dbc7Sjsg #define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \ 73c349dbc7Sjsg gen3_irq_init((uncore), \ 74c349dbc7Sjsg type##IMR, imr_val, \ 75c349dbc7Sjsg type##IER, ier_val, \ 76c349dbc7Sjsg type##IIR) 77c349dbc7Sjsg 78c349dbc7Sjsg #endif /* __I915_IRQ_H__ */ 79