17f4dd379Sjsg /*
27f4dd379Sjsg * Copyright © 2016 Intel Corporation
37f4dd379Sjsg *
47f4dd379Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
57f4dd379Sjsg * copy of this software and associated documentation files (the "Software"),
67f4dd379Sjsg * to deal in the Software without restriction, including without limitation
77f4dd379Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
87f4dd379Sjsg * and/or sell copies of the Software, and to permit persons to whom the
97f4dd379Sjsg * Software is furnished to do so, subject to the following conditions:
107f4dd379Sjsg *
117f4dd379Sjsg * The above copyright notice and this permission notice (including the next
127f4dd379Sjsg * paragraph) shall be included in all copies or substantial portions of the
137f4dd379Sjsg * Software.
147f4dd379Sjsg *
157f4dd379Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
167f4dd379Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
177f4dd379Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
187f4dd379Sjsg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
197f4dd379Sjsg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
207f4dd379Sjsg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
217f4dd379Sjsg * IN THE SOFTWARE.
227f4dd379Sjsg *
237f4dd379Sjsg */
247f4dd379Sjsg
251bb76ff1Sjsg #include <drm/drm_color_mgmt.h>
26c349dbc7Sjsg #include <drm/drm_drv.h>
27c349dbc7Sjsg #include <drm/i915_pciids.h>
28c349dbc7Sjsg
29f005ef32Sjsg #include "display/intel_display.h"
30f005ef32Sjsg #include "display/intel_display_driver.h"
311bb76ff1Sjsg #include "gt/intel_gt_regs.h"
321bb76ff1Sjsg #include "gt/intel_sa_media.h"
33f005ef32Sjsg #include "gem/i915_gem_object_types.h"
341bb76ff1Sjsg
351bb76ff1Sjsg #include "i915_driver.h"
367f4dd379Sjsg #include "i915_drv.h"
375ca02815Sjsg #include "i915_pci.h"
381bb76ff1Sjsg #include "i915_reg.h"
391bb76ff1Sjsg #include "intel_pci_config.h"
407f4dd379Sjsg
41c349dbc7Sjsg #define PLATFORM(x) .platform = (x)
425ca02815Sjsg #define GEN(x) \
431bb76ff1Sjsg .__runtime.graphics.ip.ver = (x), \
44f005ef32Sjsg .__runtime.media.ip.ver = (x)
451bb76ff1Sjsg
46f005ef32Sjsg #define LEGACY_CACHELEVEL \
47f005ef32Sjsg .cachelevel_to_pat = { \
48f005ef32Sjsg [I915_CACHE_NONE] = 0, \
49f005ef32Sjsg [I915_CACHE_LLC] = 1, \
50f005ef32Sjsg [I915_CACHE_L3_LLC] = 2, \
51f005ef32Sjsg [I915_CACHE_WT] = 3, \
52c349dbc7Sjsg }
537f4dd379Sjsg
54f005ef32Sjsg #define TGL_CACHELEVEL \
55f005ef32Sjsg .cachelevel_to_pat = { \
56f005ef32Sjsg [I915_CACHE_NONE] = 3, \
57f005ef32Sjsg [I915_CACHE_LLC] = 0, \
58f005ef32Sjsg [I915_CACHE_L3_LLC] = 0, \
59f005ef32Sjsg [I915_CACHE_WT] = 2, \
60c349dbc7Sjsg }
617f4dd379Sjsg
62f005ef32Sjsg #define PVC_CACHELEVEL \
63f005ef32Sjsg .cachelevel_to_pat = { \
64f005ef32Sjsg [I915_CACHE_NONE] = 0, \
65f005ef32Sjsg [I915_CACHE_LLC] = 3, \
66f005ef32Sjsg [I915_CACHE_L3_LLC] = 3, \
67f005ef32Sjsg [I915_CACHE_WT] = 2, \
68c349dbc7Sjsg }
69c349dbc7Sjsg
70f005ef32Sjsg #define MTL_CACHELEVEL \
71f005ef32Sjsg .cachelevel_to_pat = { \
72f005ef32Sjsg [I915_CACHE_NONE] = 2, \
73f005ef32Sjsg [I915_CACHE_LLC] = 3, \
74f005ef32Sjsg [I915_CACHE_L3_LLC] = 3, \
75f005ef32Sjsg [I915_CACHE_WT] = 1, \
761bb76ff1Sjsg }
777f4dd379Sjsg
787f4dd379Sjsg /* Keep in gen based order, and chronological order within a gen */
797f4dd379Sjsg
807f4dd379Sjsg #define GEN_DEFAULT_PAGE_SIZES \
811bb76ff1Sjsg .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K
827f4dd379Sjsg
83c349dbc7Sjsg #define GEN_DEFAULT_REGIONS \
84f005ef32Sjsg .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
85c349dbc7Sjsg
86c349dbc7Sjsg #define I830_FEATURES \
877f4dd379Sjsg GEN(2), \
88c349dbc7Sjsg .is_mobile = 1, \
89c349dbc7Sjsg .gpu_reset_clobbers_display = true, \
901bb76ff1Sjsg .has_3d_pipeline = 1, \
917f4dd379Sjsg .hws_needs_physical = 1, \
927f4dd379Sjsg .unfenced_needs_alignment = 1, \
93f005ef32Sjsg .platform_engine_mask = BIT(RCS0), \
947f4dd379Sjsg .has_snoop = true, \
95c349dbc7Sjsg .has_coherent_ggtt = false, \
96ad8b1aafSjsg .dma_mask_size = 32, \
97f005ef32Sjsg .max_pat_index = 3, \
987f4dd379Sjsg GEN_DEFAULT_PAGE_SIZES, \
99f005ef32Sjsg GEN_DEFAULT_REGIONS, \
100f005ef32Sjsg LEGACY_CACHELEVEL
1017f4dd379Sjsg
102c349dbc7Sjsg #define I845_FEATURES \
103c349dbc7Sjsg GEN(2), \
1041bb76ff1Sjsg .has_3d_pipeline = 1, \
105c349dbc7Sjsg .gpu_reset_clobbers_display = true, \
106c349dbc7Sjsg .hws_needs_physical = 1, \
107c349dbc7Sjsg .unfenced_needs_alignment = 1, \
108f005ef32Sjsg .platform_engine_mask = BIT(RCS0), \
109c349dbc7Sjsg .has_snoop = true, \
110c349dbc7Sjsg .has_coherent_ggtt = false, \
111ad8b1aafSjsg .dma_mask_size = 32, \
112f005ef32Sjsg .max_pat_index = 3, \
113c349dbc7Sjsg GEN_DEFAULT_PAGE_SIZES, \
114f005ef32Sjsg GEN_DEFAULT_REGIONS, \
115f005ef32Sjsg LEGACY_CACHELEVEL
116c349dbc7Sjsg
117c349dbc7Sjsg static const struct intel_device_info i830_info = {
118c349dbc7Sjsg I830_FEATURES,
1197f4dd379Sjsg PLATFORM(INTEL_I830),
1207f4dd379Sjsg };
1217f4dd379Sjsg
122c349dbc7Sjsg static const struct intel_device_info i845g_info = {
123c349dbc7Sjsg I845_FEATURES,
1247f4dd379Sjsg PLATFORM(INTEL_I845G),
1257f4dd379Sjsg };
1267f4dd379Sjsg
127c349dbc7Sjsg static const struct intel_device_info i85x_info = {
128c349dbc7Sjsg I830_FEATURES,
1297f4dd379Sjsg PLATFORM(INTEL_I85X),
1307f4dd379Sjsg };
1317f4dd379Sjsg
132c349dbc7Sjsg static const struct intel_device_info i865g_info = {
133c349dbc7Sjsg I845_FEATURES,
1347f4dd379Sjsg PLATFORM(INTEL_I865G),
1357f4dd379Sjsg };
1367f4dd379Sjsg
1377f4dd379Sjsg #define GEN3_FEATURES \
1387f4dd379Sjsg GEN(3), \
139c349dbc7Sjsg .gpu_reset_clobbers_display = true, \
140f005ef32Sjsg .platform_engine_mask = BIT(RCS0), \
1411bb76ff1Sjsg .has_3d_pipeline = 1, \
1427f4dd379Sjsg .has_snoop = true, \
143c349dbc7Sjsg .has_coherent_ggtt = true, \
144ad8b1aafSjsg .dma_mask_size = 32, \
145f005ef32Sjsg .max_pat_index = 3, \
1467f4dd379Sjsg GEN_DEFAULT_PAGE_SIZES, \
147f005ef32Sjsg GEN_DEFAULT_REGIONS, \
148f005ef32Sjsg LEGACY_CACHELEVEL
1497f4dd379Sjsg
150c349dbc7Sjsg static const struct intel_device_info i915g_info = {
1517f4dd379Sjsg GEN3_FEATURES,
1527f4dd379Sjsg PLATFORM(INTEL_I915G),
153c349dbc7Sjsg .has_coherent_ggtt = false,
1547f4dd379Sjsg .hws_needs_physical = 1,
1557f4dd379Sjsg .unfenced_needs_alignment = 1,
1567f4dd379Sjsg };
1577f4dd379Sjsg
158c349dbc7Sjsg static const struct intel_device_info i915gm_info = {
1597f4dd379Sjsg GEN3_FEATURES,
1607f4dd379Sjsg PLATFORM(INTEL_I915GM),
1617f4dd379Sjsg .is_mobile = 1,
1627f4dd379Sjsg .hws_needs_physical = 1,
1637f4dd379Sjsg .unfenced_needs_alignment = 1,
1647f4dd379Sjsg };
1657f4dd379Sjsg
166c349dbc7Sjsg static const struct intel_device_info i945g_info = {
1677f4dd379Sjsg GEN3_FEATURES,
1687f4dd379Sjsg PLATFORM(INTEL_I945G),
1697f4dd379Sjsg .hws_needs_physical = 1,
1707f4dd379Sjsg .unfenced_needs_alignment = 1,
1717f4dd379Sjsg };
1727f4dd379Sjsg
173c349dbc7Sjsg static const struct intel_device_info i945gm_info = {
1747f4dd379Sjsg GEN3_FEATURES,
1757f4dd379Sjsg PLATFORM(INTEL_I945GM),
1767f4dd379Sjsg .is_mobile = 1,
1777f4dd379Sjsg .hws_needs_physical = 1,
1787f4dd379Sjsg .unfenced_needs_alignment = 1,
1797f4dd379Sjsg };
1807f4dd379Sjsg
181c349dbc7Sjsg static const struct intel_device_info g33_info = {
1827f4dd379Sjsg GEN3_FEATURES,
1837f4dd379Sjsg PLATFORM(INTEL_G33),
184ad8b1aafSjsg .dma_mask_size = 36,
1857f4dd379Sjsg };
1867f4dd379Sjsg
187c349dbc7Sjsg static const struct intel_device_info pnv_g_info = {
188c349dbc7Sjsg GEN3_FEATURES,
189c349dbc7Sjsg PLATFORM(INTEL_PINEVIEW),
190ad8b1aafSjsg .dma_mask_size = 36,
191c349dbc7Sjsg };
192c349dbc7Sjsg
193c349dbc7Sjsg static const struct intel_device_info pnv_m_info = {
1947f4dd379Sjsg GEN3_FEATURES,
1957f4dd379Sjsg PLATFORM(INTEL_PINEVIEW),
1967f4dd379Sjsg .is_mobile = 1,
197ad8b1aafSjsg .dma_mask_size = 36,
1987f4dd379Sjsg };
1997f4dd379Sjsg
2007f4dd379Sjsg #define GEN4_FEATURES \
2017f4dd379Sjsg GEN(4), \
202c349dbc7Sjsg .gpu_reset_clobbers_display = true, \
203f005ef32Sjsg .platform_engine_mask = BIT(RCS0), \
2041bb76ff1Sjsg .has_3d_pipeline = 1, \
2057f4dd379Sjsg .has_snoop = true, \
206c349dbc7Sjsg .has_coherent_ggtt = true, \
207ad8b1aafSjsg .dma_mask_size = 36, \
208f005ef32Sjsg .max_pat_index = 3, \
2097f4dd379Sjsg GEN_DEFAULT_PAGE_SIZES, \
210f005ef32Sjsg GEN_DEFAULT_REGIONS, \
211f005ef32Sjsg LEGACY_CACHELEVEL
2127f4dd379Sjsg
213c349dbc7Sjsg static const struct intel_device_info i965g_info = {
2147f4dd379Sjsg GEN4_FEATURES,
2157f4dd379Sjsg PLATFORM(INTEL_I965G),
2167f4dd379Sjsg .hws_needs_physical = 1,
2177f4dd379Sjsg .has_snoop = false,
2187f4dd379Sjsg };
2197f4dd379Sjsg
220c349dbc7Sjsg static const struct intel_device_info i965gm_info = {
2217f4dd379Sjsg GEN4_FEATURES,
2227f4dd379Sjsg PLATFORM(INTEL_I965GM),
223c349dbc7Sjsg .is_mobile = 1,
2247f4dd379Sjsg .hws_needs_physical = 1,
2257f4dd379Sjsg .has_snoop = false,
2267f4dd379Sjsg };
2277f4dd379Sjsg
228c349dbc7Sjsg static const struct intel_device_info g45_info = {
2297f4dd379Sjsg GEN4_FEATURES,
2307f4dd379Sjsg PLATFORM(INTEL_G45),
231f005ef32Sjsg .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
232c349dbc7Sjsg .gpu_reset_clobbers_display = false,
2337f4dd379Sjsg };
2347f4dd379Sjsg
235c349dbc7Sjsg static const struct intel_device_info gm45_info = {
2367f4dd379Sjsg GEN4_FEATURES,
2377f4dd379Sjsg PLATFORM(INTEL_GM45),
238c349dbc7Sjsg .is_mobile = 1,
239f005ef32Sjsg .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
240c349dbc7Sjsg .gpu_reset_clobbers_display = false,
2417f4dd379Sjsg };
2427f4dd379Sjsg
2437f4dd379Sjsg #define GEN5_FEATURES \
2447f4dd379Sjsg GEN(5), \
245f005ef32Sjsg .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
2461bb76ff1Sjsg .has_3d_pipeline = 1, \
2477f4dd379Sjsg .has_snoop = true, \
248c349dbc7Sjsg .has_coherent_ggtt = true, \
2497f4dd379Sjsg /* ilk does support rc6, but we do not implement [power] contexts */ \
2507f4dd379Sjsg .has_rc6 = 0, \
251ad8b1aafSjsg .dma_mask_size = 36, \
252f005ef32Sjsg .max_pat_index = 3, \
2537f4dd379Sjsg GEN_DEFAULT_PAGE_SIZES, \
254f005ef32Sjsg GEN_DEFAULT_REGIONS, \
255f005ef32Sjsg LEGACY_CACHELEVEL
2567f4dd379Sjsg
257c349dbc7Sjsg static const struct intel_device_info ilk_d_info = {
2587f4dd379Sjsg GEN5_FEATURES,
2597f4dd379Sjsg PLATFORM(INTEL_IRONLAKE),
2607f4dd379Sjsg };
2617f4dd379Sjsg
262c349dbc7Sjsg static const struct intel_device_info ilk_m_info = {
2637f4dd379Sjsg GEN5_FEATURES,
2647f4dd379Sjsg PLATFORM(INTEL_IRONLAKE),
265c349dbc7Sjsg .is_mobile = 1,
266ad8b1aafSjsg .has_rps = true,
2677f4dd379Sjsg };
2687f4dd379Sjsg
2697f4dd379Sjsg #define GEN6_FEATURES \
2707f4dd379Sjsg GEN(6), \
271f005ef32Sjsg .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
2721bb76ff1Sjsg .has_3d_pipeline = 1, \
273c349dbc7Sjsg .has_coherent_ggtt = true, \
2747f4dd379Sjsg .has_llc = 1, \
2757f4dd379Sjsg .has_rc6 = 1, \
276af8eca09Sjsg /* snb does support rc6p, but enabling it causes various issues */ \
277af8eca09Sjsg .has_rc6p = 0, \
278c349dbc7Sjsg .has_rps = true, \
279ad8b1aafSjsg .dma_mask_size = 40, \
280f005ef32Sjsg .max_pat_index = 3, \
2811bb76ff1Sjsg .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
2821bb76ff1Sjsg .__runtime.ppgtt_size = 31, \
2837f4dd379Sjsg GEN_DEFAULT_PAGE_SIZES, \
284f005ef32Sjsg GEN_DEFAULT_REGIONS, \
285f005ef32Sjsg LEGACY_CACHELEVEL
2867f4dd379Sjsg
2877f4dd379Sjsg #define SNB_D_PLATFORM \
2887f4dd379Sjsg GEN6_FEATURES, \
2897f4dd379Sjsg PLATFORM(INTEL_SANDYBRIDGE)
2907f4dd379Sjsg
291c349dbc7Sjsg static const struct intel_device_info snb_d_gt1_info = {
2927f4dd379Sjsg SNB_D_PLATFORM,
2937f4dd379Sjsg .gt = 1,
2947f4dd379Sjsg };
2957f4dd379Sjsg
296c349dbc7Sjsg static const struct intel_device_info snb_d_gt2_info = {
2977f4dd379Sjsg SNB_D_PLATFORM,
2987f4dd379Sjsg .gt = 2,
2997f4dd379Sjsg };
3007f4dd379Sjsg
3017f4dd379Sjsg #define SNB_M_PLATFORM \
3027f4dd379Sjsg GEN6_FEATURES, \
3037f4dd379Sjsg PLATFORM(INTEL_SANDYBRIDGE), \
3047f4dd379Sjsg .is_mobile = 1
3057f4dd379Sjsg
3067f4dd379Sjsg
307c349dbc7Sjsg static const struct intel_device_info snb_m_gt1_info = {
3087f4dd379Sjsg SNB_M_PLATFORM,
3097f4dd379Sjsg .gt = 1,
3107f4dd379Sjsg };
3117f4dd379Sjsg
312c349dbc7Sjsg static const struct intel_device_info snb_m_gt2_info = {
3137f4dd379Sjsg SNB_M_PLATFORM,
3147f4dd379Sjsg .gt = 2,
3157f4dd379Sjsg };
3167f4dd379Sjsg
3177f4dd379Sjsg #define GEN7_FEATURES \
3187f4dd379Sjsg GEN(7), \
319f005ef32Sjsg .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
3201bb76ff1Sjsg .has_3d_pipeline = 1, \
321c349dbc7Sjsg .has_coherent_ggtt = true, \
3227f4dd379Sjsg .has_llc = 1, \
3237f4dd379Sjsg .has_rc6 = 1, \
3247f4dd379Sjsg .has_rc6p = 1, \
3255ca02815Sjsg .has_reset_engine = true, \
326c349dbc7Sjsg .has_rps = true, \
327ad8b1aafSjsg .dma_mask_size = 40, \
328f005ef32Sjsg .max_pat_index = 3, \
3291bb76ff1Sjsg .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
3301bb76ff1Sjsg .__runtime.ppgtt_size = 31, \
3317f4dd379Sjsg GEN_DEFAULT_PAGE_SIZES, \
332f005ef32Sjsg GEN_DEFAULT_REGIONS, \
333f005ef32Sjsg LEGACY_CACHELEVEL
3347f4dd379Sjsg
3357f4dd379Sjsg #define IVB_D_PLATFORM \
3367f4dd379Sjsg GEN7_FEATURES, \
3377f4dd379Sjsg PLATFORM(INTEL_IVYBRIDGE), \
3387f4dd379Sjsg .has_l3_dpf = 1
3397f4dd379Sjsg
340c349dbc7Sjsg static const struct intel_device_info ivb_d_gt1_info = {
3417f4dd379Sjsg IVB_D_PLATFORM,
3427f4dd379Sjsg .gt = 1,
3437f4dd379Sjsg };
3447f4dd379Sjsg
345c349dbc7Sjsg static const struct intel_device_info ivb_d_gt2_info = {
3467f4dd379Sjsg IVB_D_PLATFORM,
3477f4dd379Sjsg .gt = 2,
3487f4dd379Sjsg };
3497f4dd379Sjsg
3507f4dd379Sjsg #define IVB_M_PLATFORM \
3517f4dd379Sjsg GEN7_FEATURES, \
3527f4dd379Sjsg PLATFORM(INTEL_IVYBRIDGE), \
3537f4dd379Sjsg .is_mobile = 1, \
3547f4dd379Sjsg .has_l3_dpf = 1
3557f4dd379Sjsg
356c349dbc7Sjsg static const struct intel_device_info ivb_m_gt1_info = {
3577f4dd379Sjsg IVB_M_PLATFORM,
3587f4dd379Sjsg .gt = 1,
3597f4dd379Sjsg };
3607f4dd379Sjsg
361c349dbc7Sjsg static const struct intel_device_info ivb_m_gt2_info = {
3627f4dd379Sjsg IVB_M_PLATFORM,
3637f4dd379Sjsg .gt = 2,
3647f4dd379Sjsg };
3657f4dd379Sjsg
366c349dbc7Sjsg static const struct intel_device_info ivb_q_info = {
3677f4dd379Sjsg GEN7_FEATURES,
3687f4dd379Sjsg PLATFORM(INTEL_IVYBRIDGE),
3697f4dd379Sjsg .gt = 2,
3707f4dd379Sjsg .has_l3_dpf = 1,
3717f4dd379Sjsg };
3727f4dd379Sjsg
373c349dbc7Sjsg static const struct intel_device_info vlv_info = {
3747f4dd379Sjsg PLATFORM(INTEL_VALLEYVIEW),
3757f4dd379Sjsg GEN(7),
3767f4dd379Sjsg .is_lp = 1,
3777f4dd379Sjsg .has_runtime_pm = 1,
3787f4dd379Sjsg .has_rc6 = 1,
3795ca02815Sjsg .has_reset_engine = true,
380c349dbc7Sjsg .has_rps = true,
381ad8b1aafSjsg .dma_mask_size = 40,
382f005ef32Sjsg .max_pat_index = 3,
3831bb76ff1Sjsg .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
3841bb76ff1Sjsg .__runtime.ppgtt_size = 31,
3857f4dd379Sjsg .has_snoop = true,
386c349dbc7Sjsg .has_coherent_ggtt = false,
387f005ef32Sjsg .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
3887f4dd379Sjsg GEN_DEFAULT_PAGE_SIZES,
389c349dbc7Sjsg GEN_DEFAULT_REGIONS,
390f005ef32Sjsg LEGACY_CACHELEVEL,
3917f4dd379Sjsg };
3927f4dd379Sjsg
3937f4dd379Sjsg #define G75_FEATURES \
3947f4dd379Sjsg GEN7_FEATURES, \
395f005ef32Sjsg .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
3967f4dd379Sjsg .has_rc6p = 0 /* RC6p removed-by HSW */, \
3977f4dd379Sjsg .has_runtime_pm = 1
3987f4dd379Sjsg
3997f4dd379Sjsg #define HSW_PLATFORM \
4007f4dd379Sjsg G75_FEATURES, \
4017f4dd379Sjsg PLATFORM(INTEL_HASWELL), \
4027f4dd379Sjsg .has_l3_dpf = 1
4037f4dd379Sjsg
404c349dbc7Sjsg static const struct intel_device_info hsw_gt1_info = {
4057f4dd379Sjsg HSW_PLATFORM,
4067f4dd379Sjsg .gt = 1,
4077f4dd379Sjsg };
4087f4dd379Sjsg
409c349dbc7Sjsg static const struct intel_device_info hsw_gt2_info = {
4107f4dd379Sjsg HSW_PLATFORM,
4117f4dd379Sjsg .gt = 2,
4127f4dd379Sjsg };
4137f4dd379Sjsg
414c349dbc7Sjsg static const struct intel_device_info hsw_gt3_info = {
4157f4dd379Sjsg HSW_PLATFORM,
4167f4dd379Sjsg .gt = 3,
4177f4dd379Sjsg };
4187f4dd379Sjsg
4197f4dd379Sjsg #define GEN8_FEATURES \
4207f4dd379Sjsg G75_FEATURES, \
4217f4dd379Sjsg GEN(8), \
4227f4dd379Sjsg .has_logical_ring_contexts = 1, \
423ad8b1aafSjsg .dma_mask_size = 39, \
4241bb76ff1Sjsg .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
4251bb76ff1Sjsg .__runtime.ppgtt_size = 48, \
4265ca02815Sjsg .has_64bit_reloc = 1
4277f4dd379Sjsg
4287f4dd379Sjsg #define BDW_PLATFORM \
4297f4dd379Sjsg GEN8_FEATURES, \
4307f4dd379Sjsg PLATFORM(INTEL_BROADWELL)
4317f4dd379Sjsg
432c349dbc7Sjsg static const struct intel_device_info bdw_gt1_info = {
4337f4dd379Sjsg BDW_PLATFORM,
4347f4dd379Sjsg .gt = 1,
4357f4dd379Sjsg };
4367f4dd379Sjsg
437c349dbc7Sjsg static const struct intel_device_info bdw_gt2_info = {
4387f4dd379Sjsg BDW_PLATFORM,
4397f4dd379Sjsg .gt = 2,
4407f4dd379Sjsg };
4417f4dd379Sjsg
442c349dbc7Sjsg static const struct intel_device_info bdw_rsvd_info = {
4437f4dd379Sjsg BDW_PLATFORM,
4447f4dd379Sjsg .gt = 3,
4457f4dd379Sjsg /* According to the device ID those devices are GT3, they were
4467f4dd379Sjsg * previously treated as not GT3, keep it like that.
4477f4dd379Sjsg */
4487f4dd379Sjsg };
4497f4dd379Sjsg
450c349dbc7Sjsg static const struct intel_device_info bdw_gt3_info = {
4517f4dd379Sjsg BDW_PLATFORM,
4527f4dd379Sjsg .gt = 3,
453f005ef32Sjsg .platform_engine_mask =
454c349dbc7Sjsg BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
4557f4dd379Sjsg };
4567f4dd379Sjsg
457c349dbc7Sjsg static const struct intel_device_info chv_info = {
4587f4dd379Sjsg PLATFORM(INTEL_CHERRYVIEW),
4597f4dd379Sjsg GEN(8),
4607f4dd379Sjsg .is_lp = 1,
461f005ef32Sjsg .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
4627f4dd379Sjsg .has_64bit_reloc = 1,
4637f4dd379Sjsg .has_runtime_pm = 1,
4647f4dd379Sjsg .has_rc6 = 1,
465c349dbc7Sjsg .has_rps = true,
4667f4dd379Sjsg .has_logical_ring_contexts = 1,
467ad8b1aafSjsg .dma_mask_size = 39,
468f005ef32Sjsg .max_pat_index = 3,
4691bb76ff1Sjsg .__runtime.ppgtt_type = INTEL_PPGTT_FULL,
4701bb76ff1Sjsg .__runtime.ppgtt_size = 32,
4717f4dd379Sjsg .has_reset_engine = 1,
4727f4dd379Sjsg .has_snoop = true,
473c349dbc7Sjsg .has_coherent_ggtt = false,
474c349dbc7Sjsg GEN_DEFAULT_PAGE_SIZES,
475c349dbc7Sjsg GEN_DEFAULT_REGIONS,
476f005ef32Sjsg LEGACY_CACHELEVEL,
4777f4dd379Sjsg };
4787f4dd379Sjsg
4797f4dd379Sjsg #define GEN9_DEFAULT_PAGE_SIZES \
4801bb76ff1Sjsg .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
481c349dbc7Sjsg I915_GTT_PAGE_SIZE_64K
4827f4dd379Sjsg
4837f4dd379Sjsg #define GEN9_FEATURES \
4847f4dd379Sjsg GEN8_FEATURES, \
4857f4dd379Sjsg GEN(9), \
4867f4dd379Sjsg GEN9_DEFAULT_PAGE_SIZES, \
487f005ef32Sjsg .has_gt_uc = 1
4887f4dd379Sjsg
4897f4dd379Sjsg #define SKL_PLATFORM \
4907f4dd379Sjsg GEN9_FEATURES, \
4917f4dd379Sjsg PLATFORM(INTEL_SKYLAKE)
4927f4dd379Sjsg
493c349dbc7Sjsg static const struct intel_device_info skl_gt1_info = {
4947f4dd379Sjsg SKL_PLATFORM,
4957f4dd379Sjsg .gt = 1,
4967f4dd379Sjsg };
4977f4dd379Sjsg
498c349dbc7Sjsg static const struct intel_device_info skl_gt2_info = {
4997f4dd379Sjsg SKL_PLATFORM,
5007f4dd379Sjsg .gt = 2,
5017f4dd379Sjsg };
5027f4dd379Sjsg
5037f4dd379Sjsg #define SKL_GT3_PLUS_PLATFORM \
5047f4dd379Sjsg SKL_PLATFORM, \
505f005ef32Sjsg .platform_engine_mask = \
506c349dbc7Sjsg BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
5077f4dd379Sjsg
5087f4dd379Sjsg
509c349dbc7Sjsg static const struct intel_device_info skl_gt3_info = {
5107f4dd379Sjsg SKL_GT3_PLUS_PLATFORM,
5117f4dd379Sjsg .gt = 3,
5127f4dd379Sjsg };
5137f4dd379Sjsg
514c349dbc7Sjsg static const struct intel_device_info skl_gt4_info = {
5157f4dd379Sjsg SKL_GT3_PLUS_PLATFORM,
5167f4dd379Sjsg .gt = 4,
5177f4dd379Sjsg };
5187f4dd379Sjsg
5197f4dd379Sjsg #define GEN9_LP_FEATURES \
5207f4dd379Sjsg GEN(9), \
5217f4dd379Sjsg .is_lp = 1, \
522f005ef32Sjsg .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
5231bb76ff1Sjsg .has_3d_pipeline = 1, \
5247f4dd379Sjsg .has_64bit_reloc = 1, \
5257f4dd379Sjsg .has_runtime_pm = 1, \
5267f4dd379Sjsg .has_rc6 = 1, \
527c349dbc7Sjsg .has_rps = true, \
5287f4dd379Sjsg .has_logical_ring_contexts = 1, \
529c349dbc7Sjsg .has_gt_uc = 1, \
530ad8b1aafSjsg .dma_mask_size = 39, \
5311bb76ff1Sjsg .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
5321bb76ff1Sjsg .__runtime.ppgtt_size = 48, \
5337f4dd379Sjsg .has_reset_engine = 1, \
5347f4dd379Sjsg .has_snoop = true, \
535c349dbc7Sjsg .has_coherent_ggtt = false, \
536f005ef32Sjsg .max_pat_index = 3, \
537c349dbc7Sjsg GEN9_DEFAULT_PAGE_SIZES, \
538f005ef32Sjsg GEN_DEFAULT_REGIONS, \
539f005ef32Sjsg LEGACY_CACHELEVEL
5407f4dd379Sjsg
541c349dbc7Sjsg static const struct intel_device_info bxt_info = {
5427f4dd379Sjsg GEN9_LP_FEATURES,
5437f4dd379Sjsg PLATFORM(INTEL_BROXTON),
5447f4dd379Sjsg };
5457f4dd379Sjsg
546c349dbc7Sjsg static const struct intel_device_info glk_info = {
5477f4dd379Sjsg GEN9_LP_FEATURES,
5487f4dd379Sjsg PLATFORM(INTEL_GEMINILAKE),
5497f4dd379Sjsg };
5507f4dd379Sjsg
5517f4dd379Sjsg #define KBL_PLATFORM \
5527f4dd379Sjsg GEN9_FEATURES, \
5537f4dd379Sjsg PLATFORM(INTEL_KABYLAKE)
5547f4dd379Sjsg
555c349dbc7Sjsg static const struct intel_device_info kbl_gt1_info = {
5567f4dd379Sjsg KBL_PLATFORM,
5577f4dd379Sjsg .gt = 1,
5587f4dd379Sjsg };
5597f4dd379Sjsg
560c349dbc7Sjsg static const struct intel_device_info kbl_gt2_info = {
5617f4dd379Sjsg KBL_PLATFORM,
5627f4dd379Sjsg .gt = 2,
5637f4dd379Sjsg };
5647f4dd379Sjsg
565c349dbc7Sjsg static const struct intel_device_info kbl_gt3_info = {
5667f4dd379Sjsg KBL_PLATFORM,
5677f4dd379Sjsg .gt = 3,
568f005ef32Sjsg .platform_engine_mask =
569c349dbc7Sjsg BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
5707f4dd379Sjsg };
5717f4dd379Sjsg
5727f4dd379Sjsg #define CFL_PLATFORM \
5737f4dd379Sjsg GEN9_FEATURES, \
5747f4dd379Sjsg PLATFORM(INTEL_COFFEELAKE)
5757f4dd379Sjsg
576c349dbc7Sjsg static const struct intel_device_info cfl_gt1_info = {
5777f4dd379Sjsg CFL_PLATFORM,
5787f4dd379Sjsg .gt = 1,
5797f4dd379Sjsg };
5807f4dd379Sjsg
581c349dbc7Sjsg static const struct intel_device_info cfl_gt2_info = {
5827f4dd379Sjsg CFL_PLATFORM,
5837f4dd379Sjsg .gt = 2,
5847f4dd379Sjsg };
5857f4dd379Sjsg
586c349dbc7Sjsg static const struct intel_device_info cfl_gt3_info = {
5877f4dd379Sjsg CFL_PLATFORM,
5887f4dd379Sjsg .gt = 3,
589f005ef32Sjsg .platform_engine_mask =
590c349dbc7Sjsg BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
5917f4dd379Sjsg };
5927f4dd379Sjsg
593ad8b1aafSjsg #define CML_PLATFORM \
594ad8b1aafSjsg GEN9_FEATURES, \
595ad8b1aafSjsg PLATFORM(INTEL_COMETLAKE)
596ad8b1aafSjsg
597ad8b1aafSjsg static const struct intel_device_info cml_gt1_info = {
598ad8b1aafSjsg CML_PLATFORM,
599ad8b1aafSjsg .gt = 1,
600ad8b1aafSjsg };
601ad8b1aafSjsg
602ad8b1aafSjsg static const struct intel_device_info cml_gt2_info = {
603ad8b1aafSjsg CML_PLATFORM,
604ad8b1aafSjsg .gt = 2,
605ad8b1aafSjsg };
606ad8b1aafSjsg
607c349dbc7Sjsg #define GEN11_DEFAULT_PAGE_SIZES \
6081bb76ff1Sjsg .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
609c349dbc7Sjsg I915_GTT_PAGE_SIZE_64K | \
610c349dbc7Sjsg I915_GTT_PAGE_SIZE_2M
611c349dbc7Sjsg
6127f4dd379Sjsg #define GEN11_FEATURES \
6135ca02815Sjsg GEN9_FEATURES, \
614c349dbc7Sjsg GEN11_DEFAULT_PAGE_SIZES, \
6157f4dd379Sjsg GEN(11), \
6165ca02815Sjsg .has_coherent_ggtt = false, \
6175ca02815Sjsg .has_logical_ring_elsq = 1
6187f4dd379Sjsg
619c349dbc7Sjsg static const struct intel_device_info icl_info = {
6207f4dd379Sjsg GEN11_FEATURES,
6217f4dd379Sjsg PLATFORM(INTEL_ICELAKE),
622f005ef32Sjsg .platform_engine_mask =
623c349dbc7Sjsg BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
6247f4dd379Sjsg };
6257f4dd379Sjsg
626c349dbc7Sjsg static const struct intel_device_info ehl_info = {
627c349dbc7Sjsg GEN11_FEATURES,
628c349dbc7Sjsg PLATFORM(INTEL_ELKHARTLAKE),
629f005ef32Sjsg .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
6301bb76ff1Sjsg .__runtime.ppgtt_size = 36,
6315ca02815Sjsg };
6325ca02815Sjsg
6335ca02815Sjsg static const struct intel_device_info jsl_info = {
6345ca02815Sjsg GEN11_FEATURES,
6355ca02815Sjsg PLATFORM(INTEL_JASPERLAKE),
636f005ef32Sjsg .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
6371bb76ff1Sjsg .__runtime.ppgtt_size = 36,
638c349dbc7Sjsg };
639c349dbc7Sjsg
640c349dbc7Sjsg #define GEN12_FEATURES \
641c349dbc7Sjsg GEN11_FEATURES, \
642c349dbc7Sjsg GEN(12), \
643f005ef32Sjsg TGL_CACHELEVEL, \
644c349dbc7Sjsg .has_global_mocs = 1, \
6451bb76ff1Sjsg .has_pxp = 1, \
646f005ef32Sjsg .max_pat_index = 3
647c349dbc7Sjsg
648c349dbc7Sjsg static const struct intel_device_info tgl_info = {
649c349dbc7Sjsg GEN12_FEATURES,
650c349dbc7Sjsg PLATFORM(INTEL_TIGERLAKE),
651f005ef32Sjsg .platform_engine_mask =
652c349dbc7Sjsg BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
653c349dbc7Sjsg };
654c349dbc7Sjsg
655ad8b1aafSjsg static const struct intel_device_info rkl_info = {
656ad8b1aafSjsg GEN12_FEATURES,
657ad8b1aafSjsg PLATFORM(INTEL_ROCKETLAKE),
658f005ef32Sjsg .platform_engine_mask =
659ad8b1aafSjsg BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
660ad8b1aafSjsg };
661ad8b1aafSjsg
6625ca02815Sjsg #define DGFX_FEATURES \
663f005ef32Sjsg .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
6645ca02815Sjsg .has_llc = 0, \
6651bb76ff1Sjsg .has_pxp = 0, \
6665ca02815Sjsg .has_snoop = 1, \
6671bb76ff1Sjsg .is_dgfx = 1, \
6681bb76ff1Sjsg .has_heci_gscfi = 1
669c349dbc7Sjsg
6701bb76ff1Sjsg static const struct intel_device_info dg1_info = {
6715ca02815Sjsg GEN12_FEATURES,
6725ca02815Sjsg DGFX_FEATURES,
6731bb76ff1Sjsg .__runtime.graphics.ip.rel = 10,
674ad8b1aafSjsg PLATFORM(INTEL_DG1),
675ad8b1aafSjsg .require_force_probe = 1,
676f005ef32Sjsg .platform_engine_mask =
677ad8b1aafSjsg BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
678ad8b1aafSjsg BIT(VCS0) | BIT(VCS2),
6795ca02815Sjsg /* Wa_16011227922 */
6801bb76ff1Sjsg .__runtime.ppgtt_size = 47,
6815ca02815Sjsg };
6825ca02815Sjsg
6835ca02815Sjsg static const struct intel_device_info adl_s_info = {
6845ca02815Sjsg GEN12_FEATURES,
6855ca02815Sjsg PLATFORM(INTEL_ALDERLAKE_S),
686f005ef32Sjsg .platform_engine_mask =
6875ca02815Sjsg BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
6885ca02815Sjsg .dma_mask_size = 39,
6895ca02815Sjsg };
6905ca02815Sjsg
6915ca02815Sjsg static const struct intel_device_info adl_p_info = {
6925ca02815Sjsg GEN12_FEATURES,
6935ca02815Sjsg PLATFORM(INTEL_ALDERLAKE_P),
694f005ef32Sjsg .platform_engine_mask =
6955ca02815Sjsg BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
6961bb76ff1Sjsg .__runtime.ppgtt_size = 48,
6975ca02815Sjsg .dma_mask_size = 39,
698ad8b1aafSjsg };
699ad8b1aafSjsg
7007f4dd379Sjsg #undef GEN
7015ca02815Sjsg
7025ca02815Sjsg #define XE_HP_PAGE_SIZES \
7031bb76ff1Sjsg .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
7045ca02815Sjsg I915_GTT_PAGE_SIZE_64K | \
7055ca02815Sjsg I915_GTT_PAGE_SIZE_2M
7065ca02815Sjsg
7075ca02815Sjsg #define XE_HP_FEATURES \
7081bb76ff1Sjsg .__runtime.graphics.ip.ver = 12, \
7091bb76ff1Sjsg .__runtime.graphics.ip.rel = 50, \
7105ca02815Sjsg XE_HP_PAGE_SIZES, \
711f005ef32Sjsg TGL_CACHELEVEL, \
7125ca02815Sjsg .dma_mask_size = 46, \
7131bb76ff1Sjsg .has_3d_pipeline = 1, \
7145ca02815Sjsg .has_64bit_reloc = 1, \
7151bb76ff1Sjsg .has_flat_ccs = 1, \
716f005ef32Sjsg .has_4tile = 1, \
7175ca02815Sjsg .has_global_mocs = 1, \
7185ca02815Sjsg .has_gt_uc = 1, \
7195ca02815Sjsg .has_llc = 1, \
7205ca02815Sjsg .has_logical_ring_contexts = 1, \
7215ca02815Sjsg .has_logical_ring_elsq = 1, \
7221bb76ff1Sjsg .has_mslice_steering = 1, \
723f005ef32Sjsg .has_oa_bpc_reporting = 1, \
724f005ef32Sjsg .has_oa_slice_contrib_limits = 1, \
725f005ef32Sjsg .has_oam = 1, \
7265ca02815Sjsg .has_rc6 = 1, \
7275ca02815Sjsg .has_reset_engine = 1, \
7285ca02815Sjsg .has_rps = 1, \
7295ca02815Sjsg .has_runtime_pm = 1, \
730f005ef32Sjsg .max_pat_index = 3, \
7311bb76ff1Sjsg .__runtime.ppgtt_size = 48, \
7321bb76ff1Sjsg .__runtime.ppgtt_type = INTEL_PPGTT_FULL
7335ca02815Sjsg
7345ca02815Sjsg #define XE_HPM_FEATURES \
7351bb76ff1Sjsg .__runtime.media.ip.ver = 12, \
7361bb76ff1Sjsg .__runtime.media.ip.rel = 50
7375ca02815Sjsg
7385ca02815Sjsg __maybe_unused
7395ca02815Sjsg static const struct intel_device_info xehpsdv_info = {
7405ca02815Sjsg XE_HP_FEATURES,
7415ca02815Sjsg XE_HPM_FEATURES,
7425ca02815Sjsg DGFX_FEATURES,
7435ca02815Sjsg PLATFORM(INTEL_XEHPSDV),
7441bb76ff1Sjsg .has_64k_pages = 1,
7451bb76ff1Sjsg .has_media_ratio_mode = 1,
746f005ef32Sjsg .platform_engine_mask =
7475ca02815Sjsg BIT(RCS0) | BIT(BCS0) |
7485ca02815Sjsg BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
7495ca02815Sjsg BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
7501bb76ff1Sjsg BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
7511bb76ff1Sjsg BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
7525ca02815Sjsg .require_force_probe = 1,
7535ca02815Sjsg };
7545ca02815Sjsg
7551bb76ff1Sjsg #define DG2_FEATURES \
7561bb76ff1Sjsg XE_HP_FEATURES, \
7571bb76ff1Sjsg XE_HPM_FEATURES, \
7581bb76ff1Sjsg DGFX_FEATURES, \
7591bb76ff1Sjsg .__runtime.graphics.ip.rel = 55, \
7601bb76ff1Sjsg .__runtime.media.ip.rel = 55, \
7611bb76ff1Sjsg PLATFORM(INTEL_DG2), \
7621bb76ff1Sjsg .has_64k_pages = 1, \
7631bb76ff1Sjsg .has_guc_deprivilege = 1, \
7641bb76ff1Sjsg .has_heci_pxp = 1, \
7651bb76ff1Sjsg .has_media_ratio_mode = 1, \
766f005ef32Sjsg .platform_engine_mask = \
7671bb76ff1Sjsg BIT(RCS0) | BIT(BCS0) | \
7681bb76ff1Sjsg BIT(VECS0) | BIT(VECS1) | \
7691bb76ff1Sjsg BIT(VCS0) | BIT(VCS2) | \
7701bb76ff1Sjsg BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
7711bb76ff1Sjsg
7725ca02815Sjsg static const struct intel_device_info dg2_info = {
7731bb76ff1Sjsg DG2_FEATURES,
774*ff0714f9Sjsg .require_force_probe = 1,
7751bb76ff1Sjsg };
7761bb76ff1Sjsg
7771bb76ff1Sjsg static const struct intel_device_info ats_m_info = {
7781bb76ff1Sjsg DG2_FEATURES,
7791bb76ff1Sjsg .require_force_probe = 1,
7801bb76ff1Sjsg .tuning_thread_rr_after_dep = 1,
7811bb76ff1Sjsg };
7821bb76ff1Sjsg
7831bb76ff1Sjsg #define XE_HPC_FEATURES \
7841bb76ff1Sjsg XE_HP_FEATURES, \
7851bb76ff1Sjsg .dma_mask_size = 52, \
7861bb76ff1Sjsg .has_3d_pipeline = 0, \
7871bb76ff1Sjsg .has_guc_deprivilege = 1, \
7881bb76ff1Sjsg .has_l3_ccs_read = 1, \
7891bb76ff1Sjsg .has_mslice_steering = 0, \
7901bb76ff1Sjsg .has_one_eu_per_fuse_bit = 1
7911bb76ff1Sjsg
7921bb76ff1Sjsg __maybe_unused
7931bb76ff1Sjsg static const struct intel_device_info pvc_info = {
7941bb76ff1Sjsg XE_HPC_FEATURES,
7951bb76ff1Sjsg XE_HPM_FEATURES,
7965ca02815Sjsg DGFX_FEATURES,
7971bb76ff1Sjsg .__runtime.graphics.ip.rel = 60,
7981bb76ff1Sjsg .__runtime.media.ip.rel = 60,
7991bb76ff1Sjsg PLATFORM(INTEL_PONTEVECCHIO),
8001bb76ff1Sjsg .has_flat_ccs = 0,
801f005ef32Sjsg .max_pat_index = 7,
802f005ef32Sjsg .platform_engine_mask =
8031bb76ff1Sjsg BIT(BCS0) |
8041bb76ff1Sjsg BIT(VCS0) |
8051bb76ff1Sjsg BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
8061bb76ff1Sjsg .require_force_probe = 1,
807f005ef32Sjsg PVC_CACHELEVEL,
8081bb76ff1Sjsg };
8091bb76ff1Sjsg
8101bb76ff1Sjsg static const struct intel_gt_definition xelpmp_extra_gt[] = {
8111bb76ff1Sjsg {
8121bb76ff1Sjsg .type = GT_MEDIA,
8131bb76ff1Sjsg .name = "Standalone Media GT",
8141bb76ff1Sjsg .gsi_offset = MTL_MEDIA_GSI_BASE,
815f005ef32Sjsg .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(GSC0),
8161bb76ff1Sjsg },
8171bb76ff1Sjsg {}
8181bb76ff1Sjsg };
8191bb76ff1Sjsg
8201bb76ff1Sjsg static const struct intel_device_info mtl_info = {
8211bb76ff1Sjsg XE_HP_FEATURES,
8221bb76ff1Sjsg /*
8231bb76ff1Sjsg * Real graphics IP version will be obtained from hardware GMD_ID
8241bb76ff1Sjsg * register. Value provided here is just for sanity checking.
8251bb76ff1Sjsg */
8261bb76ff1Sjsg .__runtime.graphics.ip.ver = 12,
8271bb76ff1Sjsg .__runtime.graphics.ip.rel = 70,
8281bb76ff1Sjsg .__runtime.media.ip.ver = 13,
8291bb76ff1Sjsg PLATFORM(INTEL_METEORLAKE),
8301bb76ff1Sjsg .extra_gt_list = xelpmp_extra_gt,
8311bb76ff1Sjsg .has_flat_ccs = 0,
832f005ef32Sjsg .has_gmd_id = 1,
833f005ef32Sjsg .has_guc_deprivilege = 1,
834f005ef32Sjsg .has_llc = 0,
835f005ef32Sjsg .has_mslice_steering = 0,
8361bb76ff1Sjsg .has_snoop = 1,
837f005ef32Sjsg .max_pat_index = 4,
838f005ef32Sjsg .has_pxp = 1,
839f005ef32Sjsg .memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
840f005ef32Sjsg .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
8415ca02815Sjsg .require_force_probe = 1,
842f005ef32Sjsg MTL_CACHELEVEL,
8435ca02815Sjsg };
8445ca02815Sjsg
8457f4dd379Sjsg #undef PLATFORM
8467f4dd379Sjsg
8477f4dd379Sjsg /*
8487f4dd379Sjsg * Make sure any device matches here are from most specific to most
8497f4dd379Sjsg * general. For example, since the Quanta match is based on the subsystem
8507f4dd379Sjsg * and subvendor IDs, we need it to come before the more general IVB
8517f4dd379Sjsg * PCI ID matches, otherwise we'll use the wrong info struct above.
8527f4dd379Sjsg */
853c349dbc7Sjsg const struct pci_device_id pciidlist[] = {
854c349dbc7Sjsg INTEL_I830_IDS(&i830_info),
855c349dbc7Sjsg INTEL_I845G_IDS(&i845g_info),
856c349dbc7Sjsg INTEL_I85X_IDS(&i85x_info),
857c349dbc7Sjsg INTEL_I865G_IDS(&i865g_info),
858c349dbc7Sjsg INTEL_I915G_IDS(&i915g_info),
859c349dbc7Sjsg INTEL_I915GM_IDS(&i915gm_info),
860c349dbc7Sjsg INTEL_I945G_IDS(&i945g_info),
861c349dbc7Sjsg INTEL_I945GM_IDS(&i945gm_info),
862c349dbc7Sjsg INTEL_I965G_IDS(&i965g_info),
863c349dbc7Sjsg INTEL_G33_IDS(&g33_info),
864c349dbc7Sjsg INTEL_I965GM_IDS(&i965gm_info),
865c349dbc7Sjsg INTEL_GM45_IDS(&gm45_info),
866c349dbc7Sjsg INTEL_G45_IDS(&g45_info),
867c349dbc7Sjsg INTEL_PINEVIEW_G_IDS(&pnv_g_info),
868c349dbc7Sjsg INTEL_PINEVIEW_M_IDS(&pnv_m_info),
869c349dbc7Sjsg INTEL_IRONLAKE_D_IDS(&ilk_d_info),
870c349dbc7Sjsg INTEL_IRONLAKE_M_IDS(&ilk_m_info),
871c349dbc7Sjsg INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
872c349dbc7Sjsg INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
873c349dbc7Sjsg INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
874c349dbc7Sjsg INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
875c349dbc7Sjsg INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
876c349dbc7Sjsg INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
877c349dbc7Sjsg INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
878c349dbc7Sjsg INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
879c349dbc7Sjsg INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
880c349dbc7Sjsg INTEL_HSW_GT1_IDS(&hsw_gt1_info),
881c349dbc7Sjsg INTEL_HSW_GT2_IDS(&hsw_gt2_info),
882c349dbc7Sjsg INTEL_HSW_GT3_IDS(&hsw_gt3_info),
883c349dbc7Sjsg INTEL_VLV_IDS(&vlv_info),
884c349dbc7Sjsg INTEL_BDW_GT1_IDS(&bdw_gt1_info),
885c349dbc7Sjsg INTEL_BDW_GT2_IDS(&bdw_gt2_info),
886c349dbc7Sjsg INTEL_BDW_GT3_IDS(&bdw_gt3_info),
887c349dbc7Sjsg INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
888c349dbc7Sjsg INTEL_CHV_IDS(&chv_info),
889c349dbc7Sjsg INTEL_SKL_GT1_IDS(&skl_gt1_info),
890c349dbc7Sjsg INTEL_SKL_GT2_IDS(&skl_gt2_info),
891c349dbc7Sjsg INTEL_SKL_GT3_IDS(&skl_gt3_info),
892c349dbc7Sjsg INTEL_SKL_GT4_IDS(&skl_gt4_info),
893c349dbc7Sjsg INTEL_BXT_IDS(&bxt_info),
894c349dbc7Sjsg INTEL_GLK_IDS(&glk_info),
895c349dbc7Sjsg INTEL_KBL_GT1_IDS(&kbl_gt1_info),
896c349dbc7Sjsg INTEL_KBL_GT2_IDS(&kbl_gt2_info),
897c349dbc7Sjsg INTEL_KBL_GT3_IDS(&kbl_gt3_info),
898c349dbc7Sjsg INTEL_KBL_GT4_IDS(&kbl_gt3_info),
899c349dbc7Sjsg INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
900c349dbc7Sjsg INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
901c349dbc7Sjsg INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
902c349dbc7Sjsg INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
903c349dbc7Sjsg INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
904c349dbc7Sjsg INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
905c349dbc7Sjsg INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
906c349dbc7Sjsg INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
907c349dbc7Sjsg INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
908c349dbc7Sjsg INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
909c349dbc7Sjsg INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
910ad8b1aafSjsg INTEL_CML_GT1_IDS(&cml_gt1_info),
911ad8b1aafSjsg INTEL_CML_GT2_IDS(&cml_gt2_info),
912ad8b1aafSjsg INTEL_CML_U_GT1_IDS(&cml_gt1_info),
913ad8b1aafSjsg INTEL_CML_U_GT2_IDS(&cml_gt2_info),
914c349dbc7Sjsg INTEL_ICL_11_IDS(&icl_info),
915c349dbc7Sjsg INTEL_EHL_IDS(&ehl_info),
9165ca02815Sjsg INTEL_JSL_IDS(&jsl_info),
917c349dbc7Sjsg INTEL_TGL_12_IDS(&tgl_info),
918ad8b1aafSjsg INTEL_RKL_IDS(&rkl_info),
9195ca02815Sjsg INTEL_ADLS_IDS(&adl_s_info),
9205ca02815Sjsg INTEL_ADLP_IDS(&adl_p_info),
921c091463fSjsg INTEL_ADLN_IDS(&adl_p_info),
9221bb76ff1Sjsg INTEL_DG1_IDS(&dg1_info),
9231dae0cf4Sjsg INTEL_RPLS_IDS(&adl_s_info),
92408d1a717Sjsg INTEL_RPLP_IDS(&adl_p_info),
9251bb76ff1Sjsg INTEL_DG2_IDS(&dg2_info),
9261bb76ff1Sjsg INTEL_ATS_M_IDS(&ats_m_info),
9271bb76ff1Sjsg INTEL_MTL_IDS(&mtl_info),
9287f4dd379Sjsg {0, 0, 0}
9297f4dd379Sjsg };
9307f4dd379Sjsg MODULE_DEVICE_TABLE(pci, pciidlist);
9317f4dd379Sjsg
9327f4dd379Sjsg #ifdef __linux__
i915_pci_remove(struct pci_dev * pdev)9337f4dd379Sjsg static void i915_pci_remove(struct pci_dev *pdev)
9347f4dd379Sjsg {
935c349dbc7Sjsg struct drm_i915_private *i915;
9367f4dd379Sjsg
937c349dbc7Sjsg i915 = pci_get_drvdata(pdev);
938c349dbc7Sjsg if (!i915) /* driver load aborted, nothing to cleanup */
9397f4dd379Sjsg return;
9407f4dd379Sjsg
941c349dbc7Sjsg i915_driver_remove(i915);
9427f4dd379Sjsg pci_set_drvdata(pdev, NULL);
943c349dbc7Sjsg }
944c349dbc7Sjsg
945c349dbc7Sjsg /* is device_id present in comma separated list of ids */
device_id_in_list(u16 device_id,const char * devices,bool negative)946db1b00f2Sjsg static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
947c349dbc7Sjsg {
948c349dbc7Sjsg char *s, *p, *tok;
949c349dbc7Sjsg bool ret;
950c349dbc7Sjsg
951c349dbc7Sjsg if (!devices || !*devices)
952c349dbc7Sjsg return false;
953c349dbc7Sjsg
954c349dbc7Sjsg /* match everything */
955db1b00f2Sjsg if (negative && strcmp(devices, "!*") == 0)
956db1b00f2Sjsg return true;
957db1b00f2Sjsg if (!negative && strcmp(devices, "*") == 0)
958c349dbc7Sjsg return true;
959c349dbc7Sjsg
960c349dbc7Sjsg s = kstrdup(devices, GFP_KERNEL);
961c349dbc7Sjsg if (!s)
962c349dbc7Sjsg return false;
963c349dbc7Sjsg
964c349dbc7Sjsg for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
965c349dbc7Sjsg u16 val;
966c349dbc7Sjsg
967db1b00f2Sjsg if (negative && tok[0] == '!')
968db1b00f2Sjsg tok++;
969db1b00f2Sjsg else if ((negative && tok[0] != '!') ||
970db1b00f2Sjsg (!negative && tok[0] == '!'))
971db1b00f2Sjsg continue;
972db1b00f2Sjsg
973c349dbc7Sjsg if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
974c349dbc7Sjsg ret = true;
975c349dbc7Sjsg break;
976c349dbc7Sjsg }
977c349dbc7Sjsg }
978c349dbc7Sjsg
979c349dbc7Sjsg kfree(s);
980c349dbc7Sjsg
981c349dbc7Sjsg return ret;
9827f4dd379Sjsg }
9837f4dd379Sjsg
id_forced(u16 device_id)984db1b00f2Sjsg static bool id_forced(u16 device_id)
985db1b00f2Sjsg {
986db1b00f2Sjsg return device_id_in_list(device_id, i915_modparams.force_probe, false);
987db1b00f2Sjsg }
988db1b00f2Sjsg
id_blocked(u16 device_id)989db1b00f2Sjsg static bool id_blocked(u16 device_id)
990db1b00f2Sjsg {
991db1b00f2Sjsg return device_id_in_list(device_id, i915_modparams.force_probe, true);
992db1b00f2Sjsg }
993db1b00f2Sjsg
i915_pci_resource_valid(struct pci_dev * pdev,int bar)9941bb76ff1Sjsg bool i915_pci_resource_valid(struct pci_dev *pdev, int bar)
9951bb76ff1Sjsg {
9961bb76ff1Sjsg if (!pci_resource_flags(pdev, bar))
9971bb76ff1Sjsg return false;
9981bb76ff1Sjsg
9991bb76ff1Sjsg if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET)
10001bb76ff1Sjsg return false;
10011bb76ff1Sjsg
10021bb76ff1Sjsg if (!pci_resource_len(pdev, bar))
10031bb76ff1Sjsg return false;
10041bb76ff1Sjsg
10051bb76ff1Sjsg return true;
10061bb76ff1Sjsg }
10071bb76ff1Sjsg
intel_mmio_bar_valid(struct pci_dev * pdev,struct intel_device_info * intel_info)10081bb76ff1Sjsg static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info)
10091bb76ff1Sjsg {
1010f005ef32Sjsg return i915_pci_resource_valid(pdev, intel_mmio_bar(intel_info->__runtime.graphics.ip.ver));
10111bb76ff1Sjsg }
10121bb76ff1Sjsg
i915_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)10137f4dd379Sjsg static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10147f4dd379Sjsg {
10157f4dd379Sjsg struct intel_device_info *intel_info =
10167f4dd379Sjsg (struct intel_device_info *) ent->driver_data;
10177f4dd379Sjsg int err;
10187f4dd379Sjsg
1019db1b00f2Sjsg if (intel_info->require_force_probe && !id_forced(pdev->device)) {
1020c349dbc7Sjsg dev_info(&pdev->dev,
1021db1b00f2Sjsg "Your graphics device %04x is not properly supported by i915 in this\n"
1022c349dbc7Sjsg "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1023c349dbc7Sjsg "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1024c349dbc7Sjsg "or (recommended) check for kernel updates.\n",
1025c349dbc7Sjsg pdev->device, pdev->device, pdev->device);
10267f4dd379Sjsg return -ENODEV;
10277f4dd379Sjsg }
10287f4dd379Sjsg
1029db1b00f2Sjsg if (id_blocked(pdev->device)) {
1030db1b00f2Sjsg dev_info(&pdev->dev, "I915 probe blocked for Device ID %04x.\n",
1031db1b00f2Sjsg pdev->device);
1032db1b00f2Sjsg return -ENODEV;
1033db1b00f2Sjsg }
1034db1b00f2Sjsg
1035d218186bSjsg if (intel_info->require_force_probe) {
1036d218186bSjsg dev_info(&pdev->dev, "Force probing unsupported Device ID %04x, tainting kernel\n",
1037d218186bSjsg pdev->device);
1038d218186bSjsg add_taint(TAINT_USER, LOCKDEP_STILL_OK);
1039d218186bSjsg }
1040d218186bSjsg
10417f4dd379Sjsg /* Only bind to function 0 of the device. Early generations
10427f4dd379Sjsg * used function 1 as a placeholder for multi-head. This causes
10437f4dd379Sjsg * us confusion instead, especially on the systems where both
10447f4dd379Sjsg * functions have the same PCI-ID!
10457f4dd379Sjsg */
10467f4dd379Sjsg if (PCI_FUNC(pdev->devfn))
10477f4dd379Sjsg return -ENODEV;
10487f4dd379Sjsg
10491bb76ff1Sjsg if (!intel_mmio_bar_valid(pdev, intel_info))
10501bb76ff1Sjsg return -ENXIO;
10511bb76ff1Sjsg
10521bb76ff1Sjsg /* Detect if we need to wait for other drivers early on */
1053f005ef32Sjsg if (intel_display_driver_probe_defer(pdev))
10547f4dd379Sjsg return -EPROBE_DEFER;
10557f4dd379Sjsg
1056c349dbc7Sjsg err = i915_driver_probe(pdev, ent);
10577f4dd379Sjsg if (err)
10587f4dd379Sjsg return err;
10597f4dd379Sjsg
1060c349dbc7Sjsg if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
10617f4dd379Sjsg i915_pci_remove(pdev);
10627f4dd379Sjsg return -ENODEV;
10637f4dd379Sjsg }
10647f4dd379Sjsg
10657f4dd379Sjsg err = i915_live_selftests(pdev);
10667f4dd379Sjsg if (err) {
10677f4dd379Sjsg i915_pci_remove(pdev);
10687f4dd379Sjsg return err > 0 ? -ENOTTY : err;
10697f4dd379Sjsg }
10707f4dd379Sjsg
1071c349dbc7Sjsg err = i915_perf_selftests(pdev);
1072c349dbc7Sjsg if (err) {
1073c349dbc7Sjsg i915_pci_remove(pdev);
1074c349dbc7Sjsg return err > 0 ? -ENOTTY : err;
1075c349dbc7Sjsg }
1076c349dbc7Sjsg
10777f4dd379Sjsg return 0;
10787f4dd379Sjsg }
10797f4dd379Sjsg
i915_pci_shutdown(struct pci_dev * pdev)10805ca02815Sjsg static void i915_pci_shutdown(struct pci_dev *pdev)
10815ca02815Sjsg {
10825ca02815Sjsg struct drm_i915_private *i915 = pci_get_drvdata(pdev);
10835ca02815Sjsg
10845ca02815Sjsg i915_driver_shutdown(i915);
10855ca02815Sjsg }
10865ca02815Sjsg
10877f4dd379Sjsg static struct pci_driver i915_pci_driver = {
10887f4dd379Sjsg .name = DRIVER_NAME,
10897f4dd379Sjsg .id_table = pciidlist,
10907f4dd379Sjsg .probe = i915_pci_probe,
10917f4dd379Sjsg .remove = i915_pci_remove,
10925ca02815Sjsg .shutdown = i915_pci_shutdown,
10937f4dd379Sjsg .driver.pm = &i915_pm_ops,
10947f4dd379Sjsg };
10957f4dd379Sjsg
i915_pci_register_driver(void)10961bb76ff1Sjsg int i915_pci_register_driver(void)
10977f4dd379Sjsg {
10985ca02815Sjsg return pci_register_driver(&i915_pci_driver);
10997f4dd379Sjsg }
11007f4dd379Sjsg
i915_pci_unregister_driver(void)11011bb76ff1Sjsg void i915_pci_unregister_driver(void)
11027f4dd379Sjsg {
11037f4dd379Sjsg pci_unregister_driver(&i915_pci_driver);
11045ca02815Sjsg }
11055ca02815Sjsg
11065ca02815Sjsg #else
11075ca02815Sjsg
i915_pci_register_driver(void)11081bb76ff1Sjsg int i915_pci_register_driver(void)
11095ca02815Sjsg {
11105ca02815Sjsg return 0;
11115ca02815Sjsg }
11125ca02815Sjsg
i915_pci_unregister_driver(void)11131bb76ff1Sjsg void i915_pci_unregister_driver(void)
11145ca02815Sjsg {
11157f4dd379Sjsg }
11167f4dd379Sjsg #endif
1117