17f4dd379Sjsg /* 27f4dd379Sjsg * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 37f4dd379Sjsg * 47f4dd379Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 57f4dd379Sjsg * copy of this software and associated documentation files (the "Software"), 67f4dd379Sjsg * to deal in the Software without restriction, including without limitation 77f4dd379Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87f4dd379Sjsg * and/or sell copies of the Software, and to permit persons to whom the 97f4dd379Sjsg * Software is furnished to do so, subject to the following conditions: 107f4dd379Sjsg * 117f4dd379Sjsg * The above copyright notice and this permission notice (including the next 127f4dd379Sjsg * paragraph) shall be included in all copies or substantial portions of the 137f4dd379Sjsg * Software. 147f4dd379Sjsg * 157f4dd379Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 167f4dd379Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 177f4dd379Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 187f4dd379Sjsg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 197f4dd379Sjsg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 207f4dd379Sjsg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 217f4dd379Sjsg * SOFTWARE. 227f4dd379Sjsg */ 237f4dd379Sjsg 247f4dd379Sjsg #ifndef _I915_PVINFO_H_ 257f4dd379Sjsg #define _I915_PVINFO_H_ 267f4dd379Sjsg 27*c349dbc7Sjsg #include <linux/types.h> 28*c349dbc7Sjsg 297f4dd379Sjsg /* The MMIO offset of the shared info between guest and host emulator */ 307f4dd379Sjsg #define VGT_PVINFO_PAGE 0x78000 317f4dd379Sjsg #define VGT_PVINFO_SIZE 0x1000 327f4dd379Sjsg 337f4dd379Sjsg /* 347f4dd379Sjsg * The following structure pages are defined in GEN MMIO space 357f4dd379Sjsg * for virtualization. (One page for now) 367f4dd379Sjsg */ 377f4dd379Sjsg #define VGT_MAGIC 0x4776544776544776ULL /* 'vGTvGTvG' */ 387f4dd379Sjsg #define VGT_VERSION_MAJOR 1 397f4dd379Sjsg #define VGT_VERSION_MINOR 0 407f4dd379Sjsg 417f4dd379Sjsg /* 427f4dd379Sjsg * notifications from guest to vgpu device model 437f4dd379Sjsg */ 447f4dd379Sjsg enum vgt_g2v_type { 457f4dd379Sjsg VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2, 467f4dd379Sjsg VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY, 477f4dd379Sjsg VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE, 487f4dd379Sjsg VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY, 497f4dd379Sjsg VGT_G2V_EXECLIST_CONTEXT_CREATE, 507f4dd379Sjsg VGT_G2V_EXECLIST_CONTEXT_DESTROY, 517f4dd379Sjsg VGT_G2V_MAX, 527f4dd379Sjsg }; 537f4dd379Sjsg 547f4dd379Sjsg /* 557f4dd379Sjsg * VGT capabilities type 567f4dd379Sjsg */ 57*c349dbc7Sjsg #define VGT_CAPS_FULL_PPGTT BIT(2) 587f4dd379Sjsg #define VGT_CAPS_HWSP_EMULATION BIT(3) 597f4dd379Sjsg #define VGT_CAPS_HUGE_GTT BIT(4) 607f4dd379Sjsg 617f4dd379Sjsg struct vgt_if { 627f4dd379Sjsg u64 magic; /* VGT_MAGIC */ 637f4dd379Sjsg u16 version_major; 647f4dd379Sjsg u16 version_minor; 657f4dd379Sjsg u32 vgt_id; /* ID of vGT instance */ 667f4dd379Sjsg u32 vgt_caps; /* VGT capabilities */ 677f4dd379Sjsg u32 rsv1[11]; /* pad to offset 0x40 */ 687f4dd379Sjsg /* 697f4dd379Sjsg * Data structure to describe the balooning info of resources. 707f4dd379Sjsg * Each VM can only have one portion of continuous area for now. 717f4dd379Sjsg * (May support scattered resource in future) 727f4dd379Sjsg * (starting from offset 0x40) 737f4dd379Sjsg */ 747f4dd379Sjsg struct { 757f4dd379Sjsg /* Aperture register balooning */ 767f4dd379Sjsg struct { 777f4dd379Sjsg u32 base; 787f4dd379Sjsg u32 size; 797f4dd379Sjsg } mappable_gmadr; /* aperture */ 807f4dd379Sjsg /* GMADR register balooning */ 817f4dd379Sjsg struct { 827f4dd379Sjsg u32 base; 837f4dd379Sjsg u32 size; 847f4dd379Sjsg } nonmappable_gmadr; /* non aperture */ 857f4dd379Sjsg /* allowed fence registers */ 867f4dd379Sjsg u32 fence_num; 877f4dd379Sjsg u32 rsv2[3]; 887f4dd379Sjsg } avail_rs; /* available/assigned resource */ 897f4dd379Sjsg u32 rsv3[0x200 - 24]; /* pad to half page */ 907f4dd379Sjsg /* 917f4dd379Sjsg * The bottom half page is for response from Gfx driver to hypervisor. 927f4dd379Sjsg */ 937f4dd379Sjsg u32 rsv4; 947f4dd379Sjsg u32 display_ready; /* ready for display owner switch */ 957f4dd379Sjsg 967f4dd379Sjsg u32 rsv5[4]; 977f4dd379Sjsg 987f4dd379Sjsg u32 g2v_notify; 997f4dd379Sjsg u32 rsv6[5]; 1007f4dd379Sjsg 1017f4dd379Sjsg u32 cursor_x_hot; 1027f4dd379Sjsg u32 cursor_y_hot; 1037f4dd379Sjsg 1047f4dd379Sjsg struct { 1057f4dd379Sjsg u32 lo; 1067f4dd379Sjsg u32 hi; 1077f4dd379Sjsg } pdp[4]; 1087f4dd379Sjsg 1097f4dd379Sjsg u32 execlist_context_descriptor_lo; 1107f4dd379Sjsg u32 execlist_context_descriptor_hi; 1117f4dd379Sjsg 1127f4dd379Sjsg u32 rsv7[0x200 - 24]; /* pad to one page */ 1137f4dd379Sjsg } __packed; 1147f4dd379Sjsg 115*c349dbc7Sjsg #define vgtif_offset(x) (offsetof(struct vgt_if, x)) 116*c349dbc7Sjsg 117*c349dbc7Sjsg #define vgtif_reg(x) _MMIO(VGT_PVINFO_PAGE + vgtif_offset(x)) 1187f4dd379Sjsg 1197f4dd379Sjsg /* vGPU display status to be used by the host side */ 1207f4dd379Sjsg #define VGT_DRV_DISPLAY_NOT_READY 0 1217f4dd379Sjsg #define VGT_DRV_DISPLAY_READY 1 /* ready for display switch */ 1227f4dd379Sjsg 1237f4dd379Sjsg #endif /* _I915_PVINFO_H_ */ 124