11bb76ff1Sjsg /* SPDX-License-Identifier: MIT */ 21bb76ff1Sjsg /* 31bb76ff1Sjsg * Copyright © 2022 Intel Corporation 41bb76ff1Sjsg */ 51bb76ff1Sjsg 61bb76ff1Sjsg #ifndef __INTEL_PCI_CONFIG_H__ 71bb76ff1Sjsg #define __INTEL_PCI_CONFIG_H__ 81bb76ff1Sjsg 91bb76ff1Sjsg /* PCI BARs */ 10*f005ef32Sjsg #define GEN2_GMADR_BAR 0 11*f005ef32Sjsg #define GEN2_MMADR_BAR 1 /* MMIO+GTT, despite the name */ 12*f005ef32Sjsg #define GEN2_IO_BAR 2 /* 85x/865 */ 13*f005ef32Sjsg 14*f005ef32Sjsg #define GEN3_MMADR_BAR 0 /* MMIO only */ 15*f005ef32Sjsg #define GEN3_IO_BAR 1 16*f005ef32Sjsg #define GEN3_GMADR_BAR 2 17*f005ef32Sjsg #define GEN3_GTTADR_BAR 3 /* GTT only */ 18*f005ef32Sjsg 19*f005ef32Sjsg #define GEN4_GTTMMADR_BAR 0 /* MMIO+GTT */ 20*f005ef32Sjsg #define GEN4_GMADR_BAR 2 21*f005ef32Sjsg #define GEN4_IO_BAR 4 22*f005ef32Sjsg 23*f005ef32Sjsg #define GEN12_LMEM_BAR 2 24*f005ef32Sjsg intel_mmio_bar(int graphics_ver)25*f005ef32Sjsgstatic inline int intel_mmio_bar(int graphics_ver) 26*f005ef32Sjsg { 27*f005ef32Sjsg switch (graphics_ver) { 28*f005ef32Sjsg case 2: return GEN2_MMADR_BAR; 29*f005ef32Sjsg case 3: return GEN3_MMADR_BAR; 30*f005ef32Sjsg default: return GEN4_GTTMMADR_BAR; 31*f005ef32Sjsg } 32*f005ef32Sjsg } 331bb76ff1Sjsg 341bb76ff1Sjsg /* BSM in include/drm/i915_drm.h */ 351bb76ff1Sjsg 361bb76ff1Sjsg #define MCHBAR_I915 0x44 371bb76ff1Sjsg #define MCHBAR_I965 0x48 381bb76ff1Sjsg #define MCHBAR_SIZE (4 * 4096) 391bb76ff1Sjsg 401bb76ff1Sjsg #define DEVEN 0x54 411bb76ff1Sjsg #define DEVEN_MCHBAR_EN (1 << 28) 421bb76ff1Sjsg 431bb76ff1Sjsg #define HPLLCC 0xc0 /* 85x only */ 441bb76ff1Sjsg #define GC_CLOCK_CONTROL_MASK (0x7 << 0) 451bb76ff1Sjsg #define GC_CLOCK_133_200 (0 << 0) 461bb76ff1Sjsg #define GC_CLOCK_100_200 (1 << 0) 471bb76ff1Sjsg #define GC_CLOCK_100_133 (2 << 0) 481bb76ff1Sjsg #define GC_CLOCK_133_266 (3 << 0) 491bb76ff1Sjsg #define GC_CLOCK_133_200_2 (4 << 0) 501bb76ff1Sjsg #define GC_CLOCK_133_266_2 (5 << 0) 511bb76ff1Sjsg #define GC_CLOCK_166_266 (6 << 0) 521bb76ff1Sjsg #define GC_CLOCK_166_250 (7 << 0) 531bb76ff1Sjsg 541bb76ff1Sjsg #define I915_GDRST 0xc0 551bb76ff1Sjsg #define GRDOM_FULL (0 << 2) 561bb76ff1Sjsg #define GRDOM_RENDER (1 << 2) 571bb76ff1Sjsg #define GRDOM_MEDIA (3 << 2) 581bb76ff1Sjsg #define GRDOM_MASK (3 << 2) 591bb76ff1Sjsg #define GRDOM_RESET_STATUS (1 << 1) 601bb76ff1Sjsg #define GRDOM_RESET_ENABLE (1 << 0) 611bb76ff1Sjsg 621bb76ff1Sjsg /* BSpec only has register offset, PCI device and bit found empirically */ 631bb76ff1Sjsg #define I830_CLOCK_GATE 0xc8 /* device 0 */ 641bb76ff1Sjsg #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2) 651bb76ff1Sjsg 661bb76ff1Sjsg #define GCDGMBUS 0xcc 671bb76ff1Sjsg 681bb76ff1Sjsg #define GCFGC2 0xda 691bb76ff1Sjsg #define GCFGC 0xf0 /* 915+ only */ 701bb76ff1Sjsg #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 711bb76ff1Sjsg #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 721bb76ff1Sjsg #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) 731bb76ff1Sjsg #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 741bb76ff1Sjsg #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 751bb76ff1Sjsg #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 761bb76ff1Sjsg #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 771bb76ff1Sjsg #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 781bb76ff1Sjsg #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 791bb76ff1Sjsg #define GC_DISPLAY_CLOCK_MASK (7 << 4) 801bb76ff1Sjsg #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 811bb76ff1Sjsg #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 821bb76ff1Sjsg #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 831bb76ff1Sjsg #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 841bb76ff1Sjsg #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 851bb76ff1Sjsg #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 861bb76ff1Sjsg #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 871bb76ff1Sjsg #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 881bb76ff1Sjsg #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 891bb76ff1Sjsg #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 901bb76ff1Sjsg #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 911bb76ff1Sjsg #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 921bb76ff1Sjsg #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 931bb76ff1Sjsg #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 941bb76ff1Sjsg #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 951bb76ff1Sjsg #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 961bb76ff1Sjsg #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 971bb76ff1Sjsg #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 981bb76ff1Sjsg #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 991bb76ff1Sjsg 1001bb76ff1Sjsg #define ASLE 0xe4 1011bb76ff1Sjsg #define ASLS 0xfc 1021bb76ff1Sjsg 1031bb76ff1Sjsg #define SWSCI 0xe8 1041bb76ff1Sjsg #define SWSCI_SCISEL (1 << 15) 1051bb76ff1Sjsg #define SWSCI_GSSCIE (1 << 0) 1061bb76ff1Sjsg 1071bb76ff1Sjsg /* legacy/combination backlight modes, also called LBB */ 1081bb76ff1Sjsg #define LBPC 0xf4 1091bb76ff1Sjsg 1101bb76ff1Sjsg #endif /* __INTEL_PCI_CONFIG_H__ */ 111