1*f005ef32Sjsg // SPDX-License-Identifier: MIT
2*f005ef32Sjsg /*
3*f005ef32Sjsg * Copyright © 2023 Intel Corporation
4*f005ef32Sjsg */
5*f005ef32Sjsg
6*f005ef32Sjsg #include <linux/pci.h>
7*f005ef32Sjsg #include <linux/pnp.h>
8*f005ef32Sjsg
9*f005ef32Sjsg #include <drm/drm_managed.h>
10*f005ef32Sjsg #include <drm/i915_drm.h>
11*f005ef32Sjsg
12*f005ef32Sjsg #include "i915_drv.h"
13*f005ef32Sjsg #include "intel_gmch.h"
14*f005ef32Sjsg #include "intel_pci_config.h"
15*f005ef32Sjsg
intel_gmch_bridge_release(struct drm_device * dev,void * bridge)16*f005ef32Sjsg static void intel_gmch_bridge_release(struct drm_device *dev, void *bridge)
17*f005ef32Sjsg {
18*f005ef32Sjsg pci_dev_put(bridge);
19*f005ef32Sjsg }
20*f005ef32Sjsg
21*f005ef32Sjsg #ifdef __linux__
intel_gmch_bridge_setup(struct drm_i915_private * i915)22*f005ef32Sjsg int intel_gmch_bridge_setup(struct drm_i915_private *i915)
23*f005ef32Sjsg {
24*f005ef32Sjsg int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus);
25*f005ef32Sjsg
26*f005ef32Sjsg i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
27*f005ef32Sjsg if (!i915->gmch.pdev) {
28*f005ef32Sjsg drm_err(&i915->drm, "bridge device not found\n");
29*f005ef32Sjsg return -EIO;
30*f005ef32Sjsg }
31*f005ef32Sjsg
32*f005ef32Sjsg return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release,
33*f005ef32Sjsg i915->gmch.pdev);
34*f005ef32Sjsg }
35*f005ef32Sjsg #else
intel_gmch_bridge_setup(struct drm_i915_private * i915)36*f005ef32Sjsg int intel_gmch_bridge_setup(struct drm_i915_private *i915)
37*f005ef32Sjsg {
38*f005ef32Sjsg struct drm_device *dev = &i915->drm;
39*f005ef32Sjsg
40*f005ef32Sjsg /* may be already called from attach */
41*f005ef32Sjsg if (i915->gmch.pdev != NULL)
42*f005ef32Sjsg return 0;
43*f005ef32Sjsg
44*f005ef32Sjsg i915->gmch.pdev = malloc(sizeof(*i915->gmch.pdev),
45*f005ef32Sjsg M_DEVBUF, M_WAITOK);
46*f005ef32Sjsg i915->gmch.pdev->pc = dev->pdev->pc;
47*f005ef32Sjsg i915->gmch.pdev->tag = pci_make_tag(dev->pdev->pc, 0, 0, 0);
48*f005ef32Sjsg
49*f005ef32Sjsg return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release,
50*f005ef32Sjsg i915->gmch.pdev);
51*f005ef32Sjsg }
52*f005ef32Sjsg #endif
53*f005ef32Sjsg
54*f005ef32Sjsg /* Allocate space for the MCH regs if needed, return nonzero on error */
55*f005ef32Sjsg static int
intel_alloc_mchbar_resource(struct drm_i915_private * i915)56*f005ef32Sjsg intel_alloc_mchbar_resource(struct drm_i915_private *i915)
57*f005ef32Sjsg {
58*f005ef32Sjsg int reg = GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
59*f005ef32Sjsg u32 temp_lo, temp_hi = 0;
60*f005ef32Sjsg u64 mchbar_addr;
61*f005ef32Sjsg int ret;
62*f005ef32Sjsg
63*f005ef32Sjsg if (GRAPHICS_VER(i915) >= 4)
64*f005ef32Sjsg pci_read_config_dword(i915->gmch.pdev, reg + 4, &temp_hi);
65*f005ef32Sjsg pci_read_config_dword(i915->gmch.pdev, reg, &temp_lo);
66*f005ef32Sjsg mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
67*f005ef32Sjsg
68*f005ef32Sjsg /* If ACPI doesn't have it, assume we need to allocate it ourselves */
69*f005ef32Sjsg #ifdef CONFIG_PNP
70*f005ef32Sjsg if (IS_ENABLED(CONFIG_PNP) && mchbar_addr &&
71*f005ef32Sjsg pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
72*f005ef32Sjsg return 0;
73*f005ef32Sjsg #endif
74*f005ef32Sjsg
75*f005ef32Sjsg #ifdef __linux__
76*f005ef32Sjsg /* Get some space for it */
77*f005ef32Sjsg i915->gmch.mch_res.name = "i915 MCHBAR";
78*f005ef32Sjsg i915->gmch.mch_res.flags = IORESOURCE_MEM;
79*f005ef32Sjsg ret = pci_bus_alloc_resource(i915->gmch.pdev->bus,
80*f005ef32Sjsg &i915->gmch.mch_res,
81*f005ef32Sjsg MCHBAR_SIZE, MCHBAR_SIZE,
82*f005ef32Sjsg PCIBIOS_MIN_MEM,
83*f005ef32Sjsg 0, pcibios_align_resource,
84*f005ef32Sjsg i915->gmch.pdev);
85*f005ef32Sjsg if (ret) {
86*f005ef32Sjsg drm_dbg(&i915->drm, "failed bus alloc: %d\n", ret);
87*f005ef32Sjsg i915->gmch.mch_res.start = 0;
88*f005ef32Sjsg return ret;
89*f005ef32Sjsg }
90*f005ef32Sjsg #else
91*f005ef32Sjsg if (i915->memex == NULL || extent_alloc(i915->memex,
92*f005ef32Sjsg MCHBAR_SIZE, MCHBAR_SIZE, 0, 0, 0, &i915->gmch.mch_res.start)) {
93*f005ef32Sjsg return -ENOMEM;
94*f005ef32Sjsg }
95*f005ef32Sjsg #endif
96*f005ef32Sjsg
97*f005ef32Sjsg if (GRAPHICS_VER(i915) >= 4)
98*f005ef32Sjsg pci_write_config_dword(i915->gmch.pdev, reg + 4,
99*f005ef32Sjsg upper_32_bits(i915->gmch.mch_res.start));
100*f005ef32Sjsg
101*f005ef32Sjsg pci_write_config_dword(i915->gmch.pdev, reg,
102*f005ef32Sjsg lower_32_bits(i915->gmch.mch_res.start));
103*f005ef32Sjsg return 0;
104*f005ef32Sjsg }
105*f005ef32Sjsg
106*f005ef32Sjsg /* Setup MCHBAR if possible, return true if we should disable it again */
intel_gmch_bar_setup(struct drm_i915_private * i915)107*f005ef32Sjsg void intel_gmch_bar_setup(struct drm_i915_private *i915)
108*f005ef32Sjsg {
109*f005ef32Sjsg int mchbar_reg = GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
110*f005ef32Sjsg u32 temp;
111*f005ef32Sjsg bool enabled;
112*f005ef32Sjsg
113*f005ef32Sjsg if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
114*f005ef32Sjsg return;
115*f005ef32Sjsg
116*f005ef32Sjsg i915->gmch.mchbar_need_disable = false;
117*f005ef32Sjsg
118*f005ef32Sjsg if (IS_I915G(i915) || IS_I915GM(i915)) {
119*f005ef32Sjsg pci_read_config_dword(i915->gmch.pdev, DEVEN, &temp);
120*f005ef32Sjsg enabled = !!(temp & DEVEN_MCHBAR_EN);
121*f005ef32Sjsg } else {
122*f005ef32Sjsg pci_read_config_dword(i915->gmch.pdev, mchbar_reg, &temp);
123*f005ef32Sjsg enabled = temp & 1;
124*f005ef32Sjsg }
125*f005ef32Sjsg
126*f005ef32Sjsg /* If it's already enabled, don't have to do anything */
127*f005ef32Sjsg if (enabled)
128*f005ef32Sjsg return;
129*f005ef32Sjsg
130*f005ef32Sjsg if (intel_alloc_mchbar_resource(i915))
131*f005ef32Sjsg return;
132*f005ef32Sjsg
133*f005ef32Sjsg i915->gmch.mchbar_need_disable = true;
134*f005ef32Sjsg
135*f005ef32Sjsg /* Space is allocated or reserved, so enable it. */
136*f005ef32Sjsg if (IS_I915G(i915) || IS_I915GM(i915)) {
137*f005ef32Sjsg pci_write_config_dword(i915->gmch.pdev, DEVEN,
138*f005ef32Sjsg temp | DEVEN_MCHBAR_EN);
139*f005ef32Sjsg } else {
140*f005ef32Sjsg pci_read_config_dword(i915->gmch.pdev, mchbar_reg, &temp);
141*f005ef32Sjsg pci_write_config_dword(i915->gmch.pdev, mchbar_reg, temp | 1);
142*f005ef32Sjsg }
143*f005ef32Sjsg }
144*f005ef32Sjsg
intel_gmch_bar_teardown(struct drm_i915_private * i915)145*f005ef32Sjsg void intel_gmch_bar_teardown(struct drm_i915_private *i915)
146*f005ef32Sjsg {
147*f005ef32Sjsg int mchbar_reg = GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
148*f005ef32Sjsg
149*f005ef32Sjsg if (i915->gmch.mchbar_need_disable) {
150*f005ef32Sjsg if (IS_I915G(i915) || IS_I915GM(i915)) {
151*f005ef32Sjsg u32 deven_val;
152*f005ef32Sjsg
153*f005ef32Sjsg pci_read_config_dword(i915->gmch.pdev, DEVEN,
154*f005ef32Sjsg &deven_val);
155*f005ef32Sjsg deven_val &= ~DEVEN_MCHBAR_EN;
156*f005ef32Sjsg pci_write_config_dword(i915->gmch.pdev, DEVEN,
157*f005ef32Sjsg deven_val);
158*f005ef32Sjsg } else {
159*f005ef32Sjsg u32 mchbar_val;
160*f005ef32Sjsg
161*f005ef32Sjsg pci_read_config_dword(i915->gmch.pdev, mchbar_reg,
162*f005ef32Sjsg &mchbar_val);
163*f005ef32Sjsg mchbar_val &= ~1;
164*f005ef32Sjsg pci_write_config_dword(i915->gmch.pdev, mchbar_reg,
165*f005ef32Sjsg mchbar_val);
166*f005ef32Sjsg }
167*f005ef32Sjsg }
168*f005ef32Sjsg
169*f005ef32Sjsg if (i915->gmch.mch_res.start)
170*f005ef32Sjsg #ifdef __linux__
171*f005ef32Sjsg release_resource(&i915->gmch.mch_res);
172*f005ef32Sjsg #else
173*f005ef32Sjsg extent_free(i915->memex, i915->gmch.mch_res.start,
174*f005ef32Sjsg MCHBAR_SIZE, 0);
175*f005ef32Sjsg #endif
176*f005ef32Sjsg }
177*f005ef32Sjsg
intel_gmch_vga_set_state(struct drm_i915_private * i915,bool enable_decode)178*f005ef32Sjsg int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
179*f005ef32Sjsg {
180*f005ef32Sjsg unsigned int reg = DISPLAY_VER(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
181*f005ef32Sjsg u16 gmch_ctrl;
182*f005ef32Sjsg
183*f005ef32Sjsg if (pci_read_config_word(i915->gmch.pdev, reg, &gmch_ctrl)) {
184*f005ef32Sjsg drm_err(&i915->drm, "failed to read control word\n");
185*f005ef32Sjsg return -EIO;
186*f005ef32Sjsg }
187*f005ef32Sjsg
188*f005ef32Sjsg if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !enable_decode)
189*f005ef32Sjsg return 0;
190*f005ef32Sjsg
191*f005ef32Sjsg if (enable_decode)
192*f005ef32Sjsg gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
193*f005ef32Sjsg else
194*f005ef32Sjsg gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
195*f005ef32Sjsg
196*f005ef32Sjsg if (pci_write_config_word(i915->gmch.pdev, reg, gmch_ctrl)) {
197*f005ef32Sjsg drm_err(&i915->drm, "failed to write control word\n");
198*f005ef32Sjsg return -EIO;
199*f005ef32Sjsg }
200*f005ef32Sjsg
201*f005ef32Sjsg return 0;
202*f005ef32Sjsg }
203