xref: /openbsd/sys/dev/pci/drm/radeon/avivod.h (revision 7ccd5a2c)
1*1099013bSjsg /*
2*1099013bSjsg  * Copyright 2009 Advanced Micro Devices, Inc.
3*1099013bSjsg  * Copyright 2009 Red Hat Inc.
4*1099013bSjsg  *
5*1099013bSjsg  * Permission is hereby granted, free of charge, to any person obtaining a
6*1099013bSjsg  * copy of this software and associated documentation files (the "Software"),
7*1099013bSjsg  * to deal in the Software without restriction, including without limitation
8*1099013bSjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9*1099013bSjsg  * and/or sell copies of the Software, and to permit persons to whom the
10*1099013bSjsg  * Software is furnished to do so, subject to the following conditions:
11*1099013bSjsg  *
12*1099013bSjsg  * The above copyright notice and this permission notice shall be included in
13*1099013bSjsg  * all copies or substantial portions of the Software.
14*1099013bSjsg  *
15*1099013bSjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16*1099013bSjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17*1099013bSjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18*1099013bSjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19*1099013bSjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20*1099013bSjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21*1099013bSjsg  * OTHER DEALINGS IN THE SOFTWARE.
22*1099013bSjsg  *
23*1099013bSjsg  * Authors: Dave Airlie
24*1099013bSjsg  *          Alex Deucher
25*1099013bSjsg  *          Jerome Glisse
26*1099013bSjsg  */
27*1099013bSjsg #ifndef AVIVOD_H
28*1099013bSjsg #define AVIVOD_H
29*1099013bSjsg 
30*1099013bSjsg 
31*1099013bSjsg #define	D1CRTC_CONTROL					0x6080
32*1099013bSjsg #define		CRTC_EN						(1 << 0)
33*1099013bSjsg #define	D1CRTC_STATUS					0x609c
34*1099013bSjsg #define	D1CRTC_UPDATE_LOCK				0x60E8
35*1099013bSjsg #define	D1GRPH_PRIMARY_SURFACE_ADDRESS			0x6110
36*1099013bSjsg #define	D1GRPH_SECONDARY_SURFACE_ADDRESS		0x6118
37*1099013bSjsg 
38*1099013bSjsg #define	D2CRTC_CONTROL					0x6880
39*1099013bSjsg #define	D2CRTC_STATUS					0x689c
40*1099013bSjsg #define	D2CRTC_UPDATE_LOCK				0x68E8
41*1099013bSjsg #define	D2GRPH_PRIMARY_SURFACE_ADDRESS			0x6910
42*1099013bSjsg #define	D2GRPH_SECONDARY_SURFACE_ADDRESS		0x6918
43*1099013bSjsg 
44*1099013bSjsg #define	D1VGA_CONTROL					0x0330
45*1099013bSjsg #define		DVGA_CONTROL_MODE_ENABLE			(1 << 0)
46*1099013bSjsg #define		DVGA_CONTROL_TIMING_SELECT			(1 << 8)
47*1099013bSjsg #define		DVGA_CONTROL_SYNC_POLARITY_SELECT		(1 << 9)
48*1099013bSjsg #define		DVGA_CONTROL_OVERSCAN_TIMING_SELECT		(1 << 10)
49*1099013bSjsg #define		DVGA_CONTROL_OVERSCAN_COLOR_EN			(1 << 16)
50*1099013bSjsg #define		DVGA_CONTROL_ROTATE				(1 << 24)
51*1099013bSjsg #define D2VGA_CONTROL					0x0338
52*1099013bSjsg 
53*1099013bSjsg #define	VGA_HDP_CONTROL					0x328
54*1099013bSjsg #define		VGA_MEM_PAGE_SELECT_EN				(1 << 0)
55*1099013bSjsg #define		VGA_MEMORY_DISABLE				(1 << 4)
56*1099013bSjsg #define		VGA_RBBM_LOCK_DISABLE				(1 << 8)
57*1099013bSjsg #define		VGA_SOFT_RESET					(1 << 16)
58*1099013bSjsg #define	VGA_MEMORY_BASE_ADDRESS				0x0310
59*1099013bSjsg #define	VGA_RENDER_CONTROL				0x0300
60*1099013bSjsg #define		VGA_VSTATUS_CNTL_MASK				0x00030000
61*1099013bSjsg 
62*1099013bSjsg #endif
63