17ccd5a2cSjsg /* 27ccd5a2cSjsg * Copyright 2012 Advanced Micro Devices, Inc. 37ccd5a2cSjsg * 47ccd5a2cSjsg * Permission is hereby granted, free of charge, to any person obtaining a 57ccd5a2cSjsg * copy of this software and associated documentation files (the "Software"), 67ccd5a2cSjsg * to deal in the Software without restriction, including without limitation 77ccd5a2cSjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87ccd5a2cSjsg * and/or sell copies of the Software, and to permit persons to whom the 97ccd5a2cSjsg * Software is furnished to do so, subject to the following conditions: 107ccd5a2cSjsg * 117ccd5a2cSjsg * The above copyright notice and this permission notice shall be included in 127ccd5a2cSjsg * all copies or substantial portions of the Software. 137ccd5a2cSjsg * 147ccd5a2cSjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 157ccd5a2cSjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 167ccd5a2cSjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 177ccd5a2cSjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 187ccd5a2cSjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 197ccd5a2cSjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 207ccd5a2cSjsg * OTHER DEALINGS IN THE SOFTWARE. 217ccd5a2cSjsg * 227ccd5a2cSjsg * Authors: Alex Deucher 237ccd5a2cSjsg */ 247ccd5a2cSjsg #ifndef CIK_H 257ccd5a2cSjsg #define CIK_H 267ccd5a2cSjsg 277ccd5a2cSjsg #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 287ccd5a2cSjsg #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 297ccd5a2cSjsg 307ccd5a2cSjsg #define CIK_RB_BITMAP_WIDTH_PER_SH 2 317ccd5a2cSjsg #define HAWAII_RB_BITMAP_WIDTH_PER_SH 4 327ccd5a2cSjsg 337ccd5a2cSjsg /* DIDT IND registers */ 347ccd5a2cSjsg #define DIDT_SQ_CTRL0 0x0 357ccd5a2cSjsg # define DIDT_CTRL_EN (1 << 0) 367ccd5a2cSjsg #define DIDT_DB_CTRL0 0x20 377ccd5a2cSjsg #define DIDT_TD_CTRL0 0x40 387ccd5a2cSjsg #define DIDT_TCP_CTRL0 0x60 397ccd5a2cSjsg 407ccd5a2cSjsg /* SMC IND registers */ 417ccd5a2cSjsg #define DPM_TABLE_475 0x3F768 427ccd5a2cSjsg # define SamuBootLevel(x) ((x) << 0) 437ccd5a2cSjsg # define SamuBootLevel_MASK 0x000000ff 447ccd5a2cSjsg # define SamuBootLevel_SHIFT 0 457ccd5a2cSjsg # define AcpBootLevel(x) ((x) << 8) 467ccd5a2cSjsg # define AcpBootLevel_MASK 0x0000ff00 477ccd5a2cSjsg # define AcpBootLevel_SHIFT 8 487ccd5a2cSjsg # define VceBootLevel(x) ((x) << 16) 497ccd5a2cSjsg # define VceBootLevel_MASK 0x00ff0000 507ccd5a2cSjsg # define VceBootLevel_SHIFT 16 517ccd5a2cSjsg # define UvdBootLevel(x) ((x) << 24) 527ccd5a2cSjsg # define UvdBootLevel_MASK 0xff000000 537ccd5a2cSjsg # define UvdBootLevel_SHIFT 24 547ccd5a2cSjsg 557ccd5a2cSjsg #define FIRMWARE_FLAGS 0x3F800 567ccd5a2cSjsg # define INTERRUPTS_ENABLED (1 << 0) 577ccd5a2cSjsg 587ccd5a2cSjsg #define NB_DPM_CONFIG_1 0x3F9E8 597ccd5a2cSjsg # define Dpm0PgNbPsLo(x) ((x) << 0) 607ccd5a2cSjsg # define Dpm0PgNbPsLo_MASK 0x000000ff 617ccd5a2cSjsg # define Dpm0PgNbPsLo_SHIFT 0 627ccd5a2cSjsg # define Dpm0PgNbPsHi(x) ((x) << 8) 637ccd5a2cSjsg # define Dpm0PgNbPsHi_MASK 0x0000ff00 647ccd5a2cSjsg # define Dpm0PgNbPsHi_SHIFT 8 657ccd5a2cSjsg # define DpmXNbPsLo(x) ((x) << 16) 667ccd5a2cSjsg # define DpmXNbPsLo_MASK 0x00ff0000 677ccd5a2cSjsg # define DpmXNbPsLo_SHIFT 16 687ccd5a2cSjsg # define DpmXNbPsHi(x) ((x) << 24) 697ccd5a2cSjsg # define DpmXNbPsHi_MASK 0xff000000 707ccd5a2cSjsg # define DpmXNbPsHi_SHIFT 24 717ccd5a2cSjsg 727ccd5a2cSjsg #define SMC_SYSCON_RESET_CNTL 0x80000000 737ccd5a2cSjsg # define RST_REG (1 << 0) 747ccd5a2cSjsg #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 757ccd5a2cSjsg # define CK_DISABLE (1 << 0) 767ccd5a2cSjsg # define CKEN (1 << 24) 777ccd5a2cSjsg 787ccd5a2cSjsg #define SMC_SYSCON_MISC_CNTL 0x80000010 797ccd5a2cSjsg 807ccd5a2cSjsg #define SMC_SYSCON_MSG_ARG_0 0x80000068 817ccd5a2cSjsg 827ccd5a2cSjsg #define SMC_PC_C 0x80000370 837ccd5a2cSjsg 847ccd5a2cSjsg #define SMC_SCRATCH9 0x80000424 857ccd5a2cSjsg 867ccd5a2cSjsg #define RCU_UC_EVENTS 0xC0000004 877ccd5a2cSjsg # define BOOT_SEQ_DONE (1 << 7) 887ccd5a2cSjsg 897ccd5a2cSjsg #define GENERAL_PWRMGT 0xC0200000 907ccd5a2cSjsg # define GLOBAL_PWRMGT_EN (1 << 0) 917ccd5a2cSjsg # define STATIC_PM_EN (1 << 1) 927ccd5a2cSjsg # define THERMAL_PROTECTION_DIS (1 << 2) 937ccd5a2cSjsg # define THERMAL_PROTECTION_TYPE (1 << 3) 947ccd5a2cSjsg # define SW_SMIO_INDEX(x) ((x) << 6) 957ccd5a2cSjsg # define SW_SMIO_INDEX_MASK (1 << 6) 967ccd5a2cSjsg # define SW_SMIO_INDEX_SHIFT 6 977ccd5a2cSjsg # define VOLT_PWRMGT_EN (1 << 10) 987ccd5a2cSjsg # define GPU_COUNTER_CLK (1 << 15) 997ccd5a2cSjsg # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 1007ccd5a2cSjsg 1017ccd5a2cSjsg #define CNB_PWRMGT_CNTL 0xC0200004 1027ccd5a2cSjsg # define GNB_SLOW_MODE(x) ((x) << 0) 1037ccd5a2cSjsg # define GNB_SLOW_MODE_MASK (3 << 0) 1047ccd5a2cSjsg # define GNB_SLOW_MODE_SHIFT 0 1057ccd5a2cSjsg # define GNB_SLOW (1 << 2) 1067ccd5a2cSjsg # define FORCE_NB_PS1 (1 << 3) 1077ccd5a2cSjsg # define DPM_ENABLED (1 << 4) 1087ccd5a2cSjsg 1097ccd5a2cSjsg #define SCLK_PWRMGT_CNTL 0xC0200008 1107ccd5a2cSjsg # define SCLK_PWRMGT_OFF (1 << 0) 1117ccd5a2cSjsg # define RESET_BUSY_CNT (1 << 4) 1127ccd5a2cSjsg # define RESET_SCLK_CNT (1 << 5) 1137ccd5a2cSjsg # define DYNAMIC_PM_EN (1 << 21) 1147ccd5a2cSjsg 1157ccd5a2cSjsg #define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014 1167ccd5a2cSjsg # define CURRENT_STATE_MASK (0xf << 4) 1177ccd5a2cSjsg # define CURRENT_STATE_SHIFT 4 1187ccd5a2cSjsg # define CURR_MCLK_INDEX_MASK (0xf << 8) 1197ccd5a2cSjsg # define CURR_MCLK_INDEX_SHIFT 8 1207ccd5a2cSjsg # define CURR_SCLK_INDEX_MASK (0x1f << 16) 1217ccd5a2cSjsg # define CURR_SCLK_INDEX_SHIFT 16 1227ccd5a2cSjsg 1237ccd5a2cSjsg #define CG_SSP 0xC0200044 1247ccd5a2cSjsg # define SST(x) ((x) << 0) 1257ccd5a2cSjsg # define SST_MASK (0xffff << 0) 1267ccd5a2cSjsg # define SSTU(x) ((x) << 16) 1277ccd5a2cSjsg # define SSTU_MASK (0xf << 16) 1287ccd5a2cSjsg 1297ccd5a2cSjsg #define CG_DISPLAY_GAP_CNTL 0xC0200060 1307ccd5a2cSjsg # define DISP_GAP(x) ((x) << 0) 1317ccd5a2cSjsg # define DISP_GAP_MASK (3 << 0) 1327ccd5a2cSjsg # define VBI_TIMER_COUNT(x) ((x) << 4) 1337ccd5a2cSjsg # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 1347ccd5a2cSjsg # define VBI_TIMER_UNIT(x) ((x) << 20) 1357ccd5a2cSjsg # define VBI_TIMER_UNIT_MASK (7 << 20) 1367ccd5a2cSjsg # define DISP_GAP_MCHG(x) ((x) << 24) 1377ccd5a2cSjsg # define DISP_GAP_MCHG_MASK (3 << 24) 1387ccd5a2cSjsg 1397ccd5a2cSjsg #define SMU_VOLTAGE_STATUS 0xC0200094 1407ccd5a2cSjsg # define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1) 1417ccd5a2cSjsg # define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1 1427ccd5a2cSjsg 1437ccd5a2cSjsg #define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0 1447ccd5a2cSjsg # define CURR_PCIE_INDEX_MASK (0xf << 24) 1457ccd5a2cSjsg # define CURR_PCIE_INDEX_SHIFT 24 1467ccd5a2cSjsg 1477ccd5a2cSjsg #define CG_ULV_PARAMETER 0xC0200158 1487ccd5a2cSjsg 1497ccd5a2cSjsg #define CG_FTV_0 0xC02001A8 1507ccd5a2cSjsg #define CG_FTV_1 0xC02001AC 1517ccd5a2cSjsg #define CG_FTV_2 0xC02001B0 1527ccd5a2cSjsg #define CG_FTV_3 0xC02001B4 1537ccd5a2cSjsg #define CG_FTV_4 0xC02001B8 1547ccd5a2cSjsg #define CG_FTV_5 0xC02001BC 1557ccd5a2cSjsg #define CG_FTV_6 0xC02001C0 1567ccd5a2cSjsg #define CG_FTV_7 0xC02001C4 1577ccd5a2cSjsg 1587ccd5a2cSjsg #define CG_DISPLAY_GAP_CNTL2 0xC0200230 1597ccd5a2cSjsg 1607ccd5a2cSjsg #define LCAC_SX0_OVR_SEL 0xC0400D04 1617ccd5a2cSjsg #define LCAC_SX0_OVR_VAL 0xC0400D08 1627ccd5a2cSjsg 1637ccd5a2cSjsg #define LCAC_MC0_CNTL 0xC0400D30 1647ccd5a2cSjsg #define LCAC_MC0_OVR_SEL 0xC0400D34 1657ccd5a2cSjsg #define LCAC_MC0_OVR_VAL 0xC0400D38 1667ccd5a2cSjsg #define LCAC_MC1_CNTL 0xC0400D3C 1677ccd5a2cSjsg #define LCAC_MC1_OVR_SEL 0xC0400D40 1687ccd5a2cSjsg #define LCAC_MC1_OVR_VAL 0xC0400D44 1697ccd5a2cSjsg 1707ccd5a2cSjsg #define LCAC_MC2_OVR_SEL 0xC0400D4C 1717ccd5a2cSjsg #define LCAC_MC2_OVR_VAL 0xC0400D50 1727ccd5a2cSjsg 1737ccd5a2cSjsg #define LCAC_MC3_OVR_SEL 0xC0400D58 1747ccd5a2cSjsg #define LCAC_MC3_OVR_VAL 0xC0400D5C 1757ccd5a2cSjsg 1767ccd5a2cSjsg #define LCAC_CPL_CNTL 0xC0400D80 1777ccd5a2cSjsg #define LCAC_CPL_OVR_SEL 0xC0400D84 1787ccd5a2cSjsg #define LCAC_CPL_OVR_VAL 0xC0400D88 1797ccd5a2cSjsg 1807ccd5a2cSjsg /* dGPU */ 1817ccd5a2cSjsg #define CG_THERMAL_CTRL 0xC0300004 1827ccd5a2cSjsg #define DPM_EVENT_SRC(x) ((x) << 0) 1837ccd5a2cSjsg #define DPM_EVENT_SRC_MASK (7 << 0) 1847ccd5a2cSjsg #define DIG_THERM_DPM(x) ((x) << 14) 1857ccd5a2cSjsg #define DIG_THERM_DPM_MASK 0x003FC000 1867ccd5a2cSjsg #define DIG_THERM_DPM_SHIFT 14 1877ccd5a2cSjsg #define CG_THERMAL_STATUS 0xC0300008 1887ccd5a2cSjsg #define FDO_PWM_DUTY(x) ((x) << 9) 1897ccd5a2cSjsg #define FDO_PWM_DUTY_MASK (0xff << 9) 1907ccd5a2cSjsg #define FDO_PWM_DUTY_SHIFT 9 1917ccd5a2cSjsg #define CG_THERMAL_INT 0xC030000C 1927ccd5a2cSjsg #define CI_DIG_THERM_INTH(x) ((x) << 8) 1937ccd5a2cSjsg #define CI_DIG_THERM_INTH_MASK 0x0000FF00 1947ccd5a2cSjsg #define CI_DIG_THERM_INTH_SHIFT 8 1957ccd5a2cSjsg #define CI_DIG_THERM_INTL(x) ((x) << 16) 1967ccd5a2cSjsg #define CI_DIG_THERM_INTL_MASK 0x00FF0000 1977ccd5a2cSjsg #define CI_DIG_THERM_INTL_SHIFT 16 1987ccd5a2cSjsg #define THERM_INT_MASK_HIGH (1 << 24) 1997ccd5a2cSjsg #define THERM_INT_MASK_LOW (1 << 25) 2007ccd5a2cSjsg #define CG_MULT_THERMAL_CTRL 0xC0300010 2017ccd5a2cSjsg #define TEMP_SEL(x) ((x) << 20) 2027ccd5a2cSjsg #define TEMP_SEL_MASK (0xff << 20) 2037ccd5a2cSjsg #define TEMP_SEL_SHIFT 20 2047ccd5a2cSjsg #define CG_MULT_THERMAL_STATUS 0xC0300014 2057ccd5a2cSjsg #define ASIC_MAX_TEMP(x) ((x) << 0) 2067ccd5a2cSjsg #define ASIC_MAX_TEMP_MASK 0x000001ff 2077ccd5a2cSjsg #define ASIC_MAX_TEMP_SHIFT 0 2087ccd5a2cSjsg #define CTF_TEMP(x) ((x) << 9) 2097ccd5a2cSjsg #define CTF_TEMP_MASK 0x0003fe00 2107ccd5a2cSjsg #define CTF_TEMP_SHIFT 9 2117ccd5a2cSjsg 2127ccd5a2cSjsg #define CG_FDO_CTRL0 0xC0300064 2137ccd5a2cSjsg #define FDO_STATIC_DUTY(x) ((x) << 0) 2147ccd5a2cSjsg #define FDO_STATIC_DUTY_MASK 0x000000FF 2157ccd5a2cSjsg #define FDO_STATIC_DUTY_SHIFT 0 2167ccd5a2cSjsg #define CG_FDO_CTRL1 0xC0300068 2177ccd5a2cSjsg #define FMAX_DUTY100(x) ((x) << 0) 2187ccd5a2cSjsg #define FMAX_DUTY100_MASK 0x000000FF 2197ccd5a2cSjsg #define FMAX_DUTY100_SHIFT 0 2207ccd5a2cSjsg #define CG_FDO_CTRL2 0xC030006C 2217ccd5a2cSjsg #define TMIN(x) ((x) << 0) 2227ccd5a2cSjsg #define TMIN_MASK 0x000000FF 2237ccd5a2cSjsg #define TMIN_SHIFT 0 2247ccd5a2cSjsg #define FDO_PWM_MODE(x) ((x) << 11) 2257ccd5a2cSjsg #define FDO_PWM_MODE_MASK (7 << 11) 2267ccd5a2cSjsg #define FDO_PWM_MODE_SHIFT 11 2277ccd5a2cSjsg #define TACH_PWM_RESP_RATE(x) ((x) << 25) 2287ccd5a2cSjsg #define TACH_PWM_RESP_RATE_MASK (0x7f << 25) 2297ccd5a2cSjsg #define TACH_PWM_RESP_RATE_SHIFT 25 2307ccd5a2cSjsg #define CG_TACH_CTRL 0xC0300070 2317ccd5a2cSjsg # define EDGE_PER_REV(x) ((x) << 0) 2327ccd5a2cSjsg # define EDGE_PER_REV_MASK (0x7 << 0) 2337ccd5a2cSjsg # define EDGE_PER_REV_SHIFT 0 2347ccd5a2cSjsg # define TARGET_PERIOD(x) ((x) << 3) 2357ccd5a2cSjsg # define TARGET_PERIOD_MASK 0xfffffff8 2367ccd5a2cSjsg # define TARGET_PERIOD_SHIFT 3 2377ccd5a2cSjsg #define CG_TACH_STATUS 0xC0300074 2387ccd5a2cSjsg # define TACH_PERIOD(x) ((x) << 0) 2397ccd5a2cSjsg # define TACH_PERIOD_MASK 0xffffffff 2407ccd5a2cSjsg # define TACH_PERIOD_SHIFT 0 2417ccd5a2cSjsg 2427ccd5a2cSjsg #define CG_ECLK_CNTL 0xC05000AC 2437ccd5a2cSjsg # define ECLK_DIVIDER_MASK 0x7f 2447ccd5a2cSjsg # define ECLK_DIR_CNTL_EN (1 << 8) 2457ccd5a2cSjsg #define CG_ECLK_STATUS 0xC05000B0 2467ccd5a2cSjsg # define ECLK_STATUS (1 << 0) 2477ccd5a2cSjsg 2487ccd5a2cSjsg #define CG_SPLL_FUNC_CNTL 0xC0500140 2497ccd5a2cSjsg #define SPLL_RESET (1 << 0) 2507ccd5a2cSjsg #define SPLL_PWRON (1 << 1) 2517ccd5a2cSjsg #define SPLL_BYPASS_EN (1 << 3) 2527ccd5a2cSjsg #define SPLL_REF_DIV(x) ((x) << 5) 2537ccd5a2cSjsg #define SPLL_REF_DIV_MASK (0x3f << 5) 2547ccd5a2cSjsg #define SPLL_PDIV_A(x) ((x) << 20) 2557ccd5a2cSjsg #define SPLL_PDIV_A_MASK (0x7f << 20) 2567ccd5a2cSjsg #define SPLL_PDIV_A_SHIFT 20 2577ccd5a2cSjsg #define CG_SPLL_FUNC_CNTL_2 0xC0500144 2587ccd5a2cSjsg #define SCLK_MUX_SEL(x) ((x) << 0) 2597ccd5a2cSjsg #define SCLK_MUX_SEL_MASK (0x1ff << 0) 2607ccd5a2cSjsg #define CG_SPLL_FUNC_CNTL_3 0xC0500148 2617ccd5a2cSjsg #define SPLL_FB_DIV(x) ((x) << 0) 2627ccd5a2cSjsg #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 2637ccd5a2cSjsg #define SPLL_FB_DIV_SHIFT 0 2647ccd5a2cSjsg #define SPLL_DITHEN (1 << 28) 2657ccd5a2cSjsg #define CG_SPLL_FUNC_CNTL_4 0xC050014C 2667ccd5a2cSjsg 2677ccd5a2cSjsg #define CG_SPLL_SPREAD_SPECTRUM 0xC0500164 2687ccd5a2cSjsg #define SSEN (1 << 0) 2697ccd5a2cSjsg #define CLK_S(x) ((x) << 4) 2707ccd5a2cSjsg #define CLK_S_MASK (0xfff << 4) 2717ccd5a2cSjsg #define CLK_S_SHIFT 4 2727ccd5a2cSjsg #define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168 2737ccd5a2cSjsg #define CLK_V(x) ((x) << 0) 2747ccd5a2cSjsg #define CLK_V_MASK (0x3ffffff << 0) 2757ccd5a2cSjsg #define CLK_V_SHIFT 0 2767ccd5a2cSjsg 2777ccd5a2cSjsg #define MPLL_BYPASSCLK_SEL 0xC050019C 2787ccd5a2cSjsg # define MPLL_CLKOUT_SEL(x) ((x) << 8) 2797ccd5a2cSjsg # define MPLL_CLKOUT_SEL_MASK 0xFF00 2807ccd5a2cSjsg #define CG_CLKPIN_CNTL 0xC05001A0 2817ccd5a2cSjsg # define XTALIN_DIVIDE (1 << 1) 2827ccd5a2cSjsg # define BCLK_AS_XCLK (1 << 2) 2837ccd5a2cSjsg #define CG_CLKPIN_CNTL_2 0xC05001A4 2847ccd5a2cSjsg # define FORCE_BIF_REFCLK_EN (1 << 3) 2857ccd5a2cSjsg # define MUX_TCLK_TO_XCLK (1 << 8) 2867ccd5a2cSjsg #define THM_CLK_CNTL 0xC05001A8 2877ccd5a2cSjsg # define CMON_CLK_SEL(x) ((x) << 0) 2887ccd5a2cSjsg # define CMON_CLK_SEL_MASK 0xFF 2897ccd5a2cSjsg # define TMON_CLK_SEL(x) ((x) << 8) 2907ccd5a2cSjsg # define TMON_CLK_SEL_MASK 0xFF00 2917ccd5a2cSjsg #define MISC_CLK_CTRL 0xC05001AC 2927ccd5a2cSjsg # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) 2937ccd5a2cSjsg # define DEEP_SLEEP_CLK_SEL_MASK 0xFF 2947ccd5a2cSjsg # define ZCLK_SEL(x) ((x) << 8) 2957ccd5a2cSjsg # define ZCLK_SEL_MASK 0xFF00 2967ccd5a2cSjsg 2977ccd5a2cSjsg /* KV/KB */ 2987ccd5a2cSjsg #define CG_THERMAL_INT_CTRL 0xC2100028 2997ccd5a2cSjsg #define DIG_THERM_INTH(x) ((x) << 0) 3007ccd5a2cSjsg #define DIG_THERM_INTH_MASK 0x000000FF 3017ccd5a2cSjsg #define DIG_THERM_INTH_SHIFT 0 3027ccd5a2cSjsg #define DIG_THERM_INTL(x) ((x) << 8) 3037ccd5a2cSjsg #define DIG_THERM_INTL_MASK 0x0000FF00 3047ccd5a2cSjsg #define DIG_THERM_INTL_SHIFT 8 3057ccd5a2cSjsg #define THERM_INTH_MASK (1 << 24) 3067ccd5a2cSjsg #define THERM_INTL_MASK (1 << 25) 3077ccd5a2cSjsg 3087ccd5a2cSjsg /* PCIE registers idx/data 0x38/0x3c */ 3097ccd5a2cSjsg #define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */ 3107ccd5a2cSjsg # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 3117ccd5a2cSjsg # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 3127ccd5a2cSjsg # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 3137ccd5a2cSjsg # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 3147ccd5a2cSjsg # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 3157ccd5a2cSjsg # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 3167ccd5a2cSjsg # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 3177ccd5a2cSjsg # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 3187ccd5a2cSjsg # define PLL_RAMP_UP_TIME_0_SHIFT 24 3197ccd5a2cSjsg #define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */ 3207ccd5a2cSjsg # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 3217ccd5a2cSjsg # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 3227ccd5a2cSjsg # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 3237ccd5a2cSjsg # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 3247ccd5a2cSjsg # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 3257ccd5a2cSjsg # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 3267ccd5a2cSjsg # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 3277ccd5a2cSjsg # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 3287ccd5a2cSjsg # define PLL_RAMP_UP_TIME_1_SHIFT 24 3297ccd5a2cSjsg 3307ccd5a2cSjsg #define PCIE_CNTL2 0x1001001c /* PCIE */ 3317ccd5a2cSjsg # define SLV_MEM_LS_EN (1 << 16) 3327ccd5a2cSjsg # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17) 3337ccd5a2cSjsg # define MST_MEM_LS_EN (1 << 18) 3347ccd5a2cSjsg # define REPLAY_MEM_LS_EN (1 << 19) 3357ccd5a2cSjsg 3367ccd5a2cSjsg #define PCIE_LC_STATUS1 0x1400028 /* PCIE */ 3377ccd5a2cSjsg # define LC_REVERSE_RCVR (1 << 0) 3387ccd5a2cSjsg # define LC_REVERSE_XMIT (1 << 1) 3397ccd5a2cSjsg # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) 3407ccd5a2cSjsg # define LC_OPERATING_LINK_WIDTH_SHIFT 2 3417ccd5a2cSjsg # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) 3427ccd5a2cSjsg # define LC_DETECTED_LINK_WIDTH_SHIFT 5 3437ccd5a2cSjsg 3447ccd5a2cSjsg #define PCIE_P_CNTL 0x1400040 /* PCIE */ 3457ccd5a2cSjsg # define P_IGNORE_EDB_ERR (1 << 6) 3467ccd5a2cSjsg 3477ccd5a2cSjsg #define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */ 3487ccd5a2cSjsg #define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */ 3497ccd5a2cSjsg 3507ccd5a2cSjsg #define PCIE_LC_CNTL 0x100100A0 /* PCIE */ 3517ccd5a2cSjsg # define LC_L0S_INACTIVITY(x) ((x) << 8) 3527ccd5a2cSjsg # define LC_L0S_INACTIVITY_MASK (0xf << 8) 3537ccd5a2cSjsg # define LC_L0S_INACTIVITY_SHIFT 8 3547ccd5a2cSjsg # define LC_L1_INACTIVITY(x) ((x) << 12) 3557ccd5a2cSjsg # define LC_L1_INACTIVITY_MASK (0xf << 12) 3567ccd5a2cSjsg # define LC_L1_INACTIVITY_SHIFT 12 3577ccd5a2cSjsg # define LC_PMI_TO_L1_DIS (1 << 16) 3587ccd5a2cSjsg # define LC_ASPM_TO_L1_DIS (1 << 24) 3597ccd5a2cSjsg 3607ccd5a2cSjsg #define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */ 3617ccd5a2cSjsg # define LC_LINK_WIDTH_SHIFT 0 3627ccd5a2cSjsg # define LC_LINK_WIDTH_MASK 0x7 3637ccd5a2cSjsg # define LC_LINK_WIDTH_X0 0 3647ccd5a2cSjsg # define LC_LINK_WIDTH_X1 1 3657ccd5a2cSjsg # define LC_LINK_WIDTH_X2 2 3667ccd5a2cSjsg # define LC_LINK_WIDTH_X4 3 3677ccd5a2cSjsg # define LC_LINK_WIDTH_X8 4 3687ccd5a2cSjsg # define LC_LINK_WIDTH_X16 6 3697ccd5a2cSjsg # define LC_LINK_WIDTH_RD_SHIFT 4 3707ccd5a2cSjsg # define LC_LINK_WIDTH_RD_MASK 0x70 3717ccd5a2cSjsg # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 3727ccd5a2cSjsg # define LC_RECONFIG_NOW (1 << 8) 3737ccd5a2cSjsg # define LC_RENEGOTIATION_SUPPORT (1 << 9) 3747ccd5a2cSjsg # define LC_RENEGOTIATE_EN (1 << 10) 3757ccd5a2cSjsg # define LC_SHORT_RECONFIG_EN (1 << 11) 3767ccd5a2cSjsg # define LC_UPCONFIGURE_SUPPORT (1 << 12) 3777ccd5a2cSjsg # define LC_UPCONFIGURE_DIS (1 << 13) 3787ccd5a2cSjsg # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 3797ccd5a2cSjsg # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 3807ccd5a2cSjsg # define LC_DYN_LANES_PWR_STATE_SHIFT 21 3817ccd5a2cSjsg #define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */ 3827ccd5a2cSjsg # define LC_XMIT_N_FTS(x) ((x) << 0) 3837ccd5a2cSjsg # define LC_XMIT_N_FTS_MASK (0xff << 0) 3847ccd5a2cSjsg # define LC_XMIT_N_FTS_SHIFT 0 3857ccd5a2cSjsg # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) 3867ccd5a2cSjsg # define LC_N_FTS_MASK (0xff << 24) 3877ccd5a2cSjsg #define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */ 3887ccd5a2cSjsg # define LC_GEN2_EN_STRAP (1 << 0) 3897ccd5a2cSjsg # define LC_GEN3_EN_STRAP (1 << 1) 3907ccd5a2cSjsg # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) 3917ccd5a2cSjsg # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) 3927ccd5a2cSjsg # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 3937ccd5a2cSjsg # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) 3947ccd5a2cSjsg # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) 3957ccd5a2cSjsg # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) 3967ccd5a2cSjsg # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) 3977ccd5a2cSjsg # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) 3987ccd5a2cSjsg # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) 3997ccd5a2cSjsg # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 4007ccd5a2cSjsg # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ 4017ccd5a2cSjsg # define LC_CURRENT_DATA_RATE_SHIFT 13 4027ccd5a2cSjsg # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) 4037ccd5a2cSjsg # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) 4047ccd5a2cSjsg # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) 4057ccd5a2cSjsg # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) 4067ccd5a2cSjsg # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) 4077ccd5a2cSjsg 4087ccd5a2cSjsg #define PCIE_LC_CNTL2 0x100100B1 /* PCIE */ 4097ccd5a2cSjsg # define LC_ALLOW_PDWN_IN_L1 (1 << 17) 4107ccd5a2cSjsg # define LC_ALLOW_PDWN_IN_L23 (1 << 18) 4117ccd5a2cSjsg 4127ccd5a2cSjsg #define PCIE_LC_CNTL3 0x100100B5 /* PCIE */ 4137ccd5a2cSjsg # define LC_GO_TO_RECOVERY (1 << 30) 4147ccd5a2cSjsg #define PCIE_LC_CNTL4 0x100100B6 /* PCIE */ 4157ccd5a2cSjsg # define LC_REDO_EQ (1 << 5) 4167ccd5a2cSjsg # define LC_SET_QUIESCE (1 << 13) 4177ccd5a2cSjsg 4187ccd5a2cSjsg /* direct registers */ 4197ccd5a2cSjsg #define PCIE_INDEX 0x38 4207ccd5a2cSjsg #define PCIE_DATA 0x3C 4217ccd5a2cSjsg 4227ccd5a2cSjsg #define SMC_IND_INDEX_0 0x200 4237ccd5a2cSjsg #define SMC_IND_DATA_0 0x204 4247ccd5a2cSjsg 4257ccd5a2cSjsg #define SMC_IND_ACCESS_CNTL 0x240 4267ccd5a2cSjsg #define AUTO_INCREMENT_IND_0 (1 << 0) 4277ccd5a2cSjsg 4287ccd5a2cSjsg #define SMC_MESSAGE_0 0x250 4297ccd5a2cSjsg #define SMC_MSG_MASK 0xffff 4307ccd5a2cSjsg #define SMC_RESP_0 0x254 4317ccd5a2cSjsg #define SMC_RESP_MASK 0xffff 4327ccd5a2cSjsg 4337ccd5a2cSjsg #define SMC_MSG_ARG_0 0x290 4347ccd5a2cSjsg 4357ccd5a2cSjsg #define VGA_HDP_CONTROL 0x328 4367ccd5a2cSjsg #define VGA_MEMORY_DISABLE (1 << 4) 4377ccd5a2cSjsg 4387ccd5a2cSjsg #define DMIF_ADDR_CALC 0xC00 4397ccd5a2cSjsg 4407ccd5a2cSjsg #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 4417ccd5a2cSjsg # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 4427ccd5a2cSjsg # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 4437ccd5a2cSjsg 4447ccd5a2cSjsg #define SRBM_GFX_CNTL 0xE44 4457ccd5a2cSjsg #define PIPEID(x) ((x) << 0) 4467ccd5a2cSjsg #define MEID(x) ((x) << 2) 4477ccd5a2cSjsg #define VMID(x) ((x) << 4) 4487ccd5a2cSjsg #define QUEUEID(x) ((x) << 8) 4497ccd5a2cSjsg 4507ccd5a2cSjsg #define SRBM_STATUS2 0xE4C 4517ccd5a2cSjsg #define SDMA_BUSY (1 << 5) 4527ccd5a2cSjsg #define SDMA1_BUSY (1 << 6) 4537ccd5a2cSjsg #define SRBM_STATUS 0xE50 4547ccd5a2cSjsg #define UVD_RQ_PENDING (1 << 1) 4557ccd5a2cSjsg #define GRBM_RQ_PENDING (1 << 5) 4567ccd5a2cSjsg #define VMC_BUSY (1 << 8) 4577ccd5a2cSjsg #define MCB_BUSY (1 << 9) 4587ccd5a2cSjsg #define MCB_NON_DISPLAY_BUSY (1 << 10) 4597ccd5a2cSjsg #define MCC_BUSY (1 << 11) 4607ccd5a2cSjsg #define MCD_BUSY (1 << 12) 4617ccd5a2cSjsg #define SEM_BUSY (1 << 14) 4627ccd5a2cSjsg #define IH_BUSY (1 << 17) 4637ccd5a2cSjsg #define UVD_BUSY (1 << 19) 4647ccd5a2cSjsg 4657ccd5a2cSjsg #define SRBM_SOFT_RESET 0xE60 4667ccd5a2cSjsg #define SOFT_RESET_BIF (1 << 1) 4677ccd5a2cSjsg #define SOFT_RESET_R0PLL (1 << 4) 4687ccd5a2cSjsg #define SOFT_RESET_DC (1 << 5) 4697ccd5a2cSjsg #define SOFT_RESET_SDMA1 (1 << 6) 4707ccd5a2cSjsg #define SOFT_RESET_GRBM (1 << 8) 4717ccd5a2cSjsg #define SOFT_RESET_HDP (1 << 9) 4727ccd5a2cSjsg #define SOFT_RESET_IH (1 << 10) 4737ccd5a2cSjsg #define SOFT_RESET_MC (1 << 11) 4747ccd5a2cSjsg #define SOFT_RESET_ROM (1 << 14) 4757ccd5a2cSjsg #define SOFT_RESET_SEM (1 << 15) 4767ccd5a2cSjsg #define SOFT_RESET_VMC (1 << 17) 4777ccd5a2cSjsg #define SOFT_RESET_SDMA (1 << 20) 4787ccd5a2cSjsg #define SOFT_RESET_TST (1 << 21) 4797ccd5a2cSjsg #define SOFT_RESET_REGBB (1 << 22) 4807ccd5a2cSjsg #define SOFT_RESET_ORB (1 << 23) 4817ccd5a2cSjsg #define SOFT_RESET_VCE (1 << 24) 4827ccd5a2cSjsg 4837ccd5a2cSjsg #define SRBM_READ_ERROR 0xE98 4847ccd5a2cSjsg #define SRBM_INT_CNTL 0xEA0 4857ccd5a2cSjsg #define SRBM_INT_ACK 0xEA8 4867ccd5a2cSjsg 4877ccd5a2cSjsg #define VM_L2_CNTL 0x1400 4887ccd5a2cSjsg #define ENABLE_L2_CACHE (1 << 0) 4897ccd5a2cSjsg #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 4907ccd5a2cSjsg #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 4917ccd5a2cSjsg #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 4927ccd5a2cSjsg #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 4937ccd5a2cSjsg #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 4947ccd5a2cSjsg #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 4957ccd5a2cSjsg #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 4967ccd5a2cSjsg #define VM_L2_CNTL2 0x1404 4977ccd5a2cSjsg #define INVALIDATE_ALL_L1_TLBS (1 << 0) 4987ccd5a2cSjsg #define INVALIDATE_L2_CACHE (1 << 1) 4997ccd5a2cSjsg #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 5007ccd5a2cSjsg #define INVALIDATE_PTE_AND_PDE_CACHES 0 5017ccd5a2cSjsg #define INVALIDATE_ONLY_PTE_CACHES 1 5027ccd5a2cSjsg #define INVALIDATE_ONLY_PDE_CACHES 2 5037ccd5a2cSjsg #define VM_L2_CNTL3 0x1408 5047ccd5a2cSjsg #define BANK_SELECT(x) ((x) << 0) 5057ccd5a2cSjsg #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 5067ccd5a2cSjsg #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 5077ccd5a2cSjsg #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 5087ccd5a2cSjsg #define VM_L2_STATUS 0x140C 5097ccd5a2cSjsg #define L2_BUSY (1 << 0) 5107ccd5a2cSjsg #define VM_CONTEXT0_CNTL 0x1410 5117ccd5a2cSjsg #define ENABLE_CONTEXT (1 << 0) 5127ccd5a2cSjsg #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 5137ccd5a2cSjsg #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 5147ccd5a2cSjsg #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 5157ccd5a2cSjsg #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 5167ccd5a2cSjsg #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 5177ccd5a2cSjsg #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 5187ccd5a2cSjsg #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 5197ccd5a2cSjsg #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 5207ccd5a2cSjsg #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 5217ccd5a2cSjsg #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 5227ccd5a2cSjsg #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 5237ccd5a2cSjsg #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 5247ccd5a2cSjsg #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 5257ccd5a2cSjsg #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) 5267ccd5a2cSjsg #define VM_CONTEXT1_CNTL 0x1414 5277ccd5a2cSjsg #define VM_CONTEXT0_CNTL2 0x1430 5287ccd5a2cSjsg #define VM_CONTEXT1_CNTL2 0x1434 5297ccd5a2cSjsg #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 5307ccd5a2cSjsg #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 5317ccd5a2cSjsg #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 5327ccd5a2cSjsg #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 5337ccd5a2cSjsg #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 5347ccd5a2cSjsg #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 5357ccd5a2cSjsg #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 5367ccd5a2cSjsg #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 5377ccd5a2cSjsg 5387ccd5a2cSjsg #define VM_INVALIDATE_REQUEST 0x1478 5397ccd5a2cSjsg #define VM_INVALIDATE_RESPONSE 0x147c 5407ccd5a2cSjsg 5417ccd5a2cSjsg #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 5427ccd5a2cSjsg #define PROTECTIONS_MASK (0xf << 0) 5437ccd5a2cSjsg #define PROTECTIONS_SHIFT 0 5447ccd5a2cSjsg /* bit 0: range 5457ccd5a2cSjsg * bit 1: pde0 5467ccd5a2cSjsg * bit 2: valid 5477ccd5a2cSjsg * bit 3: read 5487ccd5a2cSjsg * bit 4: write 5497ccd5a2cSjsg */ 5507ccd5a2cSjsg #define MEMORY_CLIENT_ID_MASK (0xff << 12) 5517ccd5a2cSjsg #define HAWAII_MEMORY_CLIENT_ID_MASK (0x1ff << 12) 5527ccd5a2cSjsg #define MEMORY_CLIENT_ID_SHIFT 12 5537ccd5a2cSjsg #define MEMORY_CLIENT_RW_MASK (1 << 24) 5547ccd5a2cSjsg #define MEMORY_CLIENT_RW_SHIFT 24 5557ccd5a2cSjsg #define FAULT_VMID_MASK (0xf << 25) 5567ccd5a2cSjsg #define FAULT_VMID_SHIFT 25 5577ccd5a2cSjsg 5587ccd5a2cSjsg #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4 5597ccd5a2cSjsg 5607ccd5a2cSjsg #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 5617ccd5a2cSjsg 5627ccd5a2cSjsg #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 5637ccd5a2cSjsg #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 5647ccd5a2cSjsg 5657ccd5a2cSjsg #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 5667ccd5a2cSjsg #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 5677ccd5a2cSjsg #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 5687ccd5a2cSjsg #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 5697ccd5a2cSjsg #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 5707ccd5a2cSjsg #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 5717ccd5a2cSjsg #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 5727ccd5a2cSjsg #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 5737ccd5a2cSjsg #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 5747ccd5a2cSjsg #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 5757ccd5a2cSjsg 5767ccd5a2cSjsg #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 5777ccd5a2cSjsg #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 5787ccd5a2cSjsg 5797ccd5a2cSjsg #define VM_L2_CG 0x15c0 5807ccd5a2cSjsg #define MC_CG_ENABLE (1 << 18) 5817ccd5a2cSjsg #define MC_LS_ENABLE (1 << 19) 5827ccd5a2cSjsg 5837ccd5a2cSjsg #define MC_SHARED_CHMAP 0x2004 5847ccd5a2cSjsg #define NOOFCHAN_SHIFT 12 5857ccd5a2cSjsg #define NOOFCHAN_MASK 0x0000f000 5867ccd5a2cSjsg #define MC_SHARED_CHREMAP 0x2008 5877ccd5a2cSjsg 5887ccd5a2cSjsg #define CHUB_CONTROL 0x1864 5897ccd5a2cSjsg #define BYPASS_VM (1 << 0) 5907ccd5a2cSjsg 5917ccd5a2cSjsg #define MC_VM_FB_LOCATION 0x2024 5927ccd5a2cSjsg #define MC_VM_AGP_TOP 0x2028 5937ccd5a2cSjsg #define MC_VM_AGP_BOT 0x202C 5947ccd5a2cSjsg #define MC_VM_AGP_BASE 0x2030 5957ccd5a2cSjsg #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 5967ccd5a2cSjsg #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 5977ccd5a2cSjsg #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 5987ccd5a2cSjsg 5997ccd5a2cSjsg #define MC_VM_MX_L1_TLB_CNTL 0x2064 6007ccd5a2cSjsg #define ENABLE_L1_TLB (1 << 0) 6017ccd5a2cSjsg #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 6027ccd5a2cSjsg #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 6037ccd5a2cSjsg #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 6047ccd5a2cSjsg #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 6057ccd5a2cSjsg #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 6067ccd5a2cSjsg #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 6077ccd5a2cSjsg #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 6087ccd5a2cSjsg #define MC_VM_FB_OFFSET 0x2068 6097ccd5a2cSjsg 6107ccd5a2cSjsg #define MC_SHARED_BLACKOUT_CNTL 0x20ac 6117ccd5a2cSjsg 6127ccd5a2cSjsg #define MC_HUB_MISC_HUB_CG 0x20b8 6137ccd5a2cSjsg #define MC_HUB_MISC_VM_CG 0x20bc 6147ccd5a2cSjsg 6157ccd5a2cSjsg #define MC_HUB_MISC_SIP_CG 0x20c0 6167ccd5a2cSjsg 6177ccd5a2cSjsg #define MC_XPB_CLK_GAT 0x2478 6187ccd5a2cSjsg 6197ccd5a2cSjsg #define MC_CITF_MISC_RD_CG 0x2648 6207ccd5a2cSjsg #define MC_CITF_MISC_WR_CG 0x264c 6217ccd5a2cSjsg #define MC_CITF_MISC_VM_CG 0x2650 6227ccd5a2cSjsg 6237ccd5a2cSjsg #define MC_ARB_RAMCFG 0x2760 6247ccd5a2cSjsg #define NOOFBANK_SHIFT 0 6257ccd5a2cSjsg #define NOOFBANK_MASK 0x00000003 6267ccd5a2cSjsg #define NOOFRANK_SHIFT 2 6277ccd5a2cSjsg #define NOOFRANK_MASK 0x00000004 6287ccd5a2cSjsg #define NOOFROWS_SHIFT 3 6297ccd5a2cSjsg #define NOOFROWS_MASK 0x00000038 6307ccd5a2cSjsg #define NOOFCOLS_SHIFT 6 6317ccd5a2cSjsg #define NOOFCOLS_MASK 0x000000C0 6327ccd5a2cSjsg #define CHANSIZE_SHIFT 8 6337ccd5a2cSjsg #define CHANSIZE_MASK 0x00000100 6347ccd5a2cSjsg #define NOOFGROUPS_SHIFT 12 6357ccd5a2cSjsg #define NOOFGROUPS_MASK 0x00001000 6367ccd5a2cSjsg 6377ccd5a2cSjsg #define MC_ARB_DRAM_TIMING 0x2774 6387ccd5a2cSjsg #define MC_ARB_DRAM_TIMING2 0x2778 6397ccd5a2cSjsg 6407ccd5a2cSjsg #define MC_ARB_BURST_TIME 0x2808 6417ccd5a2cSjsg #define STATE0(x) ((x) << 0) 6427ccd5a2cSjsg #define STATE0_MASK (0x1f << 0) 6437ccd5a2cSjsg #define STATE0_SHIFT 0 6447ccd5a2cSjsg #define STATE1(x) ((x) << 5) 6457ccd5a2cSjsg #define STATE1_MASK (0x1f << 5) 6467ccd5a2cSjsg #define STATE1_SHIFT 5 6477ccd5a2cSjsg #define STATE2(x) ((x) << 10) 6487ccd5a2cSjsg #define STATE2_MASK (0x1f << 10) 6497ccd5a2cSjsg #define STATE2_SHIFT 10 6507ccd5a2cSjsg #define STATE3(x) ((x) << 15) 6517ccd5a2cSjsg #define STATE3_MASK (0x1f << 15) 6527ccd5a2cSjsg #define STATE3_SHIFT 15 6537ccd5a2cSjsg 6547ccd5a2cSjsg #define MC_SEQ_RAS_TIMING 0x28a0 6557ccd5a2cSjsg #define MC_SEQ_CAS_TIMING 0x28a4 6567ccd5a2cSjsg #define MC_SEQ_MISC_TIMING 0x28a8 6577ccd5a2cSjsg #define MC_SEQ_MISC_TIMING2 0x28ac 6587ccd5a2cSjsg #define MC_SEQ_PMG_TIMING 0x28b0 6597ccd5a2cSjsg #define MC_SEQ_RD_CTL_D0 0x28b4 6607ccd5a2cSjsg #define MC_SEQ_RD_CTL_D1 0x28b8 6617ccd5a2cSjsg #define MC_SEQ_WR_CTL_D0 0x28bc 6627ccd5a2cSjsg #define MC_SEQ_WR_CTL_D1 0x28c0 6637ccd5a2cSjsg 6647ccd5a2cSjsg #define MC_SEQ_SUP_CNTL 0x28c8 6657ccd5a2cSjsg #define RUN_MASK (1 << 0) 6667ccd5a2cSjsg #define MC_SEQ_SUP_PGM 0x28cc 6677ccd5a2cSjsg #define MC_PMG_AUTO_CMD 0x28d0 6687ccd5a2cSjsg 6697ccd5a2cSjsg #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 6707ccd5a2cSjsg #define TRAIN_DONE_D0 (1 << 30) 6717ccd5a2cSjsg #define TRAIN_DONE_D1 (1 << 31) 6727ccd5a2cSjsg 6737ccd5a2cSjsg #define MC_IO_PAD_CNTL_D0 0x29d0 6747ccd5a2cSjsg #define MEM_FALL_OUT_CMD (1 << 8) 6757ccd5a2cSjsg 6767ccd5a2cSjsg #define MC_SEQ_MISC0 0x2a00 6777ccd5a2cSjsg #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 6787ccd5a2cSjsg #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 6797ccd5a2cSjsg #define MC_SEQ_MISC0_VEN_ID_VALUE 3 6807ccd5a2cSjsg #define MC_SEQ_MISC0_REV_ID_SHIFT 12 6817ccd5a2cSjsg #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 6827ccd5a2cSjsg #define MC_SEQ_MISC0_REV_ID_VALUE 1 6837ccd5a2cSjsg #define MC_SEQ_MISC0_GDDR5_SHIFT 28 6847ccd5a2cSjsg #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 6857ccd5a2cSjsg #define MC_SEQ_MISC0_GDDR5_VALUE 5 6867ccd5a2cSjsg #define MC_SEQ_MISC1 0x2a04 6877ccd5a2cSjsg #define MC_SEQ_RESERVE_M 0x2a08 6887ccd5a2cSjsg #define MC_PMG_CMD_EMRS 0x2a0c 6897ccd5a2cSjsg 6907ccd5a2cSjsg #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 6917ccd5a2cSjsg #define MC_SEQ_IO_DEBUG_DATA 0x2a48 6927ccd5a2cSjsg 6937ccd5a2cSjsg #define MC_SEQ_MISC5 0x2a54 6947ccd5a2cSjsg #define MC_SEQ_MISC6 0x2a58 6957ccd5a2cSjsg 6967ccd5a2cSjsg #define MC_SEQ_MISC7 0x2a64 6977ccd5a2cSjsg 6987ccd5a2cSjsg #define MC_SEQ_RAS_TIMING_LP 0x2a6c 6997ccd5a2cSjsg #define MC_SEQ_CAS_TIMING_LP 0x2a70 7007ccd5a2cSjsg #define MC_SEQ_MISC_TIMING_LP 0x2a74 7017ccd5a2cSjsg #define MC_SEQ_MISC_TIMING2_LP 0x2a78 7027ccd5a2cSjsg #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 7037ccd5a2cSjsg #define MC_SEQ_WR_CTL_D1_LP 0x2a80 7047ccd5a2cSjsg #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 7057ccd5a2cSjsg #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 7067ccd5a2cSjsg 7077ccd5a2cSjsg #define MC_PMG_CMD_MRS 0x2aac 7087ccd5a2cSjsg 7097ccd5a2cSjsg #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 7107ccd5a2cSjsg #define MC_SEQ_RD_CTL_D1_LP 0x2b20 7117ccd5a2cSjsg 7127ccd5a2cSjsg #define MC_PMG_CMD_MRS1 0x2b44 7137ccd5a2cSjsg #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 7147ccd5a2cSjsg #define MC_SEQ_PMG_TIMING_LP 0x2b4c 7157ccd5a2cSjsg 7167ccd5a2cSjsg #define MC_SEQ_WR_CTL_2 0x2b54 7177ccd5a2cSjsg #define MC_SEQ_WR_CTL_2_LP 0x2b58 7187ccd5a2cSjsg #define MC_PMG_CMD_MRS2 0x2b5c 7197ccd5a2cSjsg #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 7207ccd5a2cSjsg 7217ccd5a2cSjsg #define MCLK_PWRMGT_CNTL 0x2ba0 7227ccd5a2cSjsg # define DLL_SPEED(x) ((x) << 0) 7237ccd5a2cSjsg # define DLL_SPEED_MASK (0x1f << 0) 7247ccd5a2cSjsg # define DLL_READY (1 << 6) 7257ccd5a2cSjsg # define MC_INT_CNTL (1 << 7) 7267ccd5a2cSjsg # define MRDCK0_PDNB (1 << 8) 7277ccd5a2cSjsg # define MRDCK1_PDNB (1 << 9) 7287ccd5a2cSjsg # define MRDCK0_RESET (1 << 16) 7297ccd5a2cSjsg # define MRDCK1_RESET (1 << 17) 7307ccd5a2cSjsg # define DLL_READY_READ (1 << 24) 7317ccd5a2cSjsg #define DLL_CNTL 0x2ba4 7327ccd5a2cSjsg # define MRDCK0_BYPASS (1 << 24) 7337ccd5a2cSjsg # define MRDCK1_BYPASS (1 << 25) 7347ccd5a2cSjsg 7357ccd5a2cSjsg #define MPLL_FUNC_CNTL 0x2bb4 7367ccd5a2cSjsg #define BWCTRL(x) ((x) << 20) 7377ccd5a2cSjsg #define BWCTRL_MASK (0xff << 20) 7387ccd5a2cSjsg #define MPLL_FUNC_CNTL_1 0x2bb8 7397ccd5a2cSjsg #define VCO_MODE(x) ((x) << 0) 7407ccd5a2cSjsg #define VCO_MODE_MASK (3 << 0) 7417ccd5a2cSjsg #define CLKFRAC(x) ((x) << 4) 7427ccd5a2cSjsg #define CLKFRAC_MASK (0xfff << 4) 7437ccd5a2cSjsg #define CLKF(x) ((x) << 16) 7447ccd5a2cSjsg #define CLKF_MASK (0xfff << 16) 7457ccd5a2cSjsg #define MPLL_FUNC_CNTL_2 0x2bbc 7467ccd5a2cSjsg #define MPLL_AD_FUNC_CNTL 0x2bc0 7477ccd5a2cSjsg #define YCLK_POST_DIV(x) ((x) << 0) 7487ccd5a2cSjsg #define YCLK_POST_DIV_MASK (7 << 0) 7497ccd5a2cSjsg #define MPLL_DQ_FUNC_CNTL 0x2bc4 7507ccd5a2cSjsg #define YCLK_SEL(x) ((x) << 4) 7517ccd5a2cSjsg #define YCLK_SEL_MASK (1 << 4) 7527ccd5a2cSjsg 7537ccd5a2cSjsg #define MPLL_SS1 0x2bcc 7547ccd5a2cSjsg #define CLKV(x) ((x) << 0) 7557ccd5a2cSjsg #define CLKV_MASK (0x3ffffff << 0) 7567ccd5a2cSjsg #define MPLL_SS2 0x2bd0 7577ccd5a2cSjsg #define CLKS(x) ((x) << 0) 7587ccd5a2cSjsg #define CLKS_MASK (0xfff << 0) 7597ccd5a2cSjsg 7607ccd5a2cSjsg #define HDP_HOST_PATH_CNTL 0x2C00 7617ccd5a2cSjsg #define CLOCK_GATING_DIS (1 << 23) 7627ccd5a2cSjsg #define HDP_NONSURFACE_BASE 0x2C04 7637ccd5a2cSjsg #define HDP_NONSURFACE_INFO 0x2C08 7647ccd5a2cSjsg #define HDP_NONSURFACE_SIZE 0x2C0C 7657ccd5a2cSjsg 7667ccd5a2cSjsg #define HDP_ADDR_CONFIG 0x2F48 7677ccd5a2cSjsg #define HDP_MISC_CNTL 0x2F4C 7687ccd5a2cSjsg #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 7697ccd5a2cSjsg #define HDP_MEM_POWER_LS 0x2F50 7707ccd5a2cSjsg #define HDP_LS_ENABLE (1 << 0) 7717ccd5a2cSjsg 7727ccd5a2cSjsg #define ATC_MISC_CG 0x3350 7737ccd5a2cSjsg 7747ccd5a2cSjsg #define GMCON_RENG_EXECUTE 0x3508 7757ccd5a2cSjsg #define RENG_EXECUTE_ON_PWR_UP (1 << 0) 7767ccd5a2cSjsg #define GMCON_MISC 0x350c 7777ccd5a2cSjsg #define RENG_EXECUTE_ON_REG_UPDATE (1 << 11) 7787ccd5a2cSjsg #define STCTRL_STUTTER_EN (1 << 16) 7797ccd5a2cSjsg 7807ccd5a2cSjsg #define GMCON_PGFSM_CONFIG 0x3538 7817ccd5a2cSjsg #define GMCON_PGFSM_WRITE 0x353c 7827ccd5a2cSjsg #define GMCON_PGFSM_READ 0x3540 7837ccd5a2cSjsg #define GMCON_MISC3 0x3544 7847ccd5a2cSjsg 7857ccd5a2cSjsg #define MC_SEQ_CNTL_3 0x3600 7867ccd5a2cSjsg # define CAC_EN (1 << 31) 7877ccd5a2cSjsg #define MC_SEQ_G5PDX_CTRL 0x3604 7887ccd5a2cSjsg #define MC_SEQ_G5PDX_CTRL_LP 0x3608 7897ccd5a2cSjsg #define MC_SEQ_G5PDX_CMD0 0x360c 7907ccd5a2cSjsg #define MC_SEQ_G5PDX_CMD0_LP 0x3610 7917ccd5a2cSjsg #define MC_SEQ_G5PDX_CMD1 0x3614 7927ccd5a2cSjsg #define MC_SEQ_G5PDX_CMD1_LP 0x3618 7937ccd5a2cSjsg 7947ccd5a2cSjsg #define MC_SEQ_PMG_DVS_CTL 0x3628 7957ccd5a2cSjsg #define MC_SEQ_PMG_DVS_CTL_LP 0x362c 7967ccd5a2cSjsg #define MC_SEQ_PMG_DVS_CMD 0x3630 7977ccd5a2cSjsg #define MC_SEQ_PMG_DVS_CMD_LP 0x3634 7987ccd5a2cSjsg #define MC_SEQ_DLL_STBY 0x3638 7997ccd5a2cSjsg #define MC_SEQ_DLL_STBY_LP 0x363c 8007ccd5a2cSjsg 8017ccd5a2cSjsg #define IH_RB_CNTL 0x3e00 8027ccd5a2cSjsg # define IH_RB_ENABLE (1 << 0) 8037ccd5a2cSjsg # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 8047ccd5a2cSjsg # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 8057ccd5a2cSjsg # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 8067ccd5a2cSjsg # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 8077ccd5a2cSjsg # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 8087ccd5a2cSjsg # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 8097ccd5a2cSjsg #define IH_RB_BASE 0x3e04 8107ccd5a2cSjsg #define IH_RB_RPTR 0x3e08 8117ccd5a2cSjsg #define IH_RB_WPTR 0x3e0c 8127ccd5a2cSjsg # define RB_OVERFLOW (1 << 0) 8137ccd5a2cSjsg # define WPTR_OFFSET_MASK 0x3fffc 8147ccd5a2cSjsg #define IH_RB_WPTR_ADDR_HI 0x3e10 8157ccd5a2cSjsg #define IH_RB_WPTR_ADDR_LO 0x3e14 8167ccd5a2cSjsg #define IH_CNTL 0x3e18 8177ccd5a2cSjsg # define ENABLE_INTR (1 << 0) 8187ccd5a2cSjsg # define IH_MC_SWAP(x) ((x) << 1) 8197ccd5a2cSjsg # define IH_MC_SWAP_NONE 0 8207ccd5a2cSjsg # define IH_MC_SWAP_16BIT 1 8217ccd5a2cSjsg # define IH_MC_SWAP_32BIT 2 8227ccd5a2cSjsg # define IH_MC_SWAP_64BIT 3 8237ccd5a2cSjsg # define RPTR_REARM (1 << 4) 8247ccd5a2cSjsg # define MC_WRREQ_CREDIT(x) ((x) << 15) 8257ccd5a2cSjsg # define MC_WR_CLEAN_CNT(x) ((x) << 20) 8267ccd5a2cSjsg # define MC_VMID(x) ((x) << 25) 8277ccd5a2cSjsg 8287ccd5a2cSjsg #define BIF_LNCNT_RESET 0x5220 8297ccd5a2cSjsg # define RESET_LNCNT_EN (1 << 0) 8307ccd5a2cSjsg 8317ccd5a2cSjsg #define CONFIG_MEMSIZE 0x5428 8327ccd5a2cSjsg 8337ccd5a2cSjsg #define INTERRUPT_CNTL 0x5468 8347ccd5a2cSjsg # define IH_DUMMY_RD_OVERRIDE (1 << 0) 8357ccd5a2cSjsg # define IH_DUMMY_RD_EN (1 << 1) 8367ccd5a2cSjsg # define IH_REQ_NONSNOOP_EN (1 << 3) 8377ccd5a2cSjsg # define GEN_IH_INT_EN (1 << 8) 8387ccd5a2cSjsg #define INTERRUPT_CNTL2 0x546c 8397ccd5a2cSjsg 8407ccd5a2cSjsg #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 8417ccd5a2cSjsg 8427ccd5a2cSjsg #define BIF_FB_EN 0x5490 8437ccd5a2cSjsg #define FB_READ_EN (1 << 0) 8447ccd5a2cSjsg #define FB_WRITE_EN (1 << 1) 8457ccd5a2cSjsg 8467ccd5a2cSjsg #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 8477ccd5a2cSjsg 8487ccd5a2cSjsg #define GPU_HDP_FLUSH_REQ 0x54DC 8497ccd5a2cSjsg #define GPU_HDP_FLUSH_DONE 0x54E0 8507ccd5a2cSjsg #define CP0 (1 << 0) 8517ccd5a2cSjsg #define CP1 (1 << 1) 8527ccd5a2cSjsg #define CP2 (1 << 2) 8537ccd5a2cSjsg #define CP3 (1 << 3) 8547ccd5a2cSjsg #define CP4 (1 << 4) 8557ccd5a2cSjsg #define CP5 (1 << 5) 8567ccd5a2cSjsg #define CP6 (1 << 6) 8577ccd5a2cSjsg #define CP7 (1 << 7) 8587ccd5a2cSjsg #define CP8 (1 << 8) 8597ccd5a2cSjsg #define CP9 (1 << 9) 8607ccd5a2cSjsg #define SDMA0 (1 << 10) 8617ccd5a2cSjsg #define SDMA1 (1 << 11) 8627ccd5a2cSjsg 8637ccd5a2cSjsg /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */ 8647ccd5a2cSjsg #define LB_MEMORY_CTRL 0x6b04 8657ccd5a2cSjsg #define LB_MEMORY_SIZE(x) ((x) << 0) 8667ccd5a2cSjsg #define LB_MEMORY_CONFIG(x) ((x) << 20) 8677ccd5a2cSjsg 8687ccd5a2cSjsg #define DPG_WATERMARK_MASK_CONTROL 0x6cc8 8697ccd5a2cSjsg # define LATENCY_WATERMARK_MASK(x) ((x) << 8) 8707ccd5a2cSjsg #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 8717ccd5a2cSjsg # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 8727ccd5a2cSjsg # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 8737ccd5a2cSjsg 8747ccd5a2cSjsg /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */ 8757ccd5a2cSjsg #define LB_VLINE_STATUS 0x6b24 8767ccd5a2cSjsg # define VLINE_OCCURRED (1 << 0) 8777ccd5a2cSjsg # define VLINE_ACK (1 << 4) 8787ccd5a2cSjsg # define VLINE_STAT (1 << 12) 8797ccd5a2cSjsg # define VLINE_INTERRUPT (1 << 16) 8807ccd5a2cSjsg # define VLINE_INTERRUPT_TYPE (1 << 17) 8817ccd5a2cSjsg /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */ 8827ccd5a2cSjsg #define LB_VBLANK_STATUS 0x6b2c 8837ccd5a2cSjsg # define VBLANK_OCCURRED (1 << 0) 8847ccd5a2cSjsg # define VBLANK_ACK (1 << 4) 8857ccd5a2cSjsg # define VBLANK_STAT (1 << 12) 8867ccd5a2cSjsg # define VBLANK_INTERRUPT (1 << 16) 8877ccd5a2cSjsg # define VBLANK_INTERRUPT_TYPE (1 << 17) 8887ccd5a2cSjsg 8897ccd5a2cSjsg /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */ 8907ccd5a2cSjsg #define LB_INTERRUPT_MASK 0x6b20 8917ccd5a2cSjsg # define VBLANK_INTERRUPT_MASK (1 << 0) 8927ccd5a2cSjsg # define VLINE_INTERRUPT_MASK (1 << 4) 8937ccd5a2cSjsg # define VLINE2_INTERRUPT_MASK (1 << 8) 8947ccd5a2cSjsg 8957ccd5a2cSjsg #define DISP_INTERRUPT_STATUS 0x60f4 8967ccd5a2cSjsg # define LB_D1_VLINE_INTERRUPT (1 << 2) 8977ccd5a2cSjsg # define LB_D1_VBLANK_INTERRUPT (1 << 3) 8987ccd5a2cSjsg # define DC_HPD1_INTERRUPT (1 << 17) 8997ccd5a2cSjsg # define DC_HPD1_RX_INTERRUPT (1 << 18) 9007ccd5a2cSjsg # define DACA_AUTODETECT_INTERRUPT (1 << 22) 9017ccd5a2cSjsg # define DACB_AUTODETECT_INTERRUPT (1 << 23) 9027ccd5a2cSjsg # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 9037ccd5a2cSjsg # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 9047ccd5a2cSjsg #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 9057ccd5a2cSjsg # define LB_D2_VLINE_INTERRUPT (1 << 2) 9067ccd5a2cSjsg # define LB_D2_VBLANK_INTERRUPT (1 << 3) 9077ccd5a2cSjsg # define DC_HPD2_INTERRUPT (1 << 17) 9087ccd5a2cSjsg # define DC_HPD2_RX_INTERRUPT (1 << 18) 9097ccd5a2cSjsg # define DISP_TIMER_INTERRUPT (1 << 24) 9107ccd5a2cSjsg #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 9117ccd5a2cSjsg # define LB_D3_VLINE_INTERRUPT (1 << 2) 9127ccd5a2cSjsg # define LB_D3_VBLANK_INTERRUPT (1 << 3) 9137ccd5a2cSjsg # define DC_HPD3_INTERRUPT (1 << 17) 9147ccd5a2cSjsg # define DC_HPD3_RX_INTERRUPT (1 << 18) 9157ccd5a2cSjsg #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 9167ccd5a2cSjsg # define LB_D4_VLINE_INTERRUPT (1 << 2) 9177ccd5a2cSjsg # define LB_D4_VBLANK_INTERRUPT (1 << 3) 9187ccd5a2cSjsg # define DC_HPD4_INTERRUPT (1 << 17) 9197ccd5a2cSjsg # define DC_HPD4_RX_INTERRUPT (1 << 18) 9207ccd5a2cSjsg #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 9217ccd5a2cSjsg # define LB_D5_VLINE_INTERRUPT (1 << 2) 9227ccd5a2cSjsg # define LB_D5_VBLANK_INTERRUPT (1 << 3) 9237ccd5a2cSjsg # define DC_HPD5_INTERRUPT (1 << 17) 9247ccd5a2cSjsg # define DC_HPD5_RX_INTERRUPT (1 << 18) 9257ccd5a2cSjsg #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 9267ccd5a2cSjsg # define LB_D6_VLINE_INTERRUPT (1 << 2) 9277ccd5a2cSjsg # define LB_D6_VBLANK_INTERRUPT (1 << 3) 9287ccd5a2cSjsg # define DC_HPD6_INTERRUPT (1 << 17) 9297ccd5a2cSjsg # define DC_HPD6_RX_INTERRUPT (1 << 18) 9307ccd5a2cSjsg #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 9317ccd5a2cSjsg 9327ccd5a2cSjsg /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 9337ccd5a2cSjsg #define GRPH_INT_STATUS 0x6858 9347ccd5a2cSjsg # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 9357ccd5a2cSjsg # define GRPH_PFLIP_INT_CLEAR (1 << 8) 9367ccd5a2cSjsg /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 9377ccd5a2cSjsg #define GRPH_INT_CONTROL 0x685c 9387ccd5a2cSjsg # define GRPH_PFLIP_INT_MASK (1 << 0) 9397ccd5a2cSjsg # define GRPH_PFLIP_INT_TYPE (1 << 8) 9407ccd5a2cSjsg 9417ccd5a2cSjsg #define DAC_AUTODETECT_INT_CONTROL 0x67c8 9427ccd5a2cSjsg 9437ccd5a2cSjsg #define DC_HPD1_INT_STATUS 0x601c 9447ccd5a2cSjsg #define DC_HPD2_INT_STATUS 0x6028 9457ccd5a2cSjsg #define DC_HPD3_INT_STATUS 0x6034 9467ccd5a2cSjsg #define DC_HPD4_INT_STATUS 0x6040 9477ccd5a2cSjsg #define DC_HPD5_INT_STATUS 0x604c 9487ccd5a2cSjsg #define DC_HPD6_INT_STATUS 0x6058 9497ccd5a2cSjsg # define DC_HPDx_INT_STATUS (1 << 0) 9507ccd5a2cSjsg # define DC_HPDx_SENSE (1 << 1) 9517ccd5a2cSjsg # define DC_HPDx_SENSE_DELAYED (1 << 4) 9527ccd5a2cSjsg # define DC_HPDx_RX_INT_STATUS (1 << 8) 9537ccd5a2cSjsg 9547ccd5a2cSjsg #define DC_HPD1_INT_CONTROL 0x6020 9557ccd5a2cSjsg #define DC_HPD2_INT_CONTROL 0x602c 9567ccd5a2cSjsg #define DC_HPD3_INT_CONTROL 0x6038 9577ccd5a2cSjsg #define DC_HPD4_INT_CONTROL 0x6044 9587ccd5a2cSjsg #define DC_HPD5_INT_CONTROL 0x6050 9597ccd5a2cSjsg #define DC_HPD6_INT_CONTROL 0x605c 9607ccd5a2cSjsg # define DC_HPDx_INT_ACK (1 << 0) 9617ccd5a2cSjsg # define DC_HPDx_INT_POLARITY (1 << 8) 9627ccd5a2cSjsg # define DC_HPDx_INT_EN (1 << 16) 9637ccd5a2cSjsg # define DC_HPDx_RX_INT_ACK (1 << 20) 9647ccd5a2cSjsg # define DC_HPDx_RX_INT_EN (1 << 24) 9657ccd5a2cSjsg 9667ccd5a2cSjsg #define DC_HPD1_CONTROL 0x6024 9677ccd5a2cSjsg #define DC_HPD2_CONTROL 0x6030 9687ccd5a2cSjsg #define DC_HPD3_CONTROL 0x603c 9697ccd5a2cSjsg #define DC_HPD4_CONTROL 0x6048 9707ccd5a2cSjsg #define DC_HPD5_CONTROL 0x6054 9717ccd5a2cSjsg #define DC_HPD6_CONTROL 0x6060 9727ccd5a2cSjsg # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 9737ccd5a2cSjsg # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 9747ccd5a2cSjsg # define DC_HPDx_EN (1 << 28) 9757ccd5a2cSjsg 9767ccd5a2cSjsg #define DPG_PIPE_STUTTER_CONTROL 0x6cd4 9777ccd5a2cSjsg # define STUTTER_ENABLE (1 << 0) 9787ccd5a2cSjsg 9797ccd5a2cSjsg /* DCE8 FMT blocks */ 9807ccd5a2cSjsg #define FMT_DYNAMIC_EXP_CNTL 0x6fb4 9817ccd5a2cSjsg # define FMT_DYNAMIC_EXP_EN (1 << 0) 9827ccd5a2cSjsg # define FMT_DYNAMIC_EXP_MODE (1 << 4) 9837ccd5a2cSjsg /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */ 9847ccd5a2cSjsg #define FMT_CONTROL 0x6fb8 9857ccd5a2cSjsg # define FMT_PIXEL_ENCODING (1 << 16) 9867ccd5a2cSjsg /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ 9877ccd5a2cSjsg #define FMT_BIT_DEPTH_CONTROL 0x6fc8 9887ccd5a2cSjsg # define FMT_TRUNCATE_EN (1 << 0) 9897ccd5a2cSjsg # define FMT_TRUNCATE_MODE (1 << 1) 9907ccd5a2cSjsg # define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 9917ccd5a2cSjsg # define FMT_SPATIAL_DITHER_EN (1 << 8) 9927ccd5a2cSjsg # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) 9937ccd5a2cSjsg # define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 9947ccd5a2cSjsg # define FMT_FRAME_RANDOM_ENABLE (1 << 13) 9957ccd5a2cSjsg # define FMT_RGB_RANDOM_ENABLE (1 << 14) 9967ccd5a2cSjsg # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) 9977ccd5a2cSjsg # define FMT_TEMPORAL_DITHER_EN (1 << 16) 9987ccd5a2cSjsg # define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 9997ccd5a2cSjsg # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) 10007ccd5a2cSjsg # define FMT_TEMPORAL_LEVEL (1 << 24) 10017ccd5a2cSjsg # define FMT_TEMPORAL_DITHER_RESET (1 << 25) 10027ccd5a2cSjsg # define FMT_25FRC_SEL(x) ((x) << 26) 10037ccd5a2cSjsg # define FMT_50FRC_SEL(x) ((x) << 28) 10047ccd5a2cSjsg # define FMT_75FRC_SEL(x) ((x) << 30) 10057ccd5a2cSjsg #define FMT_CLAMP_CONTROL 0x6fe4 10067ccd5a2cSjsg # define FMT_CLAMP_DATA_EN (1 << 0) 10077ccd5a2cSjsg # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16) 10087ccd5a2cSjsg # define FMT_CLAMP_6BPC 0 10097ccd5a2cSjsg # define FMT_CLAMP_8BPC 1 10107ccd5a2cSjsg # define FMT_CLAMP_10BPC 2 10117ccd5a2cSjsg 10127ccd5a2cSjsg #define GRBM_CNTL 0x8000 10137ccd5a2cSjsg #define GRBM_READ_TIMEOUT(x) ((x) << 0) 10147ccd5a2cSjsg 10157ccd5a2cSjsg #define GRBM_STATUS2 0x8008 10167ccd5a2cSjsg #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F 10177ccd5a2cSjsg #define ME0PIPE1_CF_RQ_PENDING (1 << 4) 10187ccd5a2cSjsg #define ME0PIPE1_PF_RQ_PENDING (1 << 5) 10197ccd5a2cSjsg #define ME1PIPE0_RQ_PENDING (1 << 6) 10207ccd5a2cSjsg #define ME1PIPE1_RQ_PENDING (1 << 7) 10217ccd5a2cSjsg #define ME1PIPE2_RQ_PENDING (1 << 8) 10227ccd5a2cSjsg #define ME1PIPE3_RQ_PENDING (1 << 9) 10237ccd5a2cSjsg #define ME2PIPE0_RQ_PENDING (1 << 10) 10247ccd5a2cSjsg #define ME2PIPE1_RQ_PENDING (1 << 11) 10257ccd5a2cSjsg #define ME2PIPE2_RQ_PENDING (1 << 12) 10267ccd5a2cSjsg #define ME2PIPE3_RQ_PENDING (1 << 13) 10277ccd5a2cSjsg #define RLC_RQ_PENDING (1 << 14) 10287ccd5a2cSjsg #define RLC_BUSY (1 << 24) 10297ccd5a2cSjsg #define TC_BUSY (1 << 25) 10307ccd5a2cSjsg #define CPF_BUSY (1 << 28) 10317ccd5a2cSjsg #define CPC_BUSY (1 << 29) 10327ccd5a2cSjsg #define CPG_BUSY (1 << 30) 10337ccd5a2cSjsg 10347ccd5a2cSjsg #define GRBM_STATUS 0x8010 10357ccd5a2cSjsg #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F 10367ccd5a2cSjsg #define SRBM_RQ_PENDING (1 << 5) 10377ccd5a2cSjsg #define ME0PIPE0_CF_RQ_PENDING (1 << 7) 10387ccd5a2cSjsg #define ME0PIPE0_PF_RQ_PENDING (1 << 8) 10397ccd5a2cSjsg #define GDS_DMA_RQ_PENDING (1 << 9) 10407ccd5a2cSjsg #define DB_CLEAN (1 << 12) 10417ccd5a2cSjsg #define CB_CLEAN (1 << 13) 10427ccd5a2cSjsg #define TA_BUSY (1 << 14) 10437ccd5a2cSjsg #define GDS_BUSY (1 << 15) 10447ccd5a2cSjsg #define WD_BUSY_NO_DMA (1 << 16) 10457ccd5a2cSjsg #define VGT_BUSY (1 << 17) 10467ccd5a2cSjsg #define IA_BUSY_NO_DMA (1 << 18) 10477ccd5a2cSjsg #define IA_BUSY (1 << 19) 10487ccd5a2cSjsg #define SX_BUSY (1 << 20) 10497ccd5a2cSjsg #define WD_BUSY (1 << 21) 10507ccd5a2cSjsg #define SPI_BUSY (1 << 22) 10517ccd5a2cSjsg #define BCI_BUSY (1 << 23) 10527ccd5a2cSjsg #define SC_BUSY (1 << 24) 10537ccd5a2cSjsg #define PA_BUSY (1 << 25) 10547ccd5a2cSjsg #define DB_BUSY (1 << 26) 10557ccd5a2cSjsg #define CP_COHERENCY_BUSY (1 << 28) 10567ccd5a2cSjsg #define CP_BUSY (1 << 29) 10577ccd5a2cSjsg #define CB_BUSY (1 << 30) 10587ccd5a2cSjsg #define GUI_ACTIVE (1 << 31) 10597ccd5a2cSjsg #define GRBM_STATUS_SE0 0x8014 10607ccd5a2cSjsg #define GRBM_STATUS_SE1 0x8018 10617ccd5a2cSjsg #define GRBM_STATUS_SE2 0x8038 10627ccd5a2cSjsg #define GRBM_STATUS_SE3 0x803C 10637ccd5a2cSjsg #define SE_DB_CLEAN (1 << 1) 10647ccd5a2cSjsg #define SE_CB_CLEAN (1 << 2) 10657ccd5a2cSjsg #define SE_BCI_BUSY (1 << 22) 10667ccd5a2cSjsg #define SE_VGT_BUSY (1 << 23) 10677ccd5a2cSjsg #define SE_PA_BUSY (1 << 24) 10687ccd5a2cSjsg #define SE_TA_BUSY (1 << 25) 10697ccd5a2cSjsg #define SE_SX_BUSY (1 << 26) 10707ccd5a2cSjsg #define SE_SPI_BUSY (1 << 27) 10717ccd5a2cSjsg #define SE_SC_BUSY (1 << 29) 10727ccd5a2cSjsg #define SE_DB_BUSY (1 << 30) 10737ccd5a2cSjsg #define SE_CB_BUSY (1 << 31) 10747ccd5a2cSjsg 10757ccd5a2cSjsg #define GRBM_SOFT_RESET 0x8020 10767ccd5a2cSjsg #define SOFT_RESET_CP (1 << 0) /* All CP blocks */ 10777ccd5a2cSjsg #define SOFT_RESET_RLC (1 << 2) /* RLC */ 10787ccd5a2cSjsg #define SOFT_RESET_GFX (1 << 16) /* GFX */ 10797ccd5a2cSjsg #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */ 10807ccd5a2cSjsg #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */ 10817ccd5a2cSjsg #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */ 10827ccd5a2cSjsg 10837ccd5a2cSjsg #define GRBM_INT_CNTL 0x8060 10847ccd5a2cSjsg # define RDERR_INT_ENABLE (1 << 0) 10857ccd5a2cSjsg # define GUI_IDLE_INT_ENABLE (1 << 19) 10867ccd5a2cSjsg 10877ccd5a2cSjsg #define CP_CPC_STATUS 0x8210 10887ccd5a2cSjsg #define CP_CPC_BUSY_STAT 0x8214 10897ccd5a2cSjsg #define CP_CPC_STALLED_STAT1 0x8218 10907ccd5a2cSjsg #define CP_CPF_STATUS 0x821c 10917ccd5a2cSjsg #define CP_CPF_BUSY_STAT 0x8220 10927ccd5a2cSjsg #define CP_CPF_STALLED_STAT1 0x8224 10937ccd5a2cSjsg 10947ccd5a2cSjsg #define CP_MEC_CNTL 0x8234 10957ccd5a2cSjsg #define MEC_ME2_HALT (1 << 28) 10967ccd5a2cSjsg #define MEC_ME1_HALT (1 << 30) 10977ccd5a2cSjsg 10987ccd5a2cSjsg #define CP_MEC_CNTL 0x8234 10997ccd5a2cSjsg #define MEC_ME2_HALT (1 << 28) 11007ccd5a2cSjsg #define MEC_ME1_HALT (1 << 30) 11017ccd5a2cSjsg 11027ccd5a2cSjsg #define CP_STALLED_STAT3 0x8670 11037ccd5a2cSjsg #define CP_STALLED_STAT1 0x8674 11047ccd5a2cSjsg #define CP_STALLED_STAT2 0x8678 11057ccd5a2cSjsg 11067ccd5a2cSjsg #define CP_STAT 0x8680 11077ccd5a2cSjsg 11087ccd5a2cSjsg #define CP_ME_CNTL 0x86D8 11097ccd5a2cSjsg #define CP_CE_HALT (1 << 24) 11107ccd5a2cSjsg #define CP_PFP_HALT (1 << 26) 11117ccd5a2cSjsg #define CP_ME_HALT (1 << 28) 11127ccd5a2cSjsg 11137ccd5a2cSjsg #define CP_RB0_RPTR 0x8700 11147ccd5a2cSjsg #define CP_RB_WPTR_DELAY 0x8704 11157ccd5a2cSjsg #define CP_RB_WPTR_POLL_CNTL 0x8708 11167ccd5a2cSjsg #define IDLE_POLL_COUNT(x) ((x) << 16) 11177ccd5a2cSjsg #define IDLE_POLL_COUNT_MASK (0xffff << 16) 11187ccd5a2cSjsg 11197ccd5a2cSjsg #define CP_MEQ_THRESHOLDS 0x8764 11207ccd5a2cSjsg #define MEQ1_START(x) ((x) << 0) 11217ccd5a2cSjsg #define MEQ2_START(x) ((x) << 8) 11227ccd5a2cSjsg 11237ccd5a2cSjsg #define VGT_VTX_VECT_EJECT_REG 0x88B0 11247ccd5a2cSjsg 11257ccd5a2cSjsg #define VGT_CACHE_INVALIDATION 0x88C4 11267ccd5a2cSjsg #define CACHE_INVALIDATION(x) ((x) << 0) 11277ccd5a2cSjsg #define VC_ONLY 0 11287ccd5a2cSjsg #define TC_ONLY 1 11297ccd5a2cSjsg #define VC_AND_TC 2 11307ccd5a2cSjsg #define AUTO_INVLD_EN(x) ((x) << 6) 11317ccd5a2cSjsg #define NO_AUTO 0 11327ccd5a2cSjsg #define ES_AUTO 1 11337ccd5a2cSjsg #define GS_AUTO 2 11347ccd5a2cSjsg #define ES_AND_GS_AUTO 3 11357ccd5a2cSjsg 11367ccd5a2cSjsg #define VGT_GS_VERTEX_REUSE 0x88D4 11377ccd5a2cSjsg 11387ccd5a2cSjsg #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 11397ccd5a2cSjsg #define INACTIVE_CUS_MASK 0xFFFF0000 11407ccd5a2cSjsg #define INACTIVE_CUS_SHIFT 16 11417ccd5a2cSjsg #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 11427ccd5a2cSjsg 11437ccd5a2cSjsg #define PA_CL_ENHANCE 0x8A14 11447ccd5a2cSjsg #define CLIP_VTX_REORDER_ENA (1 << 0) 11457ccd5a2cSjsg #define NUM_CLIP_SEQ(x) ((x) << 1) 11467ccd5a2cSjsg 11477ccd5a2cSjsg #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 11487ccd5a2cSjsg #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 11497ccd5a2cSjsg #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 11507ccd5a2cSjsg 11517ccd5a2cSjsg #define PA_SC_FIFO_SIZE 0x8BCC 11527ccd5a2cSjsg #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 11537ccd5a2cSjsg #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 11547ccd5a2cSjsg #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 11557ccd5a2cSjsg #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 11567ccd5a2cSjsg 11577ccd5a2cSjsg #define PA_SC_ENHANCE 0x8BF0 11587ccd5a2cSjsg #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) 11597ccd5a2cSjsg #define DISABLE_PA_SC_GUIDANCE (1 << 13) 11607ccd5a2cSjsg 11617ccd5a2cSjsg #define SQ_CONFIG 0x8C00 11627ccd5a2cSjsg 11637ccd5a2cSjsg #define SH_MEM_BASES 0x8C28 11647ccd5a2cSjsg /* if PTR32, these are the bases for scratch and lds */ 11657ccd5a2cSjsg #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 11667ccd5a2cSjsg #define SHARED_BASE(x) ((x) << 16) /* LDS */ 11677ccd5a2cSjsg #define SH_MEM_APE1_BASE 0x8C2C 11687ccd5a2cSjsg /* if PTR32, this is the base location of GPUVM */ 11697ccd5a2cSjsg #define SH_MEM_APE1_LIMIT 0x8C30 11707ccd5a2cSjsg /* if PTR32, this is the upper limit of GPUVM */ 11717ccd5a2cSjsg #define SH_MEM_CONFIG 0x8C34 11727ccd5a2cSjsg #define PTR32 (1 << 0) 11737ccd5a2cSjsg #define ALIGNMENT_MODE(x) ((x) << 2) 11747ccd5a2cSjsg #define SH_MEM_ALIGNMENT_MODE_DWORD 0 11757ccd5a2cSjsg #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 11767ccd5a2cSjsg #define SH_MEM_ALIGNMENT_MODE_STRICT 2 11777ccd5a2cSjsg #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 11787ccd5a2cSjsg #define DEFAULT_MTYPE(x) ((x) << 4) 11797ccd5a2cSjsg #define APE1_MTYPE(x) ((x) << 7) 11807ccd5a2cSjsg /* valid for both DEFAULT_MTYPE and APE1_MTYPE */ 11817ccd5a2cSjsg #define MTYPE_CACHED 0 11827ccd5a2cSjsg #define MTYPE_NONCACHED 3 11837ccd5a2cSjsg 11847ccd5a2cSjsg #define SX_DEBUG_1 0x9060 11857ccd5a2cSjsg 11867ccd5a2cSjsg #define SPI_CONFIG_CNTL 0x9100 11877ccd5a2cSjsg 11887ccd5a2cSjsg #define SPI_CONFIG_CNTL_1 0x913C 11897ccd5a2cSjsg #define VTX_DONE_DELAY(x) ((x) << 0) 11907ccd5a2cSjsg #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 11917ccd5a2cSjsg 11927ccd5a2cSjsg #define TA_CNTL_AUX 0x9508 11937ccd5a2cSjsg 11947ccd5a2cSjsg #define DB_DEBUG 0x9830 11957ccd5a2cSjsg #define DB_DEBUG2 0x9834 11967ccd5a2cSjsg #define DB_DEBUG3 0x9838 11977ccd5a2cSjsg 11987ccd5a2cSjsg #define CC_RB_BACKEND_DISABLE 0x98F4 11997ccd5a2cSjsg #define BACKEND_DISABLE(x) ((x) << 16) 12007ccd5a2cSjsg #define GB_ADDR_CONFIG 0x98F8 12017ccd5a2cSjsg #define NUM_PIPES(x) ((x) << 0) 12027ccd5a2cSjsg #define NUM_PIPES_MASK 0x00000007 12037ccd5a2cSjsg #define NUM_PIPES_SHIFT 0 12047ccd5a2cSjsg #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 12057ccd5a2cSjsg #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 12067ccd5a2cSjsg #define PIPE_INTERLEAVE_SIZE_SHIFT 4 12077ccd5a2cSjsg #define NUM_SHADER_ENGINES(x) ((x) << 12) 12087ccd5a2cSjsg #define NUM_SHADER_ENGINES_MASK 0x00003000 12097ccd5a2cSjsg #define NUM_SHADER_ENGINES_SHIFT 12 12107ccd5a2cSjsg #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 12117ccd5a2cSjsg #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 12127ccd5a2cSjsg #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 12137ccd5a2cSjsg #define ROW_SIZE(x) ((x) << 28) 12147ccd5a2cSjsg #define ROW_SIZE_MASK 0x30000000 12157ccd5a2cSjsg #define ROW_SIZE_SHIFT 28 12167ccd5a2cSjsg 12177ccd5a2cSjsg #define GB_TILE_MODE0 0x9910 12187ccd5a2cSjsg # define ARRAY_MODE(x) ((x) << 2) 12197ccd5a2cSjsg # define ARRAY_LINEAR_GENERAL 0 12207ccd5a2cSjsg # define ARRAY_LINEAR_ALIGNED 1 12217ccd5a2cSjsg # define ARRAY_1D_TILED_THIN1 2 12227ccd5a2cSjsg # define ARRAY_2D_TILED_THIN1 4 12237ccd5a2cSjsg # define ARRAY_PRT_TILED_THIN1 5 12247ccd5a2cSjsg # define ARRAY_PRT_2D_TILED_THIN1 6 12257ccd5a2cSjsg # define PIPE_CONFIG(x) ((x) << 6) 12267ccd5a2cSjsg # define ADDR_SURF_P2 0 12277ccd5a2cSjsg # define ADDR_SURF_P4_8x16 4 12287ccd5a2cSjsg # define ADDR_SURF_P4_16x16 5 12297ccd5a2cSjsg # define ADDR_SURF_P4_16x32 6 12307ccd5a2cSjsg # define ADDR_SURF_P4_32x32 7 12317ccd5a2cSjsg # define ADDR_SURF_P8_16x16_8x16 8 12327ccd5a2cSjsg # define ADDR_SURF_P8_16x32_8x16 9 12337ccd5a2cSjsg # define ADDR_SURF_P8_32x32_8x16 10 12347ccd5a2cSjsg # define ADDR_SURF_P8_16x32_16x16 11 12357ccd5a2cSjsg # define ADDR_SURF_P8_32x32_16x16 12 12367ccd5a2cSjsg # define ADDR_SURF_P8_32x32_16x32 13 12377ccd5a2cSjsg # define ADDR_SURF_P8_32x64_32x32 14 12387ccd5a2cSjsg # define ADDR_SURF_P16_32x32_8x16 16 12397ccd5a2cSjsg # define ADDR_SURF_P16_32x32_16x16 17 12407ccd5a2cSjsg # define TILE_SPLIT(x) ((x) << 11) 12417ccd5a2cSjsg # define ADDR_SURF_TILE_SPLIT_64B 0 12427ccd5a2cSjsg # define ADDR_SURF_TILE_SPLIT_128B 1 12437ccd5a2cSjsg # define ADDR_SURF_TILE_SPLIT_256B 2 12447ccd5a2cSjsg # define ADDR_SURF_TILE_SPLIT_512B 3 12457ccd5a2cSjsg # define ADDR_SURF_TILE_SPLIT_1KB 4 12467ccd5a2cSjsg # define ADDR_SURF_TILE_SPLIT_2KB 5 12477ccd5a2cSjsg # define ADDR_SURF_TILE_SPLIT_4KB 6 12487ccd5a2cSjsg # define MICRO_TILE_MODE_NEW(x) ((x) << 22) 12497ccd5a2cSjsg # define ADDR_SURF_DISPLAY_MICRO_TILING 0 12507ccd5a2cSjsg # define ADDR_SURF_THIN_MICRO_TILING 1 12517ccd5a2cSjsg # define ADDR_SURF_DEPTH_MICRO_TILING 2 12527ccd5a2cSjsg # define ADDR_SURF_ROTATED_MICRO_TILING 3 12537ccd5a2cSjsg # define SAMPLE_SPLIT(x) ((x) << 25) 12547ccd5a2cSjsg # define ADDR_SURF_SAMPLE_SPLIT_1 0 12557ccd5a2cSjsg # define ADDR_SURF_SAMPLE_SPLIT_2 1 12567ccd5a2cSjsg # define ADDR_SURF_SAMPLE_SPLIT_4 2 12577ccd5a2cSjsg # define ADDR_SURF_SAMPLE_SPLIT_8 3 12587ccd5a2cSjsg 12597ccd5a2cSjsg #define GB_MACROTILE_MODE0 0x9990 12607ccd5a2cSjsg # define BANK_WIDTH(x) ((x) << 0) 12617ccd5a2cSjsg # define ADDR_SURF_BANK_WIDTH_1 0 12627ccd5a2cSjsg # define ADDR_SURF_BANK_WIDTH_2 1 12637ccd5a2cSjsg # define ADDR_SURF_BANK_WIDTH_4 2 12647ccd5a2cSjsg # define ADDR_SURF_BANK_WIDTH_8 3 12657ccd5a2cSjsg # define BANK_HEIGHT(x) ((x) << 2) 12667ccd5a2cSjsg # define ADDR_SURF_BANK_HEIGHT_1 0 12677ccd5a2cSjsg # define ADDR_SURF_BANK_HEIGHT_2 1 12687ccd5a2cSjsg # define ADDR_SURF_BANK_HEIGHT_4 2 12697ccd5a2cSjsg # define ADDR_SURF_BANK_HEIGHT_8 3 12707ccd5a2cSjsg # define MACRO_TILE_ASPECT(x) ((x) << 4) 12717ccd5a2cSjsg # define ADDR_SURF_MACRO_ASPECT_1 0 12727ccd5a2cSjsg # define ADDR_SURF_MACRO_ASPECT_2 1 12737ccd5a2cSjsg # define ADDR_SURF_MACRO_ASPECT_4 2 12747ccd5a2cSjsg # define ADDR_SURF_MACRO_ASPECT_8 3 12757ccd5a2cSjsg # define NUM_BANKS(x) ((x) << 6) 12767ccd5a2cSjsg # define ADDR_SURF_2_BANK 0 12777ccd5a2cSjsg # define ADDR_SURF_4_BANK 1 12787ccd5a2cSjsg # define ADDR_SURF_8_BANK 2 12797ccd5a2cSjsg # define ADDR_SURF_16_BANK 3 12807ccd5a2cSjsg 12817ccd5a2cSjsg #define CB_HW_CONTROL 0x9A10 12827ccd5a2cSjsg 12837ccd5a2cSjsg #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 12847ccd5a2cSjsg #define BACKEND_DISABLE_MASK 0x00FF0000 12857ccd5a2cSjsg #define BACKEND_DISABLE_SHIFT 16 12867ccd5a2cSjsg 12877ccd5a2cSjsg #define TCP_CHAN_STEER_LO 0xac0c 12887ccd5a2cSjsg #define TCP_CHAN_STEER_HI 0xac10 12897ccd5a2cSjsg 12907ccd5a2cSjsg #define TC_CFG_L1_LOAD_POLICY0 0xAC68 12917ccd5a2cSjsg #define TC_CFG_L1_LOAD_POLICY1 0xAC6C 12927ccd5a2cSjsg #define TC_CFG_L1_STORE_POLICY 0xAC70 12937ccd5a2cSjsg #define TC_CFG_L2_LOAD_POLICY0 0xAC74 12947ccd5a2cSjsg #define TC_CFG_L2_LOAD_POLICY1 0xAC78 12957ccd5a2cSjsg #define TC_CFG_L2_STORE_POLICY0 0xAC7C 12967ccd5a2cSjsg #define TC_CFG_L2_STORE_POLICY1 0xAC80 12977ccd5a2cSjsg #define TC_CFG_L2_ATOMIC_POLICY 0xAC84 12987ccd5a2cSjsg #define TC_CFG_L1_VOLATILE 0xAC88 12997ccd5a2cSjsg #define TC_CFG_L2_VOLATILE 0xAC8C 13007ccd5a2cSjsg 13017ccd5a2cSjsg #define CP_RB0_BASE 0xC100 13027ccd5a2cSjsg #define CP_RB0_CNTL 0xC104 13037ccd5a2cSjsg #define RB_BUFSZ(x) ((x) << 0) 13047ccd5a2cSjsg #define RB_BLKSZ(x) ((x) << 8) 13057ccd5a2cSjsg #define BUF_SWAP_32BIT (2 << 16) 13067ccd5a2cSjsg #define RB_NO_UPDATE (1 << 27) 13077ccd5a2cSjsg #define RB_RPTR_WR_ENA (1 << 31) 13087ccd5a2cSjsg 13097ccd5a2cSjsg #define CP_RB0_RPTR_ADDR 0xC10C 13107ccd5a2cSjsg #define RB_RPTR_SWAP_32BIT (2 << 0) 13117ccd5a2cSjsg #define CP_RB0_RPTR_ADDR_HI 0xC110 13127ccd5a2cSjsg #define CP_RB0_WPTR 0xC114 13137ccd5a2cSjsg 13147ccd5a2cSjsg #define CP_DEVICE_ID 0xC12C 13157ccd5a2cSjsg #define CP_ENDIAN_SWAP 0xC140 13167ccd5a2cSjsg #define CP_RB_VMID 0xC144 13177ccd5a2cSjsg 13187ccd5a2cSjsg #define CP_PFP_UCODE_ADDR 0xC150 13197ccd5a2cSjsg #define CP_PFP_UCODE_DATA 0xC154 13207ccd5a2cSjsg #define CP_ME_RAM_RADDR 0xC158 13217ccd5a2cSjsg #define CP_ME_RAM_WADDR 0xC15C 13227ccd5a2cSjsg #define CP_ME_RAM_DATA 0xC160 13237ccd5a2cSjsg 13247ccd5a2cSjsg #define CP_CE_UCODE_ADDR 0xC168 13257ccd5a2cSjsg #define CP_CE_UCODE_DATA 0xC16C 13267ccd5a2cSjsg #define CP_MEC_ME1_UCODE_ADDR 0xC170 13277ccd5a2cSjsg #define CP_MEC_ME1_UCODE_DATA 0xC174 13287ccd5a2cSjsg #define CP_MEC_ME2_UCODE_ADDR 0xC178 13297ccd5a2cSjsg #define CP_MEC_ME2_UCODE_DATA 0xC17C 13307ccd5a2cSjsg 13317ccd5a2cSjsg #define CP_INT_CNTL_RING0 0xC1A8 13327ccd5a2cSjsg # define CNTX_BUSY_INT_ENABLE (1 << 19) 13337ccd5a2cSjsg # define CNTX_EMPTY_INT_ENABLE (1 << 20) 13347ccd5a2cSjsg # define PRIV_INSTR_INT_ENABLE (1 << 22) 13357ccd5a2cSjsg # define PRIV_REG_INT_ENABLE (1 << 23) 13367ccd5a2cSjsg # define OPCODE_ERROR_INT_ENABLE (1 << 24) 13377ccd5a2cSjsg # define TIME_STAMP_INT_ENABLE (1 << 26) 13387ccd5a2cSjsg # define CP_RINGID2_INT_ENABLE (1 << 29) 13397ccd5a2cSjsg # define CP_RINGID1_INT_ENABLE (1 << 30) 13407ccd5a2cSjsg # define CP_RINGID0_INT_ENABLE (1 << 31) 13417ccd5a2cSjsg 13427ccd5a2cSjsg #define CP_INT_STATUS_RING0 0xC1B4 13437ccd5a2cSjsg # define PRIV_INSTR_INT_STAT (1 << 22) 13447ccd5a2cSjsg # define PRIV_REG_INT_STAT (1 << 23) 13457ccd5a2cSjsg # define TIME_STAMP_INT_STAT (1 << 26) 13467ccd5a2cSjsg # define CP_RINGID2_INT_STAT (1 << 29) 13477ccd5a2cSjsg # define CP_RINGID1_INT_STAT (1 << 30) 13487ccd5a2cSjsg # define CP_RINGID0_INT_STAT (1 << 31) 13497ccd5a2cSjsg 13507ccd5a2cSjsg #define CP_MEM_SLP_CNTL 0xC1E4 13517ccd5a2cSjsg # define CP_MEM_LS_EN (1 << 0) 13527ccd5a2cSjsg 13537ccd5a2cSjsg #define CP_CPF_DEBUG 0xC200 13547ccd5a2cSjsg 13557ccd5a2cSjsg #define CP_PQ_WPTR_POLL_CNTL 0xC20C 13567ccd5a2cSjsg #define WPTR_POLL_EN (1 << 31) 13577ccd5a2cSjsg 13587ccd5a2cSjsg #define CP_ME1_PIPE0_INT_CNTL 0xC214 13597ccd5a2cSjsg #define CP_ME1_PIPE1_INT_CNTL 0xC218 13607ccd5a2cSjsg #define CP_ME1_PIPE2_INT_CNTL 0xC21C 13617ccd5a2cSjsg #define CP_ME1_PIPE3_INT_CNTL 0xC220 13627ccd5a2cSjsg #define CP_ME2_PIPE0_INT_CNTL 0xC224 13637ccd5a2cSjsg #define CP_ME2_PIPE1_INT_CNTL 0xC228 13647ccd5a2cSjsg #define CP_ME2_PIPE2_INT_CNTL 0xC22C 13657ccd5a2cSjsg #define CP_ME2_PIPE3_INT_CNTL 0xC230 13667ccd5a2cSjsg # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13) 13677ccd5a2cSjsg # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17) 13687ccd5a2cSjsg # define PRIV_REG_INT_ENABLE (1 << 23) 13697ccd5a2cSjsg # define TIME_STAMP_INT_ENABLE (1 << 26) 13707ccd5a2cSjsg # define GENERIC2_INT_ENABLE (1 << 29) 13717ccd5a2cSjsg # define GENERIC1_INT_ENABLE (1 << 30) 13727ccd5a2cSjsg # define GENERIC0_INT_ENABLE (1 << 31) 13737ccd5a2cSjsg #define CP_ME1_PIPE0_INT_STATUS 0xC214 13747ccd5a2cSjsg #define CP_ME1_PIPE1_INT_STATUS 0xC218 13757ccd5a2cSjsg #define CP_ME1_PIPE2_INT_STATUS 0xC21C 13767ccd5a2cSjsg #define CP_ME1_PIPE3_INT_STATUS 0xC220 13777ccd5a2cSjsg #define CP_ME2_PIPE0_INT_STATUS 0xC224 13787ccd5a2cSjsg #define CP_ME2_PIPE1_INT_STATUS 0xC228 13797ccd5a2cSjsg #define CP_ME2_PIPE2_INT_STATUS 0xC22C 13807ccd5a2cSjsg #define CP_ME2_PIPE3_INT_STATUS 0xC230 13817ccd5a2cSjsg # define DEQUEUE_REQUEST_INT_STATUS (1 << 13) 13827ccd5a2cSjsg # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17) 13837ccd5a2cSjsg # define PRIV_REG_INT_STATUS (1 << 23) 13847ccd5a2cSjsg # define TIME_STAMP_INT_STATUS (1 << 26) 13857ccd5a2cSjsg # define GENERIC2_INT_STATUS (1 << 29) 13867ccd5a2cSjsg # define GENERIC1_INT_STATUS (1 << 30) 13877ccd5a2cSjsg # define GENERIC0_INT_STATUS (1 << 31) 13887ccd5a2cSjsg 13897ccd5a2cSjsg #define CP_MAX_CONTEXT 0xC2B8 13907ccd5a2cSjsg 13917ccd5a2cSjsg #define CP_RB0_BASE_HI 0xC2C4 13927ccd5a2cSjsg 13937ccd5a2cSjsg #define RLC_CNTL 0xC300 13947ccd5a2cSjsg # define RLC_ENABLE (1 << 0) 13957ccd5a2cSjsg 13967ccd5a2cSjsg #define RLC_MC_CNTL 0xC30C 13977ccd5a2cSjsg 13987ccd5a2cSjsg #define RLC_MEM_SLP_CNTL 0xC318 13997ccd5a2cSjsg # define RLC_MEM_LS_EN (1 << 0) 14007ccd5a2cSjsg 14017ccd5a2cSjsg #define RLC_LB_CNTR_MAX 0xC348 14027ccd5a2cSjsg 14037ccd5a2cSjsg #define RLC_LB_CNTL 0xC364 14047ccd5a2cSjsg # define LOAD_BALANCE_ENABLE (1 << 0) 14057ccd5a2cSjsg 14067ccd5a2cSjsg #define RLC_LB_CNTR_INIT 0xC36C 14077ccd5a2cSjsg 14087ccd5a2cSjsg #define RLC_SAVE_AND_RESTORE_BASE 0xC374 14097ccd5a2cSjsg #define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */ 14107ccd5a2cSjsg #define RLC_CP_TABLE_RESTORE 0xC378 /* APU */ 14117ccd5a2cSjsg #define RLC_PG_DELAY_2 0xC37C 14127ccd5a2cSjsg 14137ccd5a2cSjsg #define RLC_GPM_UCODE_ADDR 0xC388 14147ccd5a2cSjsg #define RLC_GPM_UCODE_DATA 0xC38C 14157ccd5a2cSjsg #define RLC_GPU_CLOCK_COUNT_LSB 0xC390 14167ccd5a2cSjsg #define RLC_GPU_CLOCK_COUNT_MSB 0xC394 14177ccd5a2cSjsg #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398 14187ccd5a2cSjsg #define RLC_UCODE_CNTL 0xC39C 14197ccd5a2cSjsg 14207ccd5a2cSjsg #define RLC_GPM_STAT 0xC400 14217ccd5a2cSjsg # define RLC_GPM_BUSY (1 << 0) 14227ccd5a2cSjsg # define GFX_POWER_STATUS (1 << 1) 14237ccd5a2cSjsg # define GFX_CLOCK_STATUS (1 << 2) 14247ccd5a2cSjsg 14257ccd5a2cSjsg #define RLC_PG_CNTL 0xC40C 14267ccd5a2cSjsg # define GFX_PG_ENABLE (1 << 0) 14277ccd5a2cSjsg # define GFX_PG_SRC (1 << 1) 14287ccd5a2cSjsg # define DYN_PER_CU_PG_ENABLE (1 << 2) 14297ccd5a2cSjsg # define STATIC_PER_CU_PG_ENABLE (1 << 3) 14307ccd5a2cSjsg # define DISABLE_GDS_PG (1 << 13) 14317ccd5a2cSjsg # define DISABLE_CP_PG (1 << 15) 14327ccd5a2cSjsg # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17) 14337ccd5a2cSjsg # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18) 14347ccd5a2cSjsg 14357ccd5a2cSjsg #define RLC_CGTT_MGCG_OVERRIDE 0xC420 14367ccd5a2cSjsg #define RLC_CGCG_CGLS_CTRL 0xC424 14377ccd5a2cSjsg # define CGCG_EN (1 << 0) 14387ccd5a2cSjsg # define CGLS_EN (1 << 1) 14397ccd5a2cSjsg 14407ccd5a2cSjsg #define RLC_PG_DELAY 0xC434 14417ccd5a2cSjsg 14427ccd5a2cSjsg #define RLC_LB_INIT_CU_MASK 0xC43C 14437ccd5a2cSjsg 14447ccd5a2cSjsg #define RLC_LB_PARAMS 0xC444 14457ccd5a2cSjsg 14467ccd5a2cSjsg #define RLC_PG_AO_CU_MASK 0xC44C 14477ccd5a2cSjsg 14487ccd5a2cSjsg #define RLC_MAX_PG_CU 0xC450 14497ccd5a2cSjsg # define MAX_PU_CU(x) ((x) << 0) 14507ccd5a2cSjsg # define MAX_PU_CU_MASK (0xff << 0) 14517ccd5a2cSjsg #define RLC_AUTO_PG_CTRL 0xC454 14527ccd5a2cSjsg # define AUTO_PG_EN (1 << 0) 14537ccd5a2cSjsg # define GRBM_REG_SGIT(x) ((x) << 3) 14547ccd5a2cSjsg # define GRBM_REG_SGIT_MASK (0xffff << 3) 14557ccd5a2cSjsg 14567ccd5a2cSjsg #define RLC_SERDES_WR_CU_MASTER_MASK 0xC474 14577ccd5a2cSjsg #define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478 14587ccd5a2cSjsg #define RLC_SERDES_WR_CTRL 0xC47C 14597ccd5a2cSjsg #define BPM_ADDR(x) ((x) << 0) 14607ccd5a2cSjsg #define BPM_ADDR_MASK (0xff << 0) 14617ccd5a2cSjsg #define CGLS_ENABLE (1 << 16) 14627ccd5a2cSjsg #define CGCG_OVERRIDE_0 (1 << 20) 14637ccd5a2cSjsg #define MGCG_OVERRIDE_0 (1 << 22) 14647ccd5a2cSjsg #define MGCG_OVERRIDE_1 (1 << 23) 14657ccd5a2cSjsg 14667ccd5a2cSjsg #define RLC_SERDES_CU_MASTER_BUSY 0xC484 14677ccd5a2cSjsg #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 14687ccd5a2cSjsg # define SE_MASTER_BUSY_MASK 0x0000ffff 14697ccd5a2cSjsg # define GC_MASTER_BUSY (1 << 16) 14707ccd5a2cSjsg # define TC0_MASTER_BUSY (1 << 17) 14717ccd5a2cSjsg # define TC1_MASTER_BUSY (1 << 18) 14727ccd5a2cSjsg 14737ccd5a2cSjsg #define RLC_GPM_SCRATCH_ADDR 0xC4B0 14747ccd5a2cSjsg #define RLC_GPM_SCRATCH_DATA 0xC4B4 14757ccd5a2cSjsg 14767ccd5a2cSjsg #define RLC_GPR_REG2 0xC4E8 14777ccd5a2cSjsg #define REQ 0x00000001 14787ccd5a2cSjsg #define MESSAGE(x) ((x) << 1) 14797ccd5a2cSjsg #define MESSAGE_MASK 0x0000001e 14807ccd5a2cSjsg #define MSG_ENTER_RLC_SAFE_MODE 1 14817ccd5a2cSjsg #define MSG_EXIT_RLC_SAFE_MODE 0 14827ccd5a2cSjsg 14837ccd5a2cSjsg #define CP_HPD_EOP_BASE_ADDR 0xC904 14847ccd5a2cSjsg #define CP_HPD_EOP_BASE_ADDR_HI 0xC908 14857ccd5a2cSjsg #define CP_HPD_EOP_VMID 0xC90C 14867ccd5a2cSjsg #define CP_HPD_EOP_CONTROL 0xC910 14877ccd5a2cSjsg #define EOP_SIZE(x) ((x) << 0) 14887ccd5a2cSjsg #define EOP_SIZE_MASK (0x3f << 0) 14897ccd5a2cSjsg #define CP_MQD_BASE_ADDR 0xC914 14907ccd5a2cSjsg #define CP_MQD_BASE_ADDR_HI 0xC918 14917ccd5a2cSjsg #define CP_HQD_ACTIVE 0xC91C 14927ccd5a2cSjsg #define CP_HQD_VMID 0xC920 14937ccd5a2cSjsg 14947ccd5a2cSjsg #define CP_HQD_PERSISTENT_STATE 0xC924u 14957ccd5a2cSjsg #define DEFAULT_CP_HQD_PERSISTENT_STATE (0x33U << 8) 14967ccd5a2cSjsg 14977ccd5a2cSjsg #define CP_HQD_PIPE_PRIORITY 0xC928u 14987ccd5a2cSjsg #define CP_HQD_QUEUE_PRIORITY 0xC92Cu 14997ccd5a2cSjsg #define CP_HQD_QUANTUM 0xC930u 15007ccd5a2cSjsg #define QUANTUM_EN 1U 15017ccd5a2cSjsg #define QUANTUM_SCALE_1MS (1U << 4) 15027ccd5a2cSjsg #define QUANTUM_DURATION(x) ((x) << 8) 15037ccd5a2cSjsg 15047ccd5a2cSjsg #define CP_HQD_PQ_BASE 0xC934 15057ccd5a2cSjsg #define CP_HQD_PQ_BASE_HI 0xC938 15067ccd5a2cSjsg #define CP_HQD_PQ_RPTR 0xC93C 15077ccd5a2cSjsg #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940 15087ccd5a2cSjsg #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944 15097ccd5a2cSjsg #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948 15107ccd5a2cSjsg #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C 15117ccd5a2cSjsg #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950 15127ccd5a2cSjsg #define DOORBELL_OFFSET(x) ((x) << 2) 15137ccd5a2cSjsg #define DOORBELL_OFFSET_MASK (0x1fffff << 2) 15147ccd5a2cSjsg #define DOORBELL_SOURCE (1 << 28) 15157ccd5a2cSjsg #define DOORBELL_SCHD_HIT (1 << 29) 15167ccd5a2cSjsg #define DOORBELL_EN (1 << 30) 15177ccd5a2cSjsg #define DOORBELL_HIT (1 << 31) 15187ccd5a2cSjsg #define CP_HQD_PQ_WPTR 0xC954 15197ccd5a2cSjsg #define CP_HQD_PQ_CONTROL 0xC958 15207ccd5a2cSjsg #define QUEUE_SIZE(x) ((x) << 0) 15217ccd5a2cSjsg #define QUEUE_SIZE_MASK (0x3f << 0) 15227ccd5a2cSjsg #define RPTR_BLOCK_SIZE(x) ((x) << 8) 15237ccd5a2cSjsg #define RPTR_BLOCK_SIZE_MASK (0x3f << 8) 15247ccd5a2cSjsg #define PQ_VOLATILE (1 << 26) 15257ccd5a2cSjsg #define NO_UPDATE_RPTR (1 << 27) 15267ccd5a2cSjsg #define UNORD_DISPATCH (1 << 28) 15277ccd5a2cSjsg #define ROQ_PQ_IB_FLIP (1 << 29) 15287ccd5a2cSjsg #define PRIV_STATE (1 << 30) 15297ccd5a2cSjsg #define KMD_QUEUE (1 << 31) 15307ccd5a2cSjsg 15317ccd5a2cSjsg #define CP_HQD_IB_BASE_ADDR 0xC95Cu 15327ccd5a2cSjsg #define CP_HQD_IB_BASE_ADDR_HI 0xC960u 15337ccd5a2cSjsg #define CP_HQD_IB_RPTR 0xC964u 15347ccd5a2cSjsg #define CP_HQD_IB_CONTROL 0xC968u 15357ccd5a2cSjsg #define IB_ATC_EN (1U << 23) 15367ccd5a2cSjsg #define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20) 15377ccd5a2cSjsg 15387ccd5a2cSjsg #define CP_HQD_DEQUEUE_REQUEST 0xC974 15397ccd5a2cSjsg #define DEQUEUE_REQUEST_DRAIN 1 15407ccd5a2cSjsg #define DEQUEUE_REQUEST_RESET 2 15417ccd5a2cSjsg 15427ccd5a2cSjsg #define CP_MQD_CONTROL 0xC99C 15437ccd5a2cSjsg #define MQD_VMID(x) ((x) << 0) 15447ccd5a2cSjsg #define MQD_VMID_MASK (0xf << 0) 15457ccd5a2cSjsg 15467ccd5a2cSjsg #define CP_HQD_SEMA_CMD 0xC97Cu 15477ccd5a2cSjsg #define CP_HQD_MSG_TYPE 0xC980u 15487ccd5a2cSjsg #define CP_HQD_ATOMIC0_PREOP_LO 0xC984u 15497ccd5a2cSjsg #define CP_HQD_ATOMIC0_PREOP_HI 0xC988u 15507ccd5a2cSjsg #define CP_HQD_ATOMIC1_PREOP_LO 0xC98Cu 15517ccd5a2cSjsg #define CP_HQD_ATOMIC1_PREOP_HI 0xC990u 15527ccd5a2cSjsg #define CP_HQD_HQ_SCHEDULER0 0xC994u 15537ccd5a2cSjsg #define CP_HQD_HQ_SCHEDULER1 0xC998u 15547ccd5a2cSjsg 15557ccd5a2cSjsg #define SH_STATIC_MEM_CONFIG 0x9604u 15567ccd5a2cSjsg 15577ccd5a2cSjsg #define DB_RENDER_CONTROL 0x28000 15587ccd5a2cSjsg 15597ccd5a2cSjsg #define PA_SC_RASTER_CONFIG 0x28350 15607ccd5a2cSjsg # define RASTER_CONFIG_RB_MAP_0 0 15617ccd5a2cSjsg # define RASTER_CONFIG_RB_MAP_1 1 15627ccd5a2cSjsg # define RASTER_CONFIG_RB_MAP_2 2 15637ccd5a2cSjsg # define RASTER_CONFIG_RB_MAP_3 3 15647ccd5a2cSjsg #define PKR_MAP(x) ((x) << 8) 15657ccd5a2cSjsg 15667ccd5a2cSjsg #define VGT_EVENT_INITIATOR 0x28a90 15677ccd5a2cSjsg # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 15687ccd5a2cSjsg # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 15697ccd5a2cSjsg # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 15707ccd5a2cSjsg # define CACHE_FLUSH_TS (4 << 0) 15717ccd5a2cSjsg # define CACHE_FLUSH (6 << 0) 15727ccd5a2cSjsg # define CS_PARTIAL_FLUSH (7 << 0) 15737ccd5a2cSjsg # define VGT_STREAMOUT_RESET (10 << 0) 15747ccd5a2cSjsg # define END_OF_PIPE_INCR_DE (11 << 0) 15757ccd5a2cSjsg # define END_OF_PIPE_IB_END (12 << 0) 15767ccd5a2cSjsg # define RST_PIX_CNT (13 << 0) 15777ccd5a2cSjsg # define VS_PARTIAL_FLUSH (15 << 0) 15787ccd5a2cSjsg # define PS_PARTIAL_FLUSH (16 << 0) 15797ccd5a2cSjsg # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 15807ccd5a2cSjsg # define ZPASS_DONE (21 << 0) 15817ccd5a2cSjsg # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 15827ccd5a2cSjsg # define PERFCOUNTER_START (23 << 0) 15837ccd5a2cSjsg # define PERFCOUNTER_STOP (24 << 0) 15847ccd5a2cSjsg # define PIPELINESTAT_START (25 << 0) 15857ccd5a2cSjsg # define PIPELINESTAT_STOP (26 << 0) 15867ccd5a2cSjsg # define PERFCOUNTER_SAMPLE (27 << 0) 15877ccd5a2cSjsg # define SAMPLE_PIPELINESTAT (30 << 0) 15887ccd5a2cSjsg # define SO_VGT_STREAMOUT_FLUSH (31 << 0) 15897ccd5a2cSjsg # define SAMPLE_STREAMOUTSTATS (32 << 0) 15907ccd5a2cSjsg # define RESET_VTX_CNT (33 << 0) 15917ccd5a2cSjsg # define VGT_FLUSH (36 << 0) 15927ccd5a2cSjsg # define BOTTOM_OF_PIPE_TS (40 << 0) 15937ccd5a2cSjsg # define DB_CACHE_FLUSH_AND_INV (42 << 0) 15947ccd5a2cSjsg # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 15957ccd5a2cSjsg # define FLUSH_AND_INV_DB_META (44 << 0) 15967ccd5a2cSjsg # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 15977ccd5a2cSjsg # define FLUSH_AND_INV_CB_META (46 << 0) 15987ccd5a2cSjsg # define CS_DONE (47 << 0) 15997ccd5a2cSjsg # define PS_DONE (48 << 0) 16007ccd5a2cSjsg # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 16017ccd5a2cSjsg # define THREAD_TRACE_START (51 << 0) 16027ccd5a2cSjsg # define THREAD_TRACE_STOP (52 << 0) 16037ccd5a2cSjsg # define THREAD_TRACE_FLUSH (54 << 0) 16047ccd5a2cSjsg # define THREAD_TRACE_FINISH (55 << 0) 16057ccd5a2cSjsg # define PIXEL_PIPE_STAT_CONTROL (56 << 0) 16067ccd5a2cSjsg # define PIXEL_PIPE_STAT_DUMP (57 << 0) 16077ccd5a2cSjsg # define PIXEL_PIPE_STAT_RESET (58 << 0) 16087ccd5a2cSjsg 16097ccd5a2cSjsg #define SCRATCH_REG0 0x30100 16107ccd5a2cSjsg #define SCRATCH_REG1 0x30104 16117ccd5a2cSjsg #define SCRATCH_REG2 0x30108 16127ccd5a2cSjsg #define SCRATCH_REG3 0x3010C 16137ccd5a2cSjsg #define SCRATCH_REG4 0x30110 16147ccd5a2cSjsg #define SCRATCH_REG5 0x30114 16157ccd5a2cSjsg #define SCRATCH_REG6 0x30118 16167ccd5a2cSjsg #define SCRATCH_REG7 0x3011C 16177ccd5a2cSjsg 16187ccd5a2cSjsg #define SCRATCH_UMSK 0x30140 16197ccd5a2cSjsg #define SCRATCH_ADDR 0x30144 16207ccd5a2cSjsg 16217ccd5a2cSjsg #define CP_SEM_WAIT_TIMER 0x301BC 16227ccd5a2cSjsg 16237ccd5a2cSjsg #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8 16247ccd5a2cSjsg 16257ccd5a2cSjsg #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0 16267ccd5a2cSjsg 16277ccd5a2cSjsg #define GRBM_GFX_INDEX 0x30800 16287ccd5a2cSjsg #define INSTANCE_INDEX(x) ((x) << 0) 16297ccd5a2cSjsg #define SH_INDEX(x) ((x) << 8) 16307ccd5a2cSjsg #define SE_INDEX(x) ((x) << 16) 16317ccd5a2cSjsg #define SH_BROADCAST_WRITES (1 << 29) 16327ccd5a2cSjsg #define INSTANCE_BROADCAST_WRITES (1 << 30) 16337ccd5a2cSjsg #define SE_BROADCAST_WRITES (1 << 31) 16347ccd5a2cSjsg 16357ccd5a2cSjsg #define VGT_ESGS_RING_SIZE 0x30900 16367ccd5a2cSjsg #define VGT_GSVS_RING_SIZE 0x30904 16377ccd5a2cSjsg #define VGT_PRIMITIVE_TYPE 0x30908 16387ccd5a2cSjsg #define VGT_INDEX_TYPE 0x3090C 16397ccd5a2cSjsg 16407ccd5a2cSjsg #define VGT_NUM_INDICES 0x30930 16417ccd5a2cSjsg #define VGT_NUM_INSTANCES 0x30934 16427ccd5a2cSjsg #define VGT_TF_RING_SIZE 0x30938 16437ccd5a2cSjsg #define VGT_HS_OFFCHIP_PARAM 0x3093C 16447ccd5a2cSjsg #define VGT_TF_MEMORY_BASE 0x30940 16457ccd5a2cSjsg 16467ccd5a2cSjsg #define PA_SU_LINE_STIPPLE_VALUE 0x30a00 16477ccd5a2cSjsg #define PA_SC_LINE_STIPPLE_STATE 0x30a04 16487ccd5a2cSjsg 16497ccd5a2cSjsg #define SQC_CACHES 0x30d20 16507ccd5a2cSjsg 16517ccd5a2cSjsg #define CP_PERFMON_CNTL 0x36020 16527ccd5a2cSjsg 16537ccd5a2cSjsg #define CGTS_SM_CTRL_REG 0x3c000 16547ccd5a2cSjsg #define SM_MODE(x) ((x) << 17) 16557ccd5a2cSjsg #define SM_MODE_MASK (0x7 << 17) 16567ccd5a2cSjsg #define SM_MODE_ENABLE (1 << 20) 16577ccd5a2cSjsg #define CGTS_OVERRIDE (1 << 21) 16587ccd5a2cSjsg #define CGTS_LS_OVERRIDE (1 << 22) 16597ccd5a2cSjsg #define ON_MONITOR_ADD_EN (1 << 23) 16607ccd5a2cSjsg #define ON_MONITOR_ADD(x) ((x) << 24) 16617ccd5a2cSjsg #define ON_MONITOR_ADD_MASK (0xff << 24) 16627ccd5a2cSjsg 16637ccd5a2cSjsg #define CGTS_TCC_DISABLE 0x3c00c 16647ccd5a2cSjsg #define CGTS_USER_TCC_DISABLE 0x3c010 16657ccd5a2cSjsg #define TCC_DISABLE_MASK 0xFFFF0000 16667ccd5a2cSjsg #define TCC_DISABLE_SHIFT 16 16677ccd5a2cSjsg 16687ccd5a2cSjsg #define CB_CGTT_SCLK_CTRL 0x3c2a0 16697ccd5a2cSjsg 16707ccd5a2cSjsg /* 16717ccd5a2cSjsg * PM4 16727ccd5a2cSjsg */ 16737ccd5a2cSjsg #define PACKET_TYPE0 0 16747ccd5a2cSjsg #define PACKET_TYPE1 1 16757ccd5a2cSjsg #define PACKET_TYPE2 2 16767ccd5a2cSjsg #define PACKET_TYPE3 3 16777ccd5a2cSjsg 16787ccd5a2cSjsg #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 16797ccd5a2cSjsg #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 16807ccd5a2cSjsg #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 16817ccd5a2cSjsg #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 16827ccd5a2cSjsg #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 16837ccd5a2cSjsg (((reg) >> 2) & 0xFFFF) | \ 16847ccd5a2cSjsg ((n) & 0x3FFF) << 16) 16857ccd5a2cSjsg #define CP_PACKET2 0x80000000 16867ccd5a2cSjsg #define PACKET2_PAD_SHIFT 0 16877ccd5a2cSjsg #define PACKET2_PAD_MASK (0x3fffffff << 0) 16887ccd5a2cSjsg 16897ccd5a2cSjsg #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 16907ccd5a2cSjsg 16917ccd5a2cSjsg #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 16927ccd5a2cSjsg (((op) & 0xFF) << 8) | \ 16937ccd5a2cSjsg ((n) & 0x3FFF) << 16) 16947ccd5a2cSjsg 16957ccd5a2cSjsg #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 16967ccd5a2cSjsg 16977ccd5a2cSjsg /* Packet 3 types */ 16987ccd5a2cSjsg #define PACKET3_NOP 0x10 16997ccd5a2cSjsg #define PACKET3_SET_BASE 0x11 17007ccd5a2cSjsg #define PACKET3_BASE_INDEX(x) ((x) << 0) 17017ccd5a2cSjsg #define CE_PARTITION_BASE 3 17027ccd5a2cSjsg #define PACKET3_CLEAR_STATE 0x12 17037ccd5a2cSjsg #define PACKET3_INDEX_BUFFER_SIZE 0x13 17047ccd5a2cSjsg #define PACKET3_DISPATCH_DIRECT 0x15 17057ccd5a2cSjsg #define PACKET3_DISPATCH_INDIRECT 0x16 17067ccd5a2cSjsg #define PACKET3_ATOMIC_GDS 0x1D 17077ccd5a2cSjsg #define PACKET3_ATOMIC_MEM 0x1E 17087ccd5a2cSjsg #define PACKET3_OCCLUSION_QUERY 0x1F 17097ccd5a2cSjsg #define PACKET3_SET_PREDICATION 0x20 17107ccd5a2cSjsg #define PACKET3_REG_RMW 0x21 17117ccd5a2cSjsg #define PACKET3_COND_EXEC 0x22 17127ccd5a2cSjsg #define PACKET3_PRED_EXEC 0x23 17137ccd5a2cSjsg #define PACKET3_DRAW_INDIRECT 0x24 17147ccd5a2cSjsg #define PACKET3_DRAW_INDEX_INDIRECT 0x25 17157ccd5a2cSjsg #define PACKET3_INDEX_BASE 0x26 17167ccd5a2cSjsg #define PACKET3_DRAW_INDEX_2 0x27 17177ccd5a2cSjsg #define PACKET3_CONTEXT_CONTROL 0x28 17187ccd5a2cSjsg #define PACKET3_INDEX_TYPE 0x2A 17197ccd5a2cSjsg #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 17207ccd5a2cSjsg #define PACKET3_DRAW_INDEX_AUTO 0x2D 17217ccd5a2cSjsg #define PACKET3_NUM_INSTANCES 0x2F 17227ccd5a2cSjsg #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 17237ccd5a2cSjsg #define PACKET3_INDIRECT_BUFFER_CONST 0x33 17247ccd5a2cSjsg #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 17257ccd5a2cSjsg #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 17267ccd5a2cSjsg #define PACKET3_DRAW_PREAMBLE 0x36 17277ccd5a2cSjsg #define PACKET3_WRITE_DATA 0x37 17287ccd5a2cSjsg #define WRITE_DATA_DST_SEL(x) ((x) << 8) 17297ccd5a2cSjsg /* 0 - register 17307ccd5a2cSjsg * 1 - memory (sync - via GRBM) 17317ccd5a2cSjsg * 2 - gl2 17327ccd5a2cSjsg * 3 - gds 17337ccd5a2cSjsg * 4 - reserved 17347ccd5a2cSjsg * 5 - memory (async - direct) 17357ccd5a2cSjsg */ 17367ccd5a2cSjsg #define WR_ONE_ADDR (1 << 16) 17377ccd5a2cSjsg #define WR_CONFIRM (1 << 20) 17387ccd5a2cSjsg #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 17397ccd5a2cSjsg /* 0 - LRU 17407ccd5a2cSjsg * 1 - Stream 17417ccd5a2cSjsg */ 17427ccd5a2cSjsg #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 17437ccd5a2cSjsg /* 0 - me 17447ccd5a2cSjsg * 1 - pfp 17457ccd5a2cSjsg * 2 - ce 17467ccd5a2cSjsg */ 17477ccd5a2cSjsg #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 17487ccd5a2cSjsg #define PACKET3_MEM_SEMAPHORE 0x39 17497ccd5a2cSjsg # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 17507ccd5a2cSjsg # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 17517ccd5a2cSjsg # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 17527ccd5a2cSjsg # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 17537ccd5a2cSjsg # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 17547ccd5a2cSjsg #define PACKET3_COPY_DW 0x3B 17557ccd5a2cSjsg #define PACKET3_WAIT_REG_MEM 0x3C 17567ccd5a2cSjsg #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 17577ccd5a2cSjsg /* 0 - always 17587ccd5a2cSjsg * 1 - < 17597ccd5a2cSjsg * 2 - <= 17607ccd5a2cSjsg * 3 - == 17617ccd5a2cSjsg * 4 - != 17627ccd5a2cSjsg * 5 - >= 17637ccd5a2cSjsg * 6 - > 17647ccd5a2cSjsg */ 17657ccd5a2cSjsg #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 17667ccd5a2cSjsg /* 0 - reg 17677ccd5a2cSjsg * 1 - mem 17687ccd5a2cSjsg */ 17697ccd5a2cSjsg #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 17707ccd5a2cSjsg /* 0 - wait_reg_mem 17717ccd5a2cSjsg * 1 - wr_wait_wr_reg 17727ccd5a2cSjsg */ 17737ccd5a2cSjsg #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 17747ccd5a2cSjsg /* 0 - me 17757ccd5a2cSjsg * 1 - pfp 17767ccd5a2cSjsg */ 17777ccd5a2cSjsg #define PACKET3_INDIRECT_BUFFER 0x3F 17787ccd5a2cSjsg #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 17797ccd5a2cSjsg #define INDIRECT_BUFFER_VALID (1 << 23) 17807ccd5a2cSjsg #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 17817ccd5a2cSjsg /* 0 - LRU 17827ccd5a2cSjsg * 1 - Stream 17837ccd5a2cSjsg * 2 - Bypass 17847ccd5a2cSjsg */ 17857ccd5a2cSjsg #define PACKET3_COPY_DATA 0x40 17867ccd5a2cSjsg #define PACKET3_PFP_SYNC_ME 0x42 17877ccd5a2cSjsg #define PACKET3_SURFACE_SYNC 0x43 17887ccd5a2cSjsg # define PACKET3_DEST_BASE_0_ENA (1 << 0) 17897ccd5a2cSjsg # define PACKET3_DEST_BASE_1_ENA (1 << 1) 17907ccd5a2cSjsg # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 17917ccd5a2cSjsg # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 17927ccd5a2cSjsg # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 17937ccd5a2cSjsg # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 17947ccd5a2cSjsg # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 17957ccd5a2cSjsg # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 17967ccd5a2cSjsg # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 17977ccd5a2cSjsg # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 17987ccd5a2cSjsg # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 17997ccd5a2cSjsg # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 18007ccd5a2cSjsg # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 18017ccd5a2cSjsg # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 18027ccd5a2cSjsg # define PACKET3_DEST_BASE_2_ENA (1 << 19) 18037ccd5a2cSjsg # define PACKET3_DEST_BASE_3_ENA (1 << 21) 18047ccd5a2cSjsg # define PACKET3_TCL1_ACTION_ENA (1 << 22) 18057ccd5a2cSjsg # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 18067ccd5a2cSjsg # define PACKET3_CB_ACTION_ENA (1 << 25) 18077ccd5a2cSjsg # define PACKET3_DB_ACTION_ENA (1 << 26) 18087ccd5a2cSjsg # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 18097ccd5a2cSjsg # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 18107ccd5a2cSjsg # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 18117ccd5a2cSjsg #define PACKET3_COND_WRITE 0x45 18127ccd5a2cSjsg #define PACKET3_EVENT_WRITE 0x46 18137ccd5a2cSjsg #define EVENT_TYPE(x) ((x) << 0) 18147ccd5a2cSjsg #define EVENT_INDEX(x) ((x) << 8) 18157ccd5a2cSjsg /* 0 - any non-TS event 18167ccd5a2cSjsg * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 18177ccd5a2cSjsg * 2 - SAMPLE_PIPELINESTAT 18187ccd5a2cSjsg * 3 - SAMPLE_STREAMOUTSTAT* 18197ccd5a2cSjsg * 4 - *S_PARTIAL_FLUSH 18207ccd5a2cSjsg * 5 - EOP events 18217ccd5a2cSjsg * 6 - EOS events 18227ccd5a2cSjsg */ 18237ccd5a2cSjsg #define PACKET3_EVENT_WRITE_EOP 0x47 18247ccd5a2cSjsg #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 18257ccd5a2cSjsg #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 18267ccd5a2cSjsg #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 18277ccd5a2cSjsg #define EOP_TCL1_ACTION_EN (1 << 16) 18287ccd5a2cSjsg #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 18297ccd5a2cSjsg #define EOP_TCL2_VOLATILE (1 << 24) 18307ccd5a2cSjsg #define EOP_CACHE_POLICY(x) ((x) << 25) 18317ccd5a2cSjsg /* 0 - LRU 18327ccd5a2cSjsg * 1 - Stream 18337ccd5a2cSjsg * 2 - Bypass 18347ccd5a2cSjsg */ 18357ccd5a2cSjsg #define DATA_SEL(x) ((x) << 29) 18367ccd5a2cSjsg /* 0 - discard 18377ccd5a2cSjsg * 1 - send low 32bit data 18387ccd5a2cSjsg * 2 - send 64bit data 18397ccd5a2cSjsg * 3 - send 64bit GPU counter value 18407ccd5a2cSjsg * 4 - send 64bit sys counter value 18417ccd5a2cSjsg */ 18427ccd5a2cSjsg #define INT_SEL(x) ((x) << 24) 18437ccd5a2cSjsg /* 0 - none 18447ccd5a2cSjsg * 1 - interrupt only (DATA_SEL = 0) 18457ccd5a2cSjsg * 2 - interrupt when data write is confirmed 18467ccd5a2cSjsg */ 18477ccd5a2cSjsg #define DST_SEL(x) ((x) << 16) 18487ccd5a2cSjsg /* 0 - MC 18497ccd5a2cSjsg * 1 - TC/L2 18507ccd5a2cSjsg */ 18517ccd5a2cSjsg #define PACKET3_EVENT_WRITE_EOS 0x48 18527ccd5a2cSjsg #define PACKET3_RELEASE_MEM 0x49 18537ccd5a2cSjsg #define PACKET3_PREAMBLE_CNTL 0x4A 18547ccd5a2cSjsg # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 18557ccd5a2cSjsg # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 18567ccd5a2cSjsg #define PACKET3_DMA_DATA 0x50 18577ccd5a2cSjsg /* 1. header 18587ccd5a2cSjsg * 2. CONTROL 18597ccd5a2cSjsg * 3. SRC_ADDR_LO or DATA [31:0] 18607ccd5a2cSjsg * 4. SRC_ADDR_HI [31:0] 18617ccd5a2cSjsg * 5. DST_ADDR_LO [31:0] 18627ccd5a2cSjsg * 6. DST_ADDR_HI [7:0] 18637ccd5a2cSjsg * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 18647ccd5a2cSjsg */ 18657ccd5a2cSjsg /* CONTROL */ 18667ccd5a2cSjsg # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 18677ccd5a2cSjsg /* 0 - ME 18687ccd5a2cSjsg * 1 - PFP 18697ccd5a2cSjsg */ 18707ccd5a2cSjsg # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 18717ccd5a2cSjsg /* 0 - LRU 18727ccd5a2cSjsg * 1 - Stream 18737ccd5a2cSjsg * 2 - Bypass 18747ccd5a2cSjsg */ 18757ccd5a2cSjsg # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 18767ccd5a2cSjsg # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 18777ccd5a2cSjsg /* 0 - DST_ADDR using DAS 18787ccd5a2cSjsg * 1 - GDS 18797ccd5a2cSjsg * 3 - DST_ADDR using L2 18807ccd5a2cSjsg */ 18817ccd5a2cSjsg # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 18827ccd5a2cSjsg /* 0 - LRU 18837ccd5a2cSjsg * 1 - Stream 18847ccd5a2cSjsg * 2 - Bypass 18857ccd5a2cSjsg */ 18867ccd5a2cSjsg # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 18877ccd5a2cSjsg # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 18887ccd5a2cSjsg /* 0 - SRC_ADDR using SAS 18897ccd5a2cSjsg * 1 - GDS 18907ccd5a2cSjsg * 2 - DATA 18917ccd5a2cSjsg * 3 - SRC_ADDR using L2 18927ccd5a2cSjsg */ 18937ccd5a2cSjsg # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 18947ccd5a2cSjsg /* COMMAND */ 18957ccd5a2cSjsg # define PACKET3_DMA_DATA_DIS_WC (1 << 21) 18967ccd5a2cSjsg # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 18977ccd5a2cSjsg /* 0 - none 18987ccd5a2cSjsg * 1 - 8 in 16 18997ccd5a2cSjsg * 2 - 8 in 32 19007ccd5a2cSjsg * 3 - 8 in 64 19017ccd5a2cSjsg */ 19027ccd5a2cSjsg # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 19037ccd5a2cSjsg /* 0 - none 19047ccd5a2cSjsg * 1 - 8 in 16 19057ccd5a2cSjsg * 2 - 8 in 32 19067ccd5a2cSjsg * 3 - 8 in 64 19077ccd5a2cSjsg */ 19087ccd5a2cSjsg # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 19097ccd5a2cSjsg /* 0 - memory 19107ccd5a2cSjsg * 1 - register 19117ccd5a2cSjsg */ 19127ccd5a2cSjsg # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 19137ccd5a2cSjsg /* 0 - memory 19147ccd5a2cSjsg * 1 - register 19157ccd5a2cSjsg */ 19167ccd5a2cSjsg # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 19177ccd5a2cSjsg # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 19187ccd5a2cSjsg # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 19197ccd5a2cSjsg #define PACKET3_AQUIRE_MEM 0x58 19207ccd5a2cSjsg #define PACKET3_REWIND 0x59 19217ccd5a2cSjsg #define PACKET3_LOAD_UCONFIG_REG 0x5E 19227ccd5a2cSjsg #define PACKET3_LOAD_SH_REG 0x5F 19237ccd5a2cSjsg #define PACKET3_LOAD_CONFIG_REG 0x60 19247ccd5a2cSjsg #define PACKET3_LOAD_CONTEXT_REG 0x61 19257ccd5a2cSjsg #define PACKET3_SET_CONFIG_REG 0x68 19267ccd5a2cSjsg #define PACKET3_SET_CONFIG_REG_START 0x00008000 19277ccd5a2cSjsg #define PACKET3_SET_CONFIG_REG_END 0x0000b000 19287ccd5a2cSjsg #define PACKET3_SET_CONTEXT_REG 0x69 19297ccd5a2cSjsg #define PACKET3_SET_CONTEXT_REG_START 0x00028000 19307ccd5a2cSjsg #define PACKET3_SET_CONTEXT_REG_END 0x00029000 19317ccd5a2cSjsg #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 19327ccd5a2cSjsg #define PACKET3_SET_SH_REG 0x76 19337ccd5a2cSjsg #define PACKET3_SET_SH_REG_START 0x0000b000 19347ccd5a2cSjsg #define PACKET3_SET_SH_REG_END 0x0000c000 19357ccd5a2cSjsg #define PACKET3_SET_SH_REG_OFFSET 0x77 19367ccd5a2cSjsg #define PACKET3_SET_QUEUE_REG 0x78 19377ccd5a2cSjsg #define PACKET3_SET_UCONFIG_REG 0x79 19387ccd5a2cSjsg #define PACKET3_SET_UCONFIG_REG_START 0x00030000 19397ccd5a2cSjsg #define PACKET3_SET_UCONFIG_REG_END 0x00031000 19407ccd5a2cSjsg #define PACKET3_SCRATCH_RAM_WRITE 0x7D 19417ccd5a2cSjsg #define PACKET3_SCRATCH_RAM_READ 0x7E 19427ccd5a2cSjsg #define PACKET3_LOAD_CONST_RAM 0x80 19437ccd5a2cSjsg #define PACKET3_WRITE_CONST_RAM 0x81 19447ccd5a2cSjsg #define PACKET3_DUMP_CONST_RAM 0x83 19457ccd5a2cSjsg #define PACKET3_INCREMENT_CE_COUNTER 0x84 19467ccd5a2cSjsg #define PACKET3_INCREMENT_DE_COUNTER 0x85 19477ccd5a2cSjsg #define PACKET3_WAIT_ON_CE_COUNTER 0x86 19487ccd5a2cSjsg #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 19497ccd5a2cSjsg #define PACKET3_SWITCH_BUFFER 0x8B 19507ccd5a2cSjsg 19517ccd5a2cSjsg /* SDMA - first instance at 0xd000, second at 0xd800 */ 19527ccd5a2cSjsg #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 19537ccd5a2cSjsg #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ 19547ccd5a2cSjsg 19557ccd5a2cSjsg #define SDMA0_UCODE_ADDR 0xD000 19567ccd5a2cSjsg #define SDMA0_UCODE_DATA 0xD004 19577ccd5a2cSjsg #define SDMA0_POWER_CNTL 0xD008 19587ccd5a2cSjsg #define SDMA0_CLK_CTRL 0xD00C 19597ccd5a2cSjsg 19607ccd5a2cSjsg #define SDMA0_CNTL 0xD010 19617ccd5a2cSjsg # define TRAP_ENABLE (1 << 0) 19627ccd5a2cSjsg # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 19637ccd5a2cSjsg # define SEM_WAIT_INT_ENABLE (1 << 2) 19647ccd5a2cSjsg # define DATA_SWAP_ENABLE (1 << 3) 19657ccd5a2cSjsg # define FENCE_SWAP_ENABLE (1 << 4) 19667ccd5a2cSjsg # define AUTO_CTXSW_ENABLE (1 << 18) 19677ccd5a2cSjsg # define CTXEMPTY_INT_ENABLE (1 << 28) 19687ccd5a2cSjsg 19697ccd5a2cSjsg #define SDMA0_TILING_CONFIG 0xD018 19707ccd5a2cSjsg 19717ccd5a2cSjsg #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020 19727ccd5a2cSjsg #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024 19737ccd5a2cSjsg 19747ccd5a2cSjsg #define SDMA0_STATUS_REG 0xd034 19757ccd5a2cSjsg # define SDMA_IDLE (1 << 0) 19767ccd5a2cSjsg 19777ccd5a2cSjsg #define SDMA0_ME_CNTL 0xD048 19787ccd5a2cSjsg # define SDMA_HALT (1 << 0) 19797ccd5a2cSjsg 19807ccd5a2cSjsg #define SDMA0_GFX_RB_CNTL 0xD200 19817ccd5a2cSjsg # define SDMA_RB_ENABLE (1 << 0) 19827ccd5a2cSjsg # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */ 19837ccd5a2cSjsg # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 19847ccd5a2cSjsg # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12) 19857ccd5a2cSjsg # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 19867ccd5a2cSjsg # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 19877ccd5a2cSjsg #define SDMA0_GFX_RB_BASE 0xD204 19887ccd5a2cSjsg #define SDMA0_GFX_RB_BASE_HI 0xD208 19897ccd5a2cSjsg #define SDMA0_GFX_RB_RPTR 0xD20C 19907ccd5a2cSjsg #define SDMA0_GFX_RB_WPTR 0xD210 19917ccd5a2cSjsg 19927ccd5a2cSjsg #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220 19937ccd5a2cSjsg #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224 19947ccd5a2cSjsg #define SDMA0_GFX_IB_CNTL 0xD228 19957ccd5a2cSjsg # define SDMA_IB_ENABLE (1 << 0) 19967ccd5a2cSjsg # define SDMA_IB_SWAP_ENABLE (1 << 4) 19977ccd5a2cSjsg # define SDMA_SWITCH_INSIDE_IB (1 << 8) 19987ccd5a2cSjsg # define SDMA_CMD_VMID(x) ((x) << 16) 19997ccd5a2cSjsg 20007ccd5a2cSjsg #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C 20017ccd5a2cSjsg #define SDMA0_GFX_APE1_CNTL 0xD2A0 20027ccd5a2cSjsg 20037ccd5a2cSjsg #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 20047ccd5a2cSjsg (((sub_op) & 0xFF) << 8) | \ 20057ccd5a2cSjsg (((op) & 0xFF) << 0)) 20067ccd5a2cSjsg /* sDMA opcodes */ 20077ccd5a2cSjsg #define SDMA_OPCODE_NOP 0 20087ccd5a2cSjsg #define SDMA_OPCODE_COPY 1 20097ccd5a2cSjsg # define SDMA_COPY_SUB_OPCODE_LINEAR 0 20107ccd5a2cSjsg # define SDMA_COPY_SUB_OPCODE_TILED 1 20117ccd5a2cSjsg # define SDMA_COPY_SUB_OPCODE_SOA 3 20127ccd5a2cSjsg # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 20137ccd5a2cSjsg # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 20147ccd5a2cSjsg # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 20157ccd5a2cSjsg #define SDMA_OPCODE_WRITE 2 20167ccd5a2cSjsg # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 2017*7f4dd379Sjsg # define SDMA_WRITE_SUB_OPCODE_TILED 1 20187ccd5a2cSjsg #define SDMA_OPCODE_INDIRECT_BUFFER 4 20197ccd5a2cSjsg #define SDMA_OPCODE_FENCE 5 20207ccd5a2cSjsg #define SDMA_OPCODE_TRAP 6 20217ccd5a2cSjsg #define SDMA_OPCODE_SEMAPHORE 7 20227ccd5a2cSjsg # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 20237ccd5a2cSjsg /* 0 - increment 20247ccd5a2cSjsg * 1 - write 1 20257ccd5a2cSjsg */ 20267ccd5a2cSjsg # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 20277ccd5a2cSjsg /* 0 - wait 20287ccd5a2cSjsg * 1 - signal 20297ccd5a2cSjsg */ 20307ccd5a2cSjsg # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 20317ccd5a2cSjsg /* mailbox */ 20327ccd5a2cSjsg #define SDMA_OPCODE_POLL_REG_MEM 8 20337ccd5a2cSjsg # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 20347ccd5a2cSjsg /* 0 - wait_reg_mem 20357ccd5a2cSjsg * 1 - wr_wait_wr_reg 20367ccd5a2cSjsg */ 20377ccd5a2cSjsg # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 20387ccd5a2cSjsg /* 0 - always 20397ccd5a2cSjsg * 1 - < 20407ccd5a2cSjsg * 2 - <= 20417ccd5a2cSjsg * 3 - == 20427ccd5a2cSjsg * 4 - != 20437ccd5a2cSjsg * 5 - >= 20447ccd5a2cSjsg * 6 - > 20457ccd5a2cSjsg */ 20467ccd5a2cSjsg # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 20477ccd5a2cSjsg /* 0 = register 20487ccd5a2cSjsg * 1 = memory 20497ccd5a2cSjsg */ 20507ccd5a2cSjsg #define SDMA_OPCODE_COND_EXEC 9 20517ccd5a2cSjsg #define SDMA_OPCODE_CONSTANT_FILL 11 20527ccd5a2cSjsg # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 20537ccd5a2cSjsg /* 0 = byte fill 20547ccd5a2cSjsg * 2 = DW fill 20557ccd5a2cSjsg */ 20567ccd5a2cSjsg #define SDMA_OPCODE_GENERATE_PTE_PDE 12 20577ccd5a2cSjsg #define SDMA_OPCODE_TIMESTAMP 13 20587ccd5a2cSjsg # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 20597ccd5a2cSjsg # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 20607ccd5a2cSjsg # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 20617ccd5a2cSjsg #define SDMA_OPCODE_SRBM_WRITE 14 20627ccd5a2cSjsg # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 20637ccd5a2cSjsg /* byte mask */ 20647ccd5a2cSjsg 20657ccd5a2cSjsg /* UVD */ 20667ccd5a2cSjsg 20677ccd5a2cSjsg #define UVD_UDEC_ADDR_CONFIG 0xef4c 20687ccd5a2cSjsg #define UVD_UDEC_DB_ADDR_CONFIG 0xef50 20697ccd5a2cSjsg #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 2070*7f4dd379Sjsg #define UVD_NO_OP 0xeffc 20717ccd5a2cSjsg 20727ccd5a2cSjsg #define UVD_LMI_EXT40_ADDR 0xf498 2073*7f4dd379Sjsg #define UVD_GP_SCRATCH4 0xf4e0 20747ccd5a2cSjsg #define UVD_LMI_ADDR_EXT 0xf594 20757ccd5a2cSjsg #define UVD_VCPU_CACHE_OFFSET0 0xf608 20767ccd5a2cSjsg #define UVD_VCPU_CACHE_SIZE0 0xf60c 20777ccd5a2cSjsg #define UVD_VCPU_CACHE_OFFSET1 0xf610 20787ccd5a2cSjsg #define UVD_VCPU_CACHE_SIZE1 0xf614 20797ccd5a2cSjsg #define UVD_VCPU_CACHE_OFFSET2 0xf618 20807ccd5a2cSjsg #define UVD_VCPU_CACHE_SIZE2 0xf61c 20817ccd5a2cSjsg 20827ccd5a2cSjsg #define UVD_RBC_RB_RPTR 0xf690 20837ccd5a2cSjsg #define UVD_RBC_RB_WPTR 0xf694 20847ccd5a2cSjsg 20857ccd5a2cSjsg #define UVD_CGC_CTRL 0xF4B0 20867ccd5a2cSjsg # define DCM (1 << 0) 20877ccd5a2cSjsg # define CG_DT(x) ((x) << 2) 20887ccd5a2cSjsg # define CG_DT_MASK (0xf << 2) 20897ccd5a2cSjsg # define CLK_OD(x) ((x) << 6) 20907ccd5a2cSjsg # define CLK_OD_MASK (0x1f << 6) 20917ccd5a2cSjsg 20927ccd5a2cSjsg #define UVD_STATUS 0xf6bc 20937ccd5a2cSjsg 20947ccd5a2cSjsg /* UVD clocks */ 20957ccd5a2cSjsg 20967ccd5a2cSjsg #define CG_DCLK_CNTL 0xC050009C 20977ccd5a2cSjsg # define DCLK_DIVIDER_MASK 0x7f 20987ccd5a2cSjsg # define DCLK_DIR_CNTL_EN (1 << 8) 20997ccd5a2cSjsg #define CG_DCLK_STATUS 0xC05000A0 21007ccd5a2cSjsg # define DCLK_STATUS (1 << 0) 21017ccd5a2cSjsg #define CG_VCLK_CNTL 0xC05000A4 21027ccd5a2cSjsg #define CG_VCLK_STATUS 0xC05000A8 21037ccd5a2cSjsg 21047ccd5a2cSjsg /* UVD CTX indirect */ 21057ccd5a2cSjsg #define UVD_CGC_MEM_CTRL 0xC0 21067ccd5a2cSjsg 21077ccd5a2cSjsg /* VCE */ 21087ccd5a2cSjsg 21097ccd5a2cSjsg #define VCE_VCPU_CACHE_OFFSET0 0x20024 21107ccd5a2cSjsg #define VCE_VCPU_CACHE_SIZE0 0x20028 21117ccd5a2cSjsg #define VCE_VCPU_CACHE_OFFSET1 0x2002c 21127ccd5a2cSjsg #define VCE_VCPU_CACHE_SIZE1 0x20030 21137ccd5a2cSjsg #define VCE_VCPU_CACHE_OFFSET2 0x20034 21147ccd5a2cSjsg #define VCE_VCPU_CACHE_SIZE2 0x20038 21157ccd5a2cSjsg #define VCE_RB_RPTR2 0x20178 21167ccd5a2cSjsg #define VCE_RB_WPTR2 0x2017c 21177ccd5a2cSjsg #define VCE_RB_RPTR 0x2018c 21187ccd5a2cSjsg #define VCE_RB_WPTR 0x20190 21197ccd5a2cSjsg #define VCE_CLOCK_GATING_A 0x202f8 21207ccd5a2cSjsg # define CGC_CLK_GATE_DLY_TIMER_MASK (0xf << 0) 21217ccd5a2cSjsg # define CGC_CLK_GATE_DLY_TIMER(x) ((x) << 0) 21227ccd5a2cSjsg # define CGC_CLK_GATER_OFF_DLY_TIMER_MASK (0xff << 4) 21237ccd5a2cSjsg # define CGC_CLK_GATER_OFF_DLY_TIMER(x) ((x) << 4) 21247ccd5a2cSjsg # define CGC_UENC_WAIT_AWAKE (1 << 18) 21257ccd5a2cSjsg #define VCE_CLOCK_GATING_B 0x202fc 21267ccd5a2cSjsg #define VCE_CGTT_CLK_OVERRIDE 0x207a0 21277ccd5a2cSjsg #define VCE_UENC_CLOCK_GATING 0x207bc 21287ccd5a2cSjsg # define CLOCK_ON_DELAY_MASK (0xf << 0) 21297ccd5a2cSjsg # define CLOCK_ON_DELAY(x) ((x) << 0) 21307ccd5a2cSjsg # define CLOCK_OFF_DELAY_MASK (0xff << 4) 21317ccd5a2cSjsg # define CLOCK_OFF_DELAY(x) ((x) << 4) 21327ccd5a2cSjsg #define VCE_UENC_REG_CLOCK_GATING 0x207c0 21337ccd5a2cSjsg #define VCE_SYS_INT_EN 0x21300 21347ccd5a2cSjsg # define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3) 21357ccd5a2cSjsg #define VCE_LMI_VCPU_CACHE_40BIT_BAR 0x2145c 21367ccd5a2cSjsg #define VCE_LMI_CTRL2 0x21474 21377ccd5a2cSjsg #define VCE_LMI_CTRL 0x21498 21387ccd5a2cSjsg #define VCE_LMI_VM_CTRL 0x214a0 21397ccd5a2cSjsg #define VCE_LMI_SWAP_CNTL 0x214b4 21407ccd5a2cSjsg #define VCE_LMI_SWAP_CNTL1 0x214b8 21417ccd5a2cSjsg #define VCE_LMI_CACHE_CTRL 0x214f4 21427ccd5a2cSjsg 21437ccd5a2cSjsg #define VCE_CMD_NO_OP 0x00000000 21447ccd5a2cSjsg #define VCE_CMD_END 0x00000001 21457ccd5a2cSjsg #define VCE_CMD_IB 0x00000002 21467ccd5a2cSjsg #define VCE_CMD_FENCE 0x00000003 21477ccd5a2cSjsg #define VCE_CMD_TRAP 0x00000004 21487ccd5a2cSjsg #define VCE_CMD_IB_AUTO 0x00000005 21497ccd5a2cSjsg #define VCE_CMD_SEMAPHORE 0x00000006 21507ccd5a2cSjsg 21517ccd5a2cSjsg #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x3398u 21527ccd5a2cSjsg #define ATC_VMID0_PASID_MAPPING 0x339Cu 21537ccd5a2cSjsg #define ATC_VMID_PASID_MAPPING_PASID_MASK (0xFFFF) 21547ccd5a2cSjsg #define ATC_VMID_PASID_MAPPING_PASID_SHIFT 0 21557ccd5a2cSjsg #define ATC_VMID_PASID_MAPPING_VALID_MASK (0x1 << 31) 21567ccd5a2cSjsg #define ATC_VMID_PASID_MAPPING_VALID_SHIFT 31 21577ccd5a2cSjsg 21587ccd5a2cSjsg #define ATC_VM_APERTURE0_CNTL 0x3310u 21597ccd5a2cSjsg #define ATS_ACCESS_MODE_NEVER 0 21607ccd5a2cSjsg #define ATS_ACCESS_MODE_ALWAYS 1 21617ccd5a2cSjsg 21627ccd5a2cSjsg #define ATC_VM_APERTURE0_CNTL2 0x3318u 21637ccd5a2cSjsg #define ATC_VM_APERTURE0_HIGH_ADDR 0x3308u 21647ccd5a2cSjsg #define ATC_VM_APERTURE0_LOW_ADDR 0x3300u 21657ccd5a2cSjsg #define ATC_VM_APERTURE1_CNTL 0x3314u 21667ccd5a2cSjsg #define ATC_VM_APERTURE1_CNTL2 0x331Cu 21677ccd5a2cSjsg #define ATC_VM_APERTURE1_HIGH_ADDR 0x330Cu 21687ccd5a2cSjsg #define ATC_VM_APERTURE1_LOW_ADDR 0x3304u 21697ccd5a2cSjsg 21707ccd5a2cSjsg #define IH_VMID_0_LUT 0x3D40u 21717ccd5a2cSjsg 21727ccd5a2cSjsg #endif 2173