11099013bSjsg /* 21099013bSjsg * Copyright 2010 Advanced Micro Devices, Inc. 31099013bSjsg * 41099013bSjsg * Permission is hereby granted, free of charge, to any person obtaining a 51099013bSjsg * copy of this software and associated documentation files (the "Software"), 61099013bSjsg * to deal in the Software without restriction, including without limitation 71099013bSjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 81099013bSjsg * and/or sell copies of the Software, and to permit persons to whom the 91099013bSjsg * Software is furnished to do so, subject to the following conditions: 101099013bSjsg * 111099013bSjsg * The above copyright notice and this permission notice shall be included in 121099013bSjsg * all copies or substantial portions of the Software. 131099013bSjsg * 141099013bSjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 151099013bSjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 161099013bSjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 171099013bSjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 181099013bSjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 191099013bSjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 201099013bSjsg * OTHER DEALINGS IN THE SOFTWARE. 211099013bSjsg * 221099013bSjsg * Authors: Alex Deucher 231099013bSjsg */ 241099013bSjsg #ifndef NI_H 251099013bSjsg #define NI_H 261099013bSjsg 271099013bSjsg #define CAYMAN_MAX_SH_GPRS 256 281099013bSjsg #define CAYMAN_MAX_TEMP_GPRS 16 291099013bSjsg #define CAYMAN_MAX_SH_THREADS 256 301099013bSjsg #define CAYMAN_MAX_SH_STACK_ENTRIES 4096 311099013bSjsg #define CAYMAN_MAX_FRC_EOV_CNT 16384 321099013bSjsg #define CAYMAN_MAX_BACKENDS 8 331099013bSjsg #define CAYMAN_MAX_BACKENDS_MASK 0xFF 341099013bSjsg #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF 351099013bSjsg #define CAYMAN_MAX_SIMDS 16 361099013bSjsg #define CAYMAN_MAX_SIMDS_MASK 0xFFFF 371099013bSjsg #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF 381099013bSjsg #define CAYMAN_MAX_PIPES 8 391099013bSjsg #define CAYMAN_MAX_PIPES_MASK 0xFF 401099013bSjsg #define CAYMAN_MAX_LDS_NUM 0xFFFF 411099013bSjsg #define CAYMAN_MAX_TCC 16 421099013bSjsg #define CAYMAN_MAX_TCC_MASK 0xFF 431099013bSjsg 441099013bSjsg #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 451099013bSjsg #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 461099013bSjsg 471099013bSjsg #define DMIF_ADDR_CONFIG 0xBD4 481099013bSjsg 497ccd5a2cSjsg /* fusion vce clocks */ 507ccd5a2cSjsg #define CG_ECLK_CNTL 0x620 517ccd5a2cSjsg # define ECLK_DIVIDER_MASK 0x7f 527ccd5a2cSjsg # define ECLK_DIR_CNTL_EN (1 << 8) 537ccd5a2cSjsg #define CG_ECLK_STATUS 0x624 547ccd5a2cSjsg # define ECLK_STATUS (1 << 0) 557ccd5a2cSjsg 561099013bSjsg /* DCE6 only */ 571099013bSjsg #define DMIF_ADDR_CALC 0xC00 581099013bSjsg 591099013bSjsg #define SRBM_GFX_CNTL 0x0E44 601099013bSjsg #define RINGID(x) (((x) & 0x3) << 0) 611099013bSjsg #define VMID(x) (((x) & 0x7) << 0) 621099013bSjsg #define SRBM_STATUS 0x0E50 637ccd5a2cSjsg #define RLC_RQ_PENDING (1 << 3) 647ccd5a2cSjsg #define GRBM_RQ_PENDING (1 << 5) 657ccd5a2cSjsg #define VMC_BUSY (1 << 8) 667ccd5a2cSjsg #define MCB_BUSY (1 << 9) 677ccd5a2cSjsg #define MCB_NON_DISPLAY_BUSY (1 << 10) 687ccd5a2cSjsg #define MCC_BUSY (1 << 11) 697ccd5a2cSjsg #define MCD_BUSY (1 << 12) 707ccd5a2cSjsg #define SEM_BUSY (1 << 14) 717ccd5a2cSjsg #define RLC_BUSY (1 << 15) 727ccd5a2cSjsg #define IH_BUSY (1 << 17) 731099013bSjsg 741099013bSjsg #define SRBM_SOFT_RESET 0x0E60 751099013bSjsg #define SOFT_RESET_BIF (1 << 1) 761099013bSjsg #define SOFT_RESET_CG (1 << 2) 771099013bSjsg #define SOFT_RESET_DC (1 << 5) 781099013bSjsg #define SOFT_RESET_DMA1 (1 << 6) 791099013bSjsg #define SOFT_RESET_GRBM (1 << 8) 801099013bSjsg #define SOFT_RESET_HDP (1 << 9) 811099013bSjsg #define SOFT_RESET_IH (1 << 10) 821099013bSjsg #define SOFT_RESET_MC (1 << 11) 831099013bSjsg #define SOFT_RESET_RLC (1 << 13) 841099013bSjsg #define SOFT_RESET_ROM (1 << 14) 851099013bSjsg #define SOFT_RESET_SEM (1 << 15) 861099013bSjsg #define SOFT_RESET_VMC (1 << 17) 871099013bSjsg #define SOFT_RESET_DMA (1 << 20) 881099013bSjsg #define SOFT_RESET_TST (1 << 21) 891099013bSjsg #define SOFT_RESET_REGBB (1 << 22) 901099013bSjsg #define SOFT_RESET_ORB (1 << 23) 911099013bSjsg 927ccd5a2cSjsg #define SRBM_READ_ERROR 0xE98 937ccd5a2cSjsg #define SRBM_INT_CNTL 0xEA0 947ccd5a2cSjsg #define SRBM_INT_ACK 0xEA8 957ccd5a2cSjsg 967ccd5a2cSjsg #define SRBM_STATUS2 0x0EC4 977ccd5a2cSjsg #define DMA_BUSY (1 << 5) 987ccd5a2cSjsg #define DMA1_BUSY (1 << 6) 997ccd5a2cSjsg 1001099013bSjsg #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 1011099013bSjsg #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 1021099013bSjsg #define RESPONSE_TYPE_MASK 0x000000F0 1031099013bSjsg #define RESPONSE_TYPE_SHIFT 4 1041099013bSjsg #define VM_L2_CNTL 0x1400 1051099013bSjsg #define ENABLE_L2_CACHE (1 << 0) 1061099013bSjsg #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 1071099013bSjsg #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 1081099013bSjsg #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 1091099013bSjsg #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 1101099013bSjsg #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18) 1111099013bSjsg /* CONTEXT1_IDENTITY_ACCESS_MODE 1121099013bSjsg * 0 physical = logical 1131099013bSjsg * 1 logical via context1 page table 1141099013bSjsg * 2 inside identity aperture use translation, outside physical = logical 1151099013bSjsg * 3 inside identity aperture physical = logical, outside use translation 1161099013bSjsg */ 1171099013bSjsg #define VM_L2_CNTL2 0x1404 1181099013bSjsg #define INVALIDATE_ALL_L1_TLBS (1 << 0) 1191099013bSjsg #define INVALIDATE_L2_CACHE (1 << 1) 1201099013bSjsg #define VM_L2_CNTL3 0x1408 1211099013bSjsg #define BANK_SELECT(x) ((x) << 0) 1221099013bSjsg #define CACHE_UPDATE_MODE(x) ((x) << 6) 1231099013bSjsg #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 1241099013bSjsg #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 1251099013bSjsg #define VM_L2_STATUS 0x140C 1261099013bSjsg #define L2_BUSY (1 << 0) 1271099013bSjsg #define VM_CONTEXT0_CNTL 0x1410 1281099013bSjsg #define ENABLE_CONTEXT (1 << 0) 1291099013bSjsg #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 1301099013bSjsg #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 1311099013bSjsg #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 1321099013bSjsg #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 1331099013bSjsg #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 1341099013bSjsg #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 1351099013bSjsg #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 1361099013bSjsg #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 1371099013bSjsg #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 1381099013bSjsg #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 1391099013bSjsg #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 1401099013bSjsg #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 1411099013bSjsg #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 1427ccd5a2cSjsg #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) 1431099013bSjsg #define VM_CONTEXT1_CNTL 0x1414 1441099013bSjsg #define VM_CONTEXT0_CNTL2 0x1430 1451099013bSjsg #define VM_CONTEXT1_CNTL2 0x1434 1461099013bSjsg #define VM_INVALIDATE_REQUEST 0x1478 1471099013bSjsg #define VM_INVALIDATE_RESPONSE 0x147c 1487ccd5a2cSjsg #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 1497ccd5a2cSjsg #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 1507ccd5a2cSjsg #define PROTECTIONS_MASK (0xf << 0) 1517ccd5a2cSjsg #define PROTECTIONS_SHIFT 0 1527ccd5a2cSjsg /* bit 0: range 1537ccd5a2cSjsg * bit 2: pde0 1547ccd5a2cSjsg * bit 3: valid 1557ccd5a2cSjsg * bit 4: read 1567ccd5a2cSjsg * bit 5: write 1577ccd5a2cSjsg */ 1587ccd5a2cSjsg #define MEMORY_CLIENT_ID_MASK (0xff << 12) 1597ccd5a2cSjsg #define MEMORY_CLIENT_ID_SHIFT 12 1607ccd5a2cSjsg #define MEMORY_CLIENT_RW_MASK (1 << 24) 1617ccd5a2cSjsg #define MEMORY_CLIENT_RW_SHIFT 24 1627ccd5a2cSjsg #define FAULT_VMID_MASK (0x7 << 25) 1637ccd5a2cSjsg #define FAULT_VMID_SHIFT 25 1641099013bSjsg #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 1651099013bSjsg #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 1661099013bSjsg #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 1671099013bSjsg #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 1681099013bSjsg #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 1691099013bSjsg 1701099013bSjsg #define MC_SHARED_CHMAP 0x2004 1711099013bSjsg #define NOOFCHAN_SHIFT 12 1721099013bSjsg #define NOOFCHAN_MASK 0x00003000 1731099013bSjsg #define MC_SHARED_CHREMAP 0x2008 1741099013bSjsg 1751099013bSjsg #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 1761099013bSjsg #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 1771099013bSjsg #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 1781099013bSjsg #define MC_VM_MX_L1_TLB_CNTL 0x2064 1791099013bSjsg #define ENABLE_L1_TLB (1 << 0) 1801099013bSjsg #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 1811099013bSjsg #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 1821099013bSjsg #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 1831099013bSjsg #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 1841099013bSjsg #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 1851099013bSjsg #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 1861099013bSjsg #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 1871099013bSjsg #define FUS_MC_VM_FB_OFFSET 0x2068 1881099013bSjsg 1891099013bSjsg #define MC_SHARED_BLACKOUT_CNTL 0x20ac 1901099013bSjsg #define MC_ARB_RAMCFG 0x2760 1911099013bSjsg #define NOOFBANK_SHIFT 0 1921099013bSjsg #define NOOFBANK_MASK 0x00000003 1931099013bSjsg #define NOOFRANK_SHIFT 2 1941099013bSjsg #define NOOFRANK_MASK 0x00000004 1951099013bSjsg #define NOOFROWS_SHIFT 3 1961099013bSjsg #define NOOFROWS_MASK 0x00000038 1971099013bSjsg #define NOOFCOLS_SHIFT 6 1981099013bSjsg #define NOOFCOLS_MASK 0x000000C0 1991099013bSjsg #define CHANSIZE_SHIFT 8 2001099013bSjsg #define CHANSIZE_MASK 0x00000100 2011099013bSjsg #define BURSTLENGTH_SHIFT 9 2021099013bSjsg #define BURSTLENGTH_MASK 0x00000200 2031099013bSjsg #define CHANSIZE_OVERRIDE (1 << 11) 2041099013bSjsg #define MC_SEQ_SUP_CNTL 0x28c8 2051099013bSjsg #define RUN_MASK (1 << 0) 2061099013bSjsg #define MC_SEQ_SUP_PGM 0x28cc 2071099013bSjsg #define MC_IO_PAD_CNTL_D0 0x29d0 2081099013bSjsg #define MEM_FALL_OUT_CMD (1 << 8) 2091099013bSjsg #define MC_SEQ_MISC0 0x2a00 2101099013bSjsg #define MC_SEQ_MISC0_GDDR5_SHIFT 28 2111099013bSjsg #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 2121099013bSjsg #define MC_SEQ_MISC0_GDDR5_VALUE 5 2131099013bSjsg #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 2141099013bSjsg #define MC_SEQ_IO_DEBUG_DATA 0x2a48 2151099013bSjsg 2161099013bSjsg #define HDP_HOST_PATH_CNTL 0x2C00 2171099013bSjsg #define HDP_NONSURFACE_BASE 0x2C04 2181099013bSjsg #define HDP_NONSURFACE_INFO 0x2C08 2191099013bSjsg #define HDP_NONSURFACE_SIZE 0x2C0C 2201099013bSjsg #define HDP_ADDR_CONFIG 0x2F48 2211099013bSjsg #define HDP_MISC_CNTL 0x2F4C 2221099013bSjsg #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 2231099013bSjsg 2241099013bSjsg #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 2251099013bSjsg #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C 2261099013bSjsg #define CGTS_SYS_TCC_DISABLE 0x3F90 2271099013bSjsg #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 2281099013bSjsg 2291099013bSjsg #define RLC_GFX_INDEX 0x3FC4 2301099013bSjsg 2311099013bSjsg #define CONFIG_MEMSIZE 0x5428 2321099013bSjsg 2331099013bSjsg #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 2341099013bSjsg #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 2351099013bSjsg 2361099013bSjsg #define GRBM_CNTL 0x8000 2371099013bSjsg #define GRBM_READ_TIMEOUT(x) ((x) << 0) 2381099013bSjsg #define GRBM_STATUS 0x8010 2391099013bSjsg #define CMDFIFO_AVAIL_MASK 0x0000000F 2401099013bSjsg #define RING2_RQ_PENDING (1 << 4) 2411099013bSjsg #define SRBM_RQ_PENDING (1 << 5) 2421099013bSjsg #define RING1_RQ_PENDING (1 << 6) 2431099013bSjsg #define CF_RQ_PENDING (1 << 7) 2441099013bSjsg #define PF_RQ_PENDING (1 << 8) 2451099013bSjsg #define GDS_DMA_RQ_PENDING (1 << 9) 2461099013bSjsg #define GRBM_EE_BUSY (1 << 10) 2471099013bSjsg #define SX_CLEAN (1 << 11) 2481099013bSjsg #define DB_CLEAN (1 << 12) 2491099013bSjsg #define CB_CLEAN (1 << 13) 2501099013bSjsg #define TA_BUSY (1 << 14) 2511099013bSjsg #define GDS_BUSY (1 << 15) 2521099013bSjsg #define VGT_BUSY_NO_DMA (1 << 16) 2531099013bSjsg #define VGT_BUSY (1 << 17) 2541099013bSjsg #define IA_BUSY_NO_DMA (1 << 18) 2551099013bSjsg #define IA_BUSY (1 << 19) 2561099013bSjsg #define SX_BUSY (1 << 20) 2571099013bSjsg #define SH_BUSY (1 << 21) 2581099013bSjsg #define SPI_BUSY (1 << 22) 2591099013bSjsg #define SC_BUSY (1 << 24) 2601099013bSjsg #define PA_BUSY (1 << 25) 2611099013bSjsg #define DB_BUSY (1 << 26) 2621099013bSjsg #define CP_COHERENCY_BUSY (1 << 28) 2631099013bSjsg #define CP_BUSY (1 << 29) 2641099013bSjsg #define CB_BUSY (1 << 30) 2651099013bSjsg #define GUI_ACTIVE (1 << 31) 2661099013bSjsg #define GRBM_STATUS_SE0 0x8014 2671099013bSjsg #define GRBM_STATUS_SE1 0x8018 2681099013bSjsg #define SE_SX_CLEAN (1 << 0) 2691099013bSjsg #define SE_DB_CLEAN (1 << 1) 2701099013bSjsg #define SE_CB_CLEAN (1 << 2) 2711099013bSjsg #define SE_VGT_BUSY (1 << 23) 2721099013bSjsg #define SE_PA_BUSY (1 << 24) 2731099013bSjsg #define SE_TA_BUSY (1 << 25) 2741099013bSjsg #define SE_SX_BUSY (1 << 26) 2751099013bSjsg #define SE_SPI_BUSY (1 << 27) 2761099013bSjsg #define SE_SH_BUSY (1 << 28) 2771099013bSjsg #define SE_SC_BUSY (1 << 29) 2781099013bSjsg #define SE_DB_BUSY (1 << 30) 2791099013bSjsg #define SE_CB_BUSY (1 << 31) 2801099013bSjsg #define GRBM_SOFT_RESET 0x8020 2811099013bSjsg #define SOFT_RESET_CP (1 << 0) 2821099013bSjsg #define SOFT_RESET_CB (1 << 1) 2831099013bSjsg #define SOFT_RESET_DB (1 << 3) 2841099013bSjsg #define SOFT_RESET_GDS (1 << 4) 2851099013bSjsg #define SOFT_RESET_PA (1 << 5) 2861099013bSjsg #define SOFT_RESET_SC (1 << 6) 2871099013bSjsg #define SOFT_RESET_SPI (1 << 8) 2881099013bSjsg #define SOFT_RESET_SH (1 << 9) 2891099013bSjsg #define SOFT_RESET_SX (1 << 10) 2901099013bSjsg #define SOFT_RESET_TC (1 << 11) 2911099013bSjsg #define SOFT_RESET_TA (1 << 12) 2921099013bSjsg #define SOFT_RESET_VGT (1 << 14) 2931099013bSjsg #define SOFT_RESET_IA (1 << 15) 2941099013bSjsg 2951099013bSjsg #define GRBM_GFX_INDEX 0x802C 2961099013bSjsg #define INSTANCE_INDEX(x) ((x) << 0) 2971099013bSjsg #define SE_INDEX(x) ((x) << 16) 2981099013bSjsg #define INSTANCE_BROADCAST_WRITES (1 << 30) 2991099013bSjsg #define SE_BROADCAST_WRITES (1 << 31) 3001099013bSjsg 3011099013bSjsg #define SCRATCH_REG0 0x8500 3021099013bSjsg #define SCRATCH_REG1 0x8504 3031099013bSjsg #define SCRATCH_REG2 0x8508 3041099013bSjsg #define SCRATCH_REG3 0x850C 3051099013bSjsg #define SCRATCH_REG4 0x8510 3061099013bSjsg #define SCRATCH_REG5 0x8514 3071099013bSjsg #define SCRATCH_REG6 0x8518 3081099013bSjsg #define SCRATCH_REG7 0x851C 3091099013bSjsg #define SCRATCH_UMSK 0x8540 3101099013bSjsg #define SCRATCH_ADDR 0x8544 3111099013bSjsg #define CP_SEM_WAIT_TIMER 0x85BC 3121099013bSjsg #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 3131099013bSjsg #define CP_COHER_CNTL2 0x85E8 3141099013bSjsg #define CP_STALLED_STAT1 0x8674 3151099013bSjsg #define CP_STALLED_STAT2 0x8678 3161099013bSjsg #define CP_BUSY_STAT 0x867C 3171099013bSjsg #define CP_STAT 0x8680 3181099013bSjsg #define CP_ME_CNTL 0x86D8 3191099013bSjsg #define CP_ME_HALT (1 << 28) 3201099013bSjsg #define CP_PFP_HALT (1 << 26) 3211099013bSjsg #define CP_RB2_RPTR 0x86f8 3221099013bSjsg #define CP_RB1_RPTR 0x86fc 3231099013bSjsg #define CP_RB0_RPTR 0x8700 3241099013bSjsg #define CP_RB_WPTR_DELAY 0x8704 3251099013bSjsg #define CP_MEQ_THRESHOLDS 0x8764 3261099013bSjsg #define MEQ1_START(x) ((x) << 0) 3271099013bSjsg #define MEQ2_START(x) ((x) << 8) 3281099013bSjsg #define CP_PERFMON_CNTL 0x87FC 3291099013bSjsg 3301099013bSjsg #define VGT_CACHE_INVALIDATION 0x88C4 3311099013bSjsg #define CACHE_INVALIDATION(x) ((x) << 0) 3321099013bSjsg #define VC_ONLY 0 3331099013bSjsg #define TC_ONLY 1 3341099013bSjsg #define VC_AND_TC 2 3351099013bSjsg #define AUTO_INVLD_EN(x) ((x) << 6) 3361099013bSjsg #define NO_AUTO 0 3371099013bSjsg #define ES_AUTO 1 3381099013bSjsg #define GS_AUTO 2 3391099013bSjsg #define ES_AND_GS_AUTO 3 3401099013bSjsg #define VGT_GS_VERTEX_REUSE 0x88D4 3411099013bSjsg 3421099013bSjsg #define CC_GC_SHADER_PIPE_CONFIG 0x8950 3431099013bSjsg #define GC_USER_SHADER_PIPE_CONFIG 0x8954 3441099013bSjsg #define INACTIVE_QD_PIPES(x) ((x) << 8) 3451099013bSjsg #define INACTIVE_QD_PIPES_MASK 0x0000FF00 3461099013bSjsg #define INACTIVE_QD_PIPES_SHIFT 8 3471099013bSjsg #define INACTIVE_SIMDS(x) ((x) << 16) 3481099013bSjsg #define INACTIVE_SIMDS_MASK 0xFFFF0000 3491099013bSjsg #define INACTIVE_SIMDS_SHIFT 16 3501099013bSjsg 3511099013bSjsg #define VGT_PRIMITIVE_TYPE 0x8958 3521099013bSjsg #define VGT_NUM_INSTANCES 0x8974 3531099013bSjsg #define VGT_TF_RING_SIZE 0x8988 3541099013bSjsg #define VGT_OFFCHIP_LDS_BASE 0x89b4 3551099013bSjsg 3561099013bSjsg #define PA_SC_LINE_STIPPLE_STATE 0x8B10 3571099013bSjsg #define PA_CL_ENHANCE 0x8A14 3581099013bSjsg #define CLIP_VTX_REORDER_ENA (1 << 0) 3591099013bSjsg #define NUM_CLIP_SEQ(x) ((x) << 1) 3601099013bSjsg #define PA_SC_FIFO_SIZE 0x8BCC 3611099013bSjsg #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 3621099013bSjsg #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 3631099013bSjsg #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 3641099013bSjsg #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 3651099013bSjsg #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 3661099013bSjsg #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 3671099013bSjsg 3681099013bSjsg #define SQ_CONFIG 0x8C00 3691099013bSjsg #define VC_ENABLE (1 << 0) 3701099013bSjsg #define EXPORT_SRC_C (1 << 1) 3711099013bSjsg #define GFX_PRIO(x) ((x) << 2) 3721099013bSjsg #define CS1_PRIO(x) ((x) << 4) 3731099013bSjsg #define CS2_PRIO(x) ((x) << 6) 3741099013bSjsg #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 3751099013bSjsg #define NUM_PS_GPRS(x) ((x) << 0) 3761099013bSjsg #define NUM_VS_GPRS(x) ((x) << 16) 3771099013bSjsg #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 3781099013bSjsg #define SQ_ESGS_RING_SIZE 0x8c44 3791099013bSjsg #define SQ_GSVS_RING_SIZE 0x8c4c 3801099013bSjsg #define SQ_ESTMP_RING_BASE 0x8c50 3811099013bSjsg #define SQ_ESTMP_RING_SIZE 0x8c54 3821099013bSjsg #define SQ_GSTMP_RING_BASE 0x8c58 3831099013bSjsg #define SQ_GSTMP_RING_SIZE 0x8c5c 3841099013bSjsg #define SQ_VSTMP_RING_BASE 0x8c60 3851099013bSjsg #define SQ_VSTMP_RING_SIZE 0x8c64 3861099013bSjsg #define SQ_PSTMP_RING_BASE 0x8c68 3871099013bSjsg #define SQ_PSTMP_RING_SIZE 0x8c6c 3881099013bSjsg #define SQ_MS_FIFO_SIZES 0x8CF0 3891099013bSjsg #define CACHE_FIFO_SIZE(x) ((x) << 0) 3901099013bSjsg #define FETCH_FIFO_HIWATER(x) ((x) << 8) 3911099013bSjsg #define DONE_FIFO_HIWATER(x) ((x) << 16) 3921099013bSjsg #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 3931099013bSjsg #define SQ_LSTMP_RING_BASE 0x8e10 3941099013bSjsg #define SQ_LSTMP_RING_SIZE 0x8e14 3951099013bSjsg #define SQ_HSTMP_RING_BASE 0x8e18 3961099013bSjsg #define SQ_HSTMP_RING_SIZE 0x8e1c 3971099013bSjsg #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 3981099013bSjsg #define DYN_GPR_ENABLE (1 << 8) 3991099013bSjsg #define SQ_CONST_MEM_BASE 0x8df8 4001099013bSjsg 4011099013bSjsg #define SX_EXPORT_BUFFER_SIZES 0x900C 4021099013bSjsg #define COLOR_BUFFER_SIZE(x) ((x) << 0) 4031099013bSjsg #define POSITION_BUFFER_SIZE(x) ((x) << 8) 4041099013bSjsg #define SMX_BUFFER_SIZE(x) ((x) << 16) 4051099013bSjsg #define SX_DEBUG_1 0x9058 4061099013bSjsg #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 4071099013bSjsg 4081099013bSjsg #define SPI_CONFIG_CNTL 0x9100 4091099013bSjsg #define GPR_WRITE_PRIORITY(x) ((x) << 0) 4101099013bSjsg #define SPI_CONFIG_CNTL_1 0x913C 4111099013bSjsg #define VTX_DONE_DELAY(x) ((x) << 0) 4121099013bSjsg #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 4131099013bSjsg #define CRC_SIMD_ID_WADDR_DISABLE (1 << 8) 4141099013bSjsg 4151099013bSjsg #define CGTS_TCC_DISABLE 0x9148 4161099013bSjsg #define CGTS_USER_TCC_DISABLE 0x914C 4171099013bSjsg #define TCC_DISABLE_MASK 0xFFFF0000 4181099013bSjsg #define TCC_DISABLE_SHIFT 16 4191099013bSjsg #define CGTS_SM_CTRL_REG 0x9150 4201099013bSjsg #define OVERRIDE (1 << 21) 4211099013bSjsg 4221099013bSjsg #define TA_CNTL_AUX 0x9508 4231099013bSjsg #define DISABLE_CUBE_WRAP (1 << 0) 4241099013bSjsg #define DISABLE_CUBE_ANISO (1 << 1) 4251099013bSjsg 4261099013bSjsg #define TCP_CHAN_STEER_LO 0x960c 4271099013bSjsg #define TCP_CHAN_STEER_HI 0x9610 4281099013bSjsg 4291099013bSjsg #define CC_RB_BACKEND_DISABLE 0x98F4 4301099013bSjsg #define BACKEND_DISABLE(x) ((x) << 16) 4311099013bSjsg #define GB_ADDR_CONFIG 0x98F8 4321099013bSjsg #define NUM_PIPES(x) ((x) << 0) 4331099013bSjsg #define NUM_PIPES_MASK 0x00000007 4341099013bSjsg #define NUM_PIPES_SHIFT 0 4351099013bSjsg #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 4361099013bSjsg #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 4371099013bSjsg #define PIPE_INTERLEAVE_SIZE_SHIFT 4 4381099013bSjsg #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 4391099013bSjsg #define NUM_SHADER_ENGINES(x) ((x) << 12) 4401099013bSjsg #define NUM_SHADER_ENGINES_MASK 0x00003000 4411099013bSjsg #define NUM_SHADER_ENGINES_SHIFT 12 4421099013bSjsg #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 4431099013bSjsg #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 4441099013bSjsg #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 4451099013bSjsg #define NUM_GPUS(x) ((x) << 20) 4461099013bSjsg #define NUM_GPUS_MASK 0x00700000 4471099013bSjsg #define NUM_GPUS_SHIFT 20 4481099013bSjsg #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 4491099013bSjsg #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 4501099013bSjsg #define MULTI_GPU_TILE_SIZE_SHIFT 24 4511099013bSjsg #define ROW_SIZE(x) ((x) << 28) 4521099013bSjsg #define ROW_SIZE_MASK 0x30000000 4531099013bSjsg #define ROW_SIZE_SHIFT 28 4541099013bSjsg #define NUM_LOWER_PIPES(x) ((x) << 30) 4551099013bSjsg #define NUM_LOWER_PIPES_MASK 0x40000000 4561099013bSjsg #define NUM_LOWER_PIPES_SHIFT 30 4571099013bSjsg #define GB_BACKEND_MAP 0x98FC 4581099013bSjsg 4591099013bSjsg #define CB_PERF_CTR0_SEL_0 0x9A20 4601099013bSjsg #define CB_PERF_CTR0_SEL_1 0x9A24 4611099013bSjsg #define CB_PERF_CTR1_SEL_0 0x9A28 4621099013bSjsg #define CB_PERF_CTR1_SEL_1 0x9A2C 4631099013bSjsg #define CB_PERF_CTR2_SEL_0 0x9A30 4641099013bSjsg #define CB_PERF_CTR2_SEL_1 0x9A34 4651099013bSjsg #define CB_PERF_CTR3_SEL_0 0x9A38 4661099013bSjsg #define CB_PERF_CTR3_SEL_1 0x9A3C 4671099013bSjsg 4681099013bSjsg #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 4691099013bSjsg #define BACKEND_DISABLE_MASK 0x00FF0000 4701099013bSjsg #define BACKEND_DISABLE_SHIFT 16 4711099013bSjsg 4721099013bSjsg #define SMX_DC_CTL0 0xA020 4731099013bSjsg #define USE_HASH_FUNCTION (1 << 0) 4741099013bSjsg #define NUMBER_OF_SETS(x) ((x) << 1) 4751099013bSjsg #define FLUSH_ALL_ON_EVENT (1 << 10) 4761099013bSjsg #define STALL_ON_EVENT (1 << 11) 4771099013bSjsg #define SMX_EVENT_CTL 0xA02C 4781099013bSjsg #define ES_FLUSH_CTL(x) ((x) << 0) 4791099013bSjsg #define GS_FLUSH_CTL(x) ((x) << 3) 4801099013bSjsg #define ACK_FLUSH_CTL(x) ((x) << 6) 4811099013bSjsg #define SYNC_FLUSH_CTL (1 << 8) 4821099013bSjsg 4831099013bSjsg #define CP_RB0_BASE 0xC100 4841099013bSjsg #define CP_RB0_CNTL 0xC104 4851099013bSjsg #define RB_BUFSZ(x) ((x) << 0) 4861099013bSjsg #define RB_BLKSZ(x) ((x) << 8) 4871099013bSjsg #define RB_NO_UPDATE (1 << 27) 4881099013bSjsg #define RB_RPTR_WR_ENA (1 << 31) 4891099013bSjsg #define BUF_SWAP_32BIT (2 << 16) 4901099013bSjsg #define CP_RB0_RPTR_ADDR 0xC10C 4911099013bSjsg #define CP_RB0_RPTR_ADDR_HI 0xC110 4921099013bSjsg #define CP_RB0_WPTR 0xC114 4931099013bSjsg 4941099013bSjsg #define CP_INT_CNTL 0xC124 4951099013bSjsg # define CNTX_BUSY_INT_ENABLE (1 << 19) 4961099013bSjsg # define CNTX_EMPTY_INT_ENABLE (1 << 20) 4971099013bSjsg # define TIME_STAMP_INT_ENABLE (1 << 26) 4981099013bSjsg 4991099013bSjsg #define CP_RB1_BASE 0xC180 5001099013bSjsg #define CP_RB1_CNTL 0xC184 5011099013bSjsg #define CP_RB1_RPTR_ADDR 0xC188 5021099013bSjsg #define CP_RB1_RPTR_ADDR_HI 0xC18C 5031099013bSjsg #define CP_RB1_WPTR 0xC190 5041099013bSjsg #define CP_RB2_BASE 0xC194 5051099013bSjsg #define CP_RB2_CNTL 0xC198 5061099013bSjsg #define CP_RB2_RPTR_ADDR 0xC19C 5071099013bSjsg #define CP_RB2_RPTR_ADDR_HI 0xC1A0 5081099013bSjsg #define CP_RB2_WPTR 0xC1A4 5091099013bSjsg #define CP_PFP_UCODE_ADDR 0xC150 5101099013bSjsg #define CP_PFP_UCODE_DATA 0xC154 5111099013bSjsg #define CP_ME_RAM_RADDR 0xC158 5121099013bSjsg #define CP_ME_RAM_WADDR 0xC15C 5131099013bSjsg #define CP_ME_RAM_DATA 0xC160 5141099013bSjsg #define CP_DEBUG 0xC1FC 5151099013bSjsg 5161099013bSjsg #define VGT_EVENT_INITIATOR 0x28a90 5171099013bSjsg # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 5181099013bSjsg # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 5191099013bSjsg 5207ccd5a2cSjsg /* TN SMU registers */ 5217ccd5a2cSjsg #define TN_CURRENT_GNB_TEMP 0x1F390 5227ccd5a2cSjsg 5237ccd5a2cSjsg /* pm registers */ 5247ccd5a2cSjsg #define SMC_MSG 0x20c 5257ccd5a2cSjsg #define HOST_SMC_MSG(x) ((x) << 0) 5267ccd5a2cSjsg #define HOST_SMC_MSG_MASK (0xff << 0) 5277ccd5a2cSjsg #define HOST_SMC_MSG_SHIFT 0 5287ccd5a2cSjsg #define HOST_SMC_RESP(x) ((x) << 8) 5297ccd5a2cSjsg #define HOST_SMC_RESP_MASK (0xff << 8) 5307ccd5a2cSjsg #define HOST_SMC_RESP_SHIFT 8 5317ccd5a2cSjsg #define SMC_HOST_MSG(x) ((x) << 16) 5327ccd5a2cSjsg #define SMC_HOST_MSG_MASK (0xff << 16) 5337ccd5a2cSjsg #define SMC_HOST_MSG_SHIFT 16 5347ccd5a2cSjsg #define SMC_HOST_RESP(x) ((x) << 24) 5357ccd5a2cSjsg #define SMC_HOST_RESP_MASK (0xff << 24) 5367ccd5a2cSjsg #define SMC_HOST_RESP_SHIFT 24 5377ccd5a2cSjsg 5387ccd5a2cSjsg #define CG_SPLL_FUNC_CNTL 0x600 5397ccd5a2cSjsg #define SPLL_RESET (1 << 0) 5407ccd5a2cSjsg #define SPLL_SLEEP (1 << 1) 5417ccd5a2cSjsg #define SPLL_BYPASS_EN (1 << 3) 5427ccd5a2cSjsg #define SPLL_REF_DIV(x) ((x) << 4) 5437ccd5a2cSjsg #define SPLL_REF_DIV_MASK (0x3f << 4) 5447ccd5a2cSjsg #define SPLL_PDIV_A(x) ((x) << 20) 5457ccd5a2cSjsg #define SPLL_PDIV_A_MASK (0x7f << 20) 5467ccd5a2cSjsg #define SPLL_PDIV_A_SHIFT 20 5477ccd5a2cSjsg #define CG_SPLL_FUNC_CNTL_2 0x604 5487ccd5a2cSjsg #define SCLK_MUX_SEL(x) ((x) << 0) 5497ccd5a2cSjsg #define SCLK_MUX_SEL_MASK (0x1ff << 0) 5507ccd5a2cSjsg #define CG_SPLL_FUNC_CNTL_3 0x608 5517ccd5a2cSjsg #define SPLL_FB_DIV(x) ((x) << 0) 5527ccd5a2cSjsg #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 5537ccd5a2cSjsg #define SPLL_FB_DIV_SHIFT 0 5547ccd5a2cSjsg #define SPLL_DITHEN (1 << 28) 5557ccd5a2cSjsg 5567ccd5a2cSjsg #define MPLL_CNTL_MODE 0x61c 5577ccd5a2cSjsg # define SS_SSEN (1 << 24) 5587ccd5a2cSjsg # define SS_DSMODE_EN (1 << 25) 5597ccd5a2cSjsg 5607ccd5a2cSjsg #define MPLL_AD_FUNC_CNTL 0x624 5617ccd5a2cSjsg #define CLKF(x) ((x) << 0) 5627ccd5a2cSjsg #define CLKF_MASK (0x7f << 0) 5637ccd5a2cSjsg #define CLKR(x) ((x) << 7) 5647ccd5a2cSjsg #define CLKR_MASK (0x1f << 7) 5657ccd5a2cSjsg #define CLKFRAC(x) ((x) << 12) 5667ccd5a2cSjsg #define CLKFRAC_MASK (0x1f << 12) 5677ccd5a2cSjsg #define YCLK_POST_DIV(x) ((x) << 17) 5687ccd5a2cSjsg #define YCLK_POST_DIV_MASK (3 << 17) 5697ccd5a2cSjsg #define IBIAS(x) ((x) << 20) 5707ccd5a2cSjsg #define IBIAS_MASK (0x3ff << 20) 5717ccd5a2cSjsg #define RESET (1 << 30) 5727ccd5a2cSjsg #define PDNB (1 << 31) 5737ccd5a2cSjsg #define MPLL_AD_FUNC_CNTL_2 0x628 5747ccd5a2cSjsg #define BYPASS (1 << 19) 5757ccd5a2cSjsg #define BIAS_GEN_PDNB (1 << 24) 5767ccd5a2cSjsg #define RESET_EN (1 << 25) 5777ccd5a2cSjsg #define VCO_MODE (1 << 29) 5787ccd5a2cSjsg #define MPLL_DQ_FUNC_CNTL 0x62c 5797ccd5a2cSjsg #define MPLL_DQ_FUNC_CNTL_2 0x630 5807ccd5a2cSjsg 5817ccd5a2cSjsg #define GENERAL_PWRMGT 0x63c 5827ccd5a2cSjsg # define GLOBAL_PWRMGT_EN (1 << 0) 5837ccd5a2cSjsg # define STATIC_PM_EN (1 << 1) 5847ccd5a2cSjsg # define THERMAL_PROTECTION_DIS (1 << 2) 5857ccd5a2cSjsg # define THERMAL_PROTECTION_TYPE (1 << 3) 5867ccd5a2cSjsg # define ENABLE_GEN2PCIE (1 << 4) 5877ccd5a2cSjsg # define ENABLE_GEN2XSP (1 << 5) 5887ccd5a2cSjsg # define SW_SMIO_INDEX(x) ((x) << 6) 5897ccd5a2cSjsg # define SW_SMIO_INDEX_MASK (3 << 6) 5907ccd5a2cSjsg # define SW_SMIO_INDEX_SHIFT 6 5917ccd5a2cSjsg # define LOW_VOLT_D2_ACPI (1 << 8) 5927ccd5a2cSjsg # define LOW_VOLT_D3_ACPI (1 << 9) 5937ccd5a2cSjsg # define VOLT_PWRMGT_EN (1 << 10) 5947ccd5a2cSjsg # define BACKBIAS_PAD_EN (1 << 18) 5957ccd5a2cSjsg # define BACKBIAS_VALUE (1 << 19) 5967ccd5a2cSjsg # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 5977ccd5a2cSjsg # define AC_DC_SW (1 << 24) 5987ccd5a2cSjsg 5997ccd5a2cSjsg #define SCLK_PWRMGT_CNTL 0x644 6007ccd5a2cSjsg # define SCLK_PWRMGT_OFF (1 << 0) 6017ccd5a2cSjsg # define SCLK_LOW_D1 (1 << 1) 6027ccd5a2cSjsg # define FIR_RESET (1 << 4) 6037ccd5a2cSjsg # define FIR_FORCE_TREND_SEL (1 << 5) 6047ccd5a2cSjsg # define FIR_TREND_MODE (1 << 6) 6057ccd5a2cSjsg # define DYN_GFX_CLK_OFF_EN (1 << 7) 6067ccd5a2cSjsg # define GFX_CLK_FORCE_ON (1 << 8) 6077ccd5a2cSjsg # define GFX_CLK_REQUEST_OFF (1 << 9) 6087ccd5a2cSjsg # define GFX_CLK_FORCE_OFF (1 << 10) 6097ccd5a2cSjsg # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 6107ccd5a2cSjsg # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 6117ccd5a2cSjsg # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 6127ccd5a2cSjsg # define DYN_LIGHT_SLEEP_EN (1 << 14) 6137ccd5a2cSjsg #define MCLK_PWRMGT_CNTL 0x648 6147ccd5a2cSjsg # define DLL_SPEED(x) ((x) << 0) 6157ccd5a2cSjsg # define DLL_SPEED_MASK (0x1f << 0) 6167ccd5a2cSjsg # define MPLL_PWRMGT_OFF (1 << 5) 6177ccd5a2cSjsg # define DLL_READY (1 << 6) 6187ccd5a2cSjsg # define MC_INT_CNTL (1 << 7) 6197ccd5a2cSjsg # define MRDCKA0_PDNB (1 << 8) 6207ccd5a2cSjsg # define MRDCKA1_PDNB (1 << 9) 6217ccd5a2cSjsg # define MRDCKB0_PDNB (1 << 10) 6227ccd5a2cSjsg # define MRDCKB1_PDNB (1 << 11) 6237ccd5a2cSjsg # define MRDCKC0_PDNB (1 << 12) 6247ccd5a2cSjsg # define MRDCKC1_PDNB (1 << 13) 6257ccd5a2cSjsg # define MRDCKD0_PDNB (1 << 14) 6267ccd5a2cSjsg # define MRDCKD1_PDNB (1 << 15) 6277ccd5a2cSjsg # define MRDCKA0_RESET (1 << 16) 6287ccd5a2cSjsg # define MRDCKA1_RESET (1 << 17) 6297ccd5a2cSjsg # define MRDCKB0_RESET (1 << 18) 6307ccd5a2cSjsg # define MRDCKB1_RESET (1 << 19) 6317ccd5a2cSjsg # define MRDCKC0_RESET (1 << 20) 6327ccd5a2cSjsg # define MRDCKC1_RESET (1 << 21) 6337ccd5a2cSjsg # define MRDCKD0_RESET (1 << 22) 6347ccd5a2cSjsg # define MRDCKD1_RESET (1 << 23) 6357ccd5a2cSjsg # define DLL_READY_READ (1 << 24) 6367ccd5a2cSjsg # define USE_DISPLAY_GAP (1 << 25) 6377ccd5a2cSjsg # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 6387ccd5a2cSjsg # define MPLL_TURNOFF_D2 (1 << 28) 6397ccd5a2cSjsg #define DLL_CNTL 0x64c 6407ccd5a2cSjsg # define MRDCKA0_BYPASS (1 << 24) 6417ccd5a2cSjsg # define MRDCKA1_BYPASS (1 << 25) 6427ccd5a2cSjsg # define MRDCKB0_BYPASS (1 << 26) 6437ccd5a2cSjsg # define MRDCKB1_BYPASS (1 << 27) 6447ccd5a2cSjsg # define MRDCKC0_BYPASS (1 << 28) 6457ccd5a2cSjsg # define MRDCKC1_BYPASS (1 << 29) 6467ccd5a2cSjsg # define MRDCKD0_BYPASS (1 << 30) 6477ccd5a2cSjsg # define MRDCKD1_BYPASS (1 << 31) 6487ccd5a2cSjsg 6497ccd5a2cSjsg #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c 6507ccd5a2cSjsg # define CURRENT_STATE_INDEX_MASK (0xf << 4) 6517ccd5a2cSjsg # define CURRENT_STATE_INDEX_SHIFT 4 6527ccd5a2cSjsg 6537ccd5a2cSjsg #define CG_AT 0x6d4 6547ccd5a2cSjsg # define CG_R(x) ((x) << 0) 6557ccd5a2cSjsg # define CG_R_MASK (0xffff << 0) 6567ccd5a2cSjsg # define CG_L(x) ((x) << 16) 6577ccd5a2cSjsg # define CG_L_MASK (0xffff << 16) 6587ccd5a2cSjsg 6597ccd5a2cSjsg #define CG_BIF_REQ_AND_RSP 0x7f4 6607ccd5a2cSjsg #define CG_CLIENT_REQ(x) ((x) << 0) 6617ccd5a2cSjsg #define CG_CLIENT_REQ_MASK (0xff << 0) 6627ccd5a2cSjsg #define CG_CLIENT_REQ_SHIFT 0 6637ccd5a2cSjsg #define CG_CLIENT_RESP(x) ((x) << 8) 6647ccd5a2cSjsg #define CG_CLIENT_RESP_MASK (0xff << 8) 6657ccd5a2cSjsg #define CG_CLIENT_RESP_SHIFT 8 6667ccd5a2cSjsg #define CLIENT_CG_REQ(x) ((x) << 16) 6677ccd5a2cSjsg #define CLIENT_CG_REQ_MASK (0xff << 16) 6687ccd5a2cSjsg #define CLIENT_CG_REQ_SHIFT 16 6697ccd5a2cSjsg #define CLIENT_CG_RESP(x) ((x) << 24) 6707ccd5a2cSjsg #define CLIENT_CG_RESP_MASK (0xff << 24) 6717ccd5a2cSjsg #define CLIENT_CG_RESP_SHIFT 24 6727ccd5a2cSjsg 6737ccd5a2cSjsg #define CG_SPLL_SPREAD_SPECTRUM 0x790 6747ccd5a2cSjsg #define SSEN (1 << 0) 6757ccd5a2cSjsg #define CLK_S(x) ((x) << 4) 6767ccd5a2cSjsg #define CLK_S_MASK (0xfff << 4) 6777ccd5a2cSjsg #define CLK_S_SHIFT 4 6787ccd5a2cSjsg #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 6797ccd5a2cSjsg #define CLK_V(x) ((x) << 0) 6807ccd5a2cSjsg #define CLK_V_MASK (0x3ffffff << 0) 6817ccd5a2cSjsg #define CLK_V_SHIFT 0 6827ccd5a2cSjsg 6837ccd5a2cSjsg #define SMC_SCRATCH0 0x81c 6847ccd5a2cSjsg 6857ccd5a2cSjsg #define CG_SPLL_FUNC_CNTL_4 0x850 6867ccd5a2cSjsg 6877ccd5a2cSjsg #define MPLL_SS1 0x85c 6887ccd5a2cSjsg #define CLKV(x) ((x) << 0) 6897ccd5a2cSjsg #define CLKV_MASK (0x3ffffff << 0) 6907ccd5a2cSjsg #define MPLL_SS2 0x860 6917ccd5a2cSjsg #define CLKS(x) ((x) << 0) 6927ccd5a2cSjsg #define CLKS_MASK (0xfff << 0) 6937ccd5a2cSjsg 6947ccd5a2cSjsg #define CG_CAC_CTRL 0x88c 6957ccd5a2cSjsg #define TID_CNT(x) ((x) << 0) 6967ccd5a2cSjsg #define TID_CNT_MASK (0x3fff << 0) 6977ccd5a2cSjsg #define TID_UNIT(x) ((x) << 14) 6987ccd5a2cSjsg #define TID_UNIT_MASK (0xf << 14) 6997ccd5a2cSjsg 7007ccd5a2cSjsg #define CG_IND_ADDR 0x8f8 7017ccd5a2cSjsg #define CG_IND_DATA 0x8fc 7027ccd5a2cSjsg /* CGIND regs */ 7037ccd5a2cSjsg #define CG_CGTT_LOCAL_0 0x00 7047ccd5a2cSjsg #define CG_CGTT_LOCAL_1 0x01 7057ccd5a2cSjsg 7067ccd5a2cSjsg #define MC_CG_CONFIG 0x25bc 7077ccd5a2cSjsg #define MCDW_WR_ENABLE (1 << 0) 7087ccd5a2cSjsg #define MCDX_WR_ENABLE (1 << 1) 7097ccd5a2cSjsg #define MCDY_WR_ENABLE (1 << 2) 7107ccd5a2cSjsg #define MCDZ_WR_ENABLE (1 << 3) 7117ccd5a2cSjsg #define MC_RD_ENABLE(x) ((x) << 4) 7127ccd5a2cSjsg #define MC_RD_ENABLE_MASK (3 << 4) 7137ccd5a2cSjsg #define INDEX(x) ((x) << 6) 7147ccd5a2cSjsg #define INDEX_MASK (0xfff << 6) 7157ccd5a2cSjsg #define INDEX_SHIFT 6 7167ccd5a2cSjsg 7177ccd5a2cSjsg #define MC_ARB_CAC_CNTL 0x2750 7187ccd5a2cSjsg #define ENABLE (1 << 0) 7197ccd5a2cSjsg #define READ_WEIGHT(x) ((x) << 1) 7207ccd5a2cSjsg #define READ_WEIGHT_MASK (0x3f << 1) 7217ccd5a2cSjsg #define READ_WEIGHT_SHIFT 1 7227ccd5a2cSjsg #define WRITE_WEIGHT(x) ((x) << 7) 7237ccd5a2cSjsg #define WRITE_WEIGHT_MASK (0x3f << 7) 7247ccd5a2cSjsg #define WRITE_WEIGHT_SHIFT 7 7257ccd5a2cSjsg #define ALLOW_OVERFLOW (1 << 13) 7267ccd5a2cSjsg 7277ccd5a2cSjsg #define MC_ARB_DRAM_TIMING 0x2774 7287ccd5a2cSjsg #define MC_ARB_DRAM_TIMING2 0x2778 7297ccd5a2cSjsg 7307ccd5a2cSjsg #define MC_ARB_RFSH_RATE 0x27b0 7317ccd5a2cSjsg #define POWERMODE0(x) ((x) << 0) 7327ccd5a2cSjsg #define POWERMODE0_MASK (0xff << 0) 7337ccd5a2cSjsg #define POWERMODE0_SHIFT 0 7347ccd5a2cSjsg #define POWERMODE1(x) ((x) << 8) 7357ccd5a2cSjsg #define POWERMODE1_MASK (0xff << 8) 7367ccd5a2cSjsg #define POWERMODE1_SHIFT 8 7377ccd5a2cSjsg #define POWERMODE2(x) ((x) << 16) 7387ccd5a2cSjsg #define POWERMODE2_MASK (0xff << 16) 7397ccd5a2cSjsg #define POWERMODE2_SHIFT 16 7407ccd5a2cSjsg #define POWERMODE3(x) ((x) << 24) 7417ccd5a2cSjsg #define POWERMODE3_MASK (0xff << 24) 7427ccd5a2cSjsg #define POWERMODE3_SHIFT 24 7437ccd5a2cSjsg 7447ccd5a2cSjsg #define MC_ARB_CG 0x27e8 7457ccd5a2cSjsg #define CG_ARB_REQ(x) ((x) << 0) 7467ccd5a2cSjsg #define CG_ARB_REQ_MASK (0xff << 0) 7477ccd5a2cSjsg #define CG_ARB_REQ_SHIFT 0 7487ccd5a2cSjsg #define CG_ARB_RESP(x) ((x) << 8) 7497ccd5a2cSjsg #define CG_ARB_RESP_MASK (0xff << 8) 7507ccd5a2cSjsg #define CG_ARB_RESP_SHIFT 8 7517ccd5a2cSjsg #define ARB_CG_REQ(x) ((x) << 16) 7527ccd5a2cSjsg #define ARB_CG_REQ_MASK (0xff << 16) 7537ccd5a2cSjsg #define ARB_CG_REQ_SHIFT 16 7547ccd5a2cSjsg #define ARB_CG_RESP(x) ((x) << 24) 7557ccd5a2cSjsg #define ARB_CG_RESP_MASK (0xff << 24) 7567ccd5a2cSjsg #define ARB_CG_RESP_SHIFT 24 7577ccd5a2cSjsg 7587ccd5a2cSjsg #define MC_ARB_DRAM_TIMING_1 0x27f0 7597ccd5a2cSjsg #define MC_ARB_DRAM_TIMING_2 0x27f4 7607ccd5a2cSjsg #define MC_ARB_DRAM_TIMING_3 0x27f8 7617ccd5a2cSjsg #define MC_ARB_DRAM_TIMING2_1 0x27fc 7627ccd5a2cSjsg #define MC_ARB_DRAM_TIMING2_2 0x2800 7637ccd5a2cSjsg #define MC_ARB_DRAM_TIMING2_3 0x2804 7647ccd5a2cSjsg #define MC_ARB_BURST_TIME 0x2808 7657ccd5a2cSjsg #define STATE0(x) ((x) << 0) 7667ccd5a2cSjsg #define STATE0_MASK (0x1f << 0) 7677ccd5a2cSjsg #define STATE0_SHIFT 0 7687ccd5a2cSjsg #define STATE1(x) ((x) << 5) 7697ccd5a2cSjsg #define STATE1_MASK (0x1f << 5) 7707ccd5a2cSjsg #define STATE1_SHIFT 5 7717ccd5a2cSjsg #define STATE2(x) ((x) << 10) 7727ccd5a2cSjsg #define STATE2_MASK (0x1f << 10) 7737ccd5a2cSjsg #define STATE2_SHIFT 10 7747ccd5a2cSjsg #define STATE3(x) ((x) << 15) 7757ccd5a2cSjsg #define STATE3_MASK (0x1f << 15) 7767ccd5a2cSjsg #define STATE3_SHIFT 15 7777ccd5a2cSjsg 7787ccd5a2cSjsg #define MC_CG_DATAPORT 0x2884 7797ccd5a2cSjsg 7807ccd5a2cSjsg #define MC_SEQ_RAS_TIMING 0x28a0 7817ccd5a2cSjsg #define MC_SEQ_CAS_TIMING 0x28a4 7827ccd5a2cSjsg #define MC_SEQ_MISC_TIMING 0x28a8 7837ccd5a2cSjsg #define MC_SEQ_MISC_TIMING2 0x28ac 7847ccd5a2cSjsg #define MC_SEQ_PMG_TIMING 0x28b0 7857ccd5a2cSjsg #define MC_SEQ_RD_CTL_D0 0x28b4 7867ccd5a2cSjsg #define MC_SEQ_RD_CTL_D1 0x28b8 7877ccd5a2cSjsg #define MC_SEQ_WR_CTL_D0 0x28bc 7887ccd5a2cSjsg #define MC_SEQ_WR_CTL_D1 0x28c0 7897ccd5a2cSjsg 7907ccd5a2cSjsg #define MC_SEQ_MISC0 0x2a00 7917ccd5a2cSjsg #define MC_SEQ_MISC0_GDDR5_SHIFT 28 7927ccd5a2cSjsg #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 7937ccd5a2cSjsg #define MC_SEQ_MISC0_GDDR5_VALUE 5 7947ccd5a2cSjsg #define MC_SEQ_MISC1 0x2a04 7957ccd5a2cSjsg #define MC_SEQ_RESERVE_M 0x2a08 7967ccd5a2cSjsg #define MC_PMG_CMD_EMRS 0x2a0c 7977ccd5a2cSjsg 7987ccd5a2cSjsg #define MC_SEQ_MISC3 0x2a2c 7997ccd5a2cSjsg 8007ccd5a2cSjsg #define MC_SEQ_MISC5 0x2a54 8017ccd5a2cSjsg #define MC_SEQ_MISC6 0x2a58 8027ccd5a2cSjsg 8037ccd5a2cSjsg #define MC_SEQ_MISC7 0x2a64 8047ccd5a2cSjsg 8057ccd5a2cSjsg #define MC_SEQ_RAS_TIMING_LP 0x2a6c 8067ccd5a2cSjsg #define MC_SEQ_CAS_TIMING_LP 0x2a70 8077ccd5a2cSjsg #define MC_SEQ_MISC_TIMING_LP 0x2a74 8087ccd5a2cSjsg #define MC_SEQ_MISC_TIMING2_LP 0x2a78 8097ccd5a2cSjsg #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 8107ccd5a2cSjsg #define MC_SEQ_WR_CTL_D1_LP 0x2a80 8117ccd5a2cSjsg #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 8127ccd5a2cSjsg #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 8137ccd5a2cSjsg 8147ccd5a2cSjsg #define MC_PMG_CMD_MRS 0x2aac 8157ccd5a2cSjsg 8167ccd5a2cSjsg #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 8177ccd5a2cSjsg #define MC_SEQ_RD_CTL_D1_LP 0x2b20 8187ccd5a2cSjsg 8197ccd5a2cSjsg #define MC_PMG_CMD_MRS1 0x2b44 8207ccd5a2cSjsg #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 8217ccd5a2cSjsg #define MC_SEQ_PMG_TIMING_LP 0x2b4c 8227ccd5a2cSjsg 8237ccd5a2cSjsg #define MC_PMG_CMD_MRS2 0x2b5c 8247ccd5a2cSjsg #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 8257ccd5a2cSjsg 8263253c27bSkettenis #define AUX_CONTROL 0x6200 8273253c27bSkettenis #define AUX_EN (1 << 0) 8283253c27bSkettenis #define AUX_LS_READ_EN (1 << 8) 8293253c27bSkettenis #define AUX_LS_UPDATE_DISABLE(x) (((x) & 0x1) << 12) 8303253c27bSkettenis #define AUX_HPD_DISCON(x) (((x) & 0x1) << 16) 8313253c27bSkettenis #define AUX_DET_EN (1 << 18) 8323253c27bSkettenis #define AUX_HPD_SEL(x) (((x) & 0x7) << 20) 8333253c27bSkettenis #define AUX_IMPCAL_REQ_EN (1 << 24) 8343253c27bSkettenis #define AUX_TEST_MODE (1 << 28) 8353253c27bSkettenis #define AUX_DEGLITCH_EN (1 << 29) 8363253c27bSkettenis #define AUX_SW_CONTROL 0x6204 8373253c27bSkettenis #define AUX_SW_GO (1 << 0) 8383253c27bSkettenis #define AUX_LS_READ_TRIG (1 << 2) 8393253c27bSkettenis #define AUX_SW_START_DELAY(x) (((x) & 0xf) << 4) 8403253c27bSkettenis #define AUX_SW_WR_BYTES(x) (((x) & 0x1f) << 16) 8413253c27bSkettenis 8423253c27bSkettenis #define AUX_SW_INTERRUPT_CONTROL 0x620c 8433253c27bSkettenis #define AUX_SW_DONE_INT (1 << 0) 8443253c27bSkettenis #define AUX_SW_DONE_ACK (1 << 1) 8453253c27bSkettenis #define AUX_SW_DONE_MASK (1 << 2) 8463253c27bSkettenis #define AUX_SW_LS_DONE_INT (1 << 4) 8473253c27bSkettenis #define AUX_SW_LS_DONE_MASK (1 << 6) 8483253c27bSkettenis #define AUX_SW_STATUS 0x6210 8493253c27bSkettenis #define AUX_SW_DONE (1 << 0) 8503253c27bSkettenis #define AUX_SW_REQ (1 << 1) 8513253c27bSkettenis #define AUX_SW_RX_TIMEOUT_STATE(x) (((x) & 0x7) << 4) 8523253c27bSkettenis #define AUX_SW_RX_TIMEOUT (1 << 7) 8533253c27bSkettenis #define AUX_SW_RX_OVERFLOW (1 << 8) 8543253c27bSkettenis #define AUX_SW_RX_HPD_DISCON (1 << 9) 8553253c27bSkettenis #define AUX_SW_RX_PARTIAL_BYTE (1 << 10) 8563253c27bSkettenis #define AUX_SW_NON_AUX_MODE (1 << 11) 8573253c27bSkettenis #define AUX_SW_RX_MIN_COUNT_VIOL (1 << 12) 8583253c27bSkettenis #define AUX_SW_RX_INVALID_STOP (1 << 14) 8593253c27bSkettenis #define AUX_SW_RX_SYNC_INVALID_L (1 << 17) 8603253c27bSkettenis #define AUX_SW_RX_SYNC_INVALID_H (1 << 18) 8613253c27bSkettenis #define AUX_SW_RX_INVALID_START (1 << 19) 8623253c27bSkettenis #define AUX_SW_RX_RECV_NO_DET (1 << 20) 8633253c27bSkettenis #define AUX_SW_RX_RECV_INVALID_H (1 << 22) 8643253c27bSkettenis #define AUX_SW_RX_RECV_INVALID_V (1 << 23) 8653253c27bSkettenis 8663253c27bSkettenis #define AUX_SW_DATA 0x6218 8673253c27bSkettenis #define AUX_SW_DATA_RW (1 << 0) 8683253c27bSkettenis #define AUX_SW_DATA_MASK(x) (((x) & 0xff) << 8) 8693253c27bSkettenis #define AUX_SW_DATA_INDEX(x) (((x) & 0x1f) << 16) 8703253c27bSkettenis #define AUX_SW_AUTOINCREMENT_DISABLE (1 << 31) 8713253c27bSkettenis 8727ccd5a2cSjsg #define LB_SYNC_RESET_SEL 0x6b28 8737ccd5a2cSjsg #define LB_SYNC_RESET_SEL_MASK (3 << 0) 8747ccd5a2cSjsg #define LB_SYNC_RESET_SEL_SHIFT 0 8757ccd5a2cSjsg 8767ccd5a2cSjsg #define DC_STUTTER_CNTL 0x6b30 8777ccd5a2cSjsg #define DC_STUTTER_ENABLE_A (1 << 0) 8787ccd5a2cSjsg #define DC_STUTTER_ENABLE_B (1 << 1) 8797ccd5a2cSjsg 8807ccd5a2cSjsg #define SQ_CAC_THRESHOLD 0x8e4c 8817ccd5a2cSjsg #define VSP(x) ((x) << 0) 8827ccd5a2cSjsg #define VSP_MASK (0xff << 0) 8837ccd5a2cSjsg #define VSP_SHIFT 0 8847ccd5a2cSjsg #define VSP0(x) ((x) << 8) 8857ccd5a2cSjsg #define VSP0_MASK (0xff << 8) 8867ccd5a2cSjsg #define VSP0_SHIFT 8 8877ccd5a2cSjsg #define GPR(x) ((x) << 16) 8887ccd5a2cSjsg #define GPR_MASK (0xff << 16) 8897ccd5a2cSjsg #define GPR_SHIFT 16 8907ccd5a2cSjsg 8917ccd5a2cSjsg #define SQ_POWER_THROTTLE 0x8e58 8927ccd5a2cSjsg #define MIN_POWER(x) ((x) << 0) 8937ccd5a2cSjsg #define MIN_POWER_MASK (0x3fff << 0) 8947ccd5a2cSjsg #define MIN_POWER_SHIFT 0 8957ccd5a2cSjsg #define MAX_POWER(x) ((x) << 16) 8967ccd5a2cSjsg #define MAX_POWER_MASK (0x3fff << 16) 8977ccd5a2cSjsg #define MAX_POWER_SHIFT 0 8987ccd5a2cSjsg #define SQ_POWER_THROTTLE2 0x8e5c 8997ccd5a2cSjsg #define MAX_POWER_DELTA(x) ((x) << 0) 9007ccd5a2cSjsg #define MAX_POWER_DELTA_MASK (0x3fff << 0) 9017ccd5a2cSjsg #define MAX_POWER_DELTA_SHIFT 0 9027ccd5a2cSjsg #define STI_SIZE(x) ((x) << 16) 9037ccd5a2cSjsg #define STI_SIZE_MASK (0x3ff << 16) 9047ccd5a2cSjsg #define STI_SIZE_SHIFT 16 9057ccd5a2cSjsg #define LTI_RATIO(x) ((x) << 27) 9067ccd5a2cSjsg #define LTI_RATIO_MASK (0xf << 27) 9077ccd5a2cSjsg #define LTI_RATIO_SHIFT 27 9087ccd5a2cSjsg 9097ccd5a2cSjsg /* CG indirect registers */ 9107ccd5a2cSjsg #define CG_CAC_REGION_1_WEIGHT_0 0x83 9117ccd5a2cSjsg #define WEIGHT_TCP_SIG0(x) ((x) << 0) 9127ccd5a2cSjsg #define WEIGHT_TCP_SIG0_MASK (0x3f << 0) 9137ccd5a2cSjsg #define WEIGHT_TCP_SIG0_SHIFT 0 9147ccd5a2cSjsg #define WEIGHT_TCP_SIG1(x) ((x) << 6) 9157ccd5a2cSjsg #define WEIGHT_TCP_SIG1_MASK (0x3f << 6) 9167ccd5a2cSjsg #define WEIGHT_TCP_SIG1_SHIFT 6 9177ccd5a2cSjsg #define WEIGHT_TA_SIG(x) ((x) << 12) 9187ccd5a2cSjsg #define WEIGHT_TA_SIG_MASK (0x3f << 12) 9197ccd5a2cSjsg #define WEIGHT_TA_SIG_SHIFT 12 9207ccd5a2cSjsg #define CG_CAC_REGION_1_WEIGHT_1 0x84 9217ccd5a2cSjsg #define WEIGHT_TCC_EN0(x) ((x) << 0) 9227ccd5a2cSjsg #define WEIGHT_TCC_EN0_MASK (0x3f << 0) 9237ccd5a2cSjsg #define WEIGHT_TCC_EN0_SHIFT 0 9247ccd5a2cSjsg #define WEIGHT_TCC_EN1(x) ((x) << 6) 9257ccd5a2cSjsg #define WEIGHT_TCC_EN1_MASK (0x3f << 6) 9267ccd5a2cSjsg #define WEIGHT_TCC_EN1_SHIFT 6 9277ccd5a2cSjsg #define WEIGHT_TCC_EN2(x) ((x) << 12) 9287ccd5a2cSjsg #define WEIGHT_TCC_EN2_MASK (0x3f << 12) 9297ccd5a2cSjsg #define WEIGHT_TCC_EN2_SHIFT 12 9307ccd5a2cSjsg #define WEIGHT_TCC_EN3(x) ((x) << 18) 9317ccd5a2cSjsg #define WEIGHT_TCC_EN3_MASK (0x3f << 18) 9327ccd5a2cSjsg #define WEIGHT_TCC_EN3_SHIFT 18 9337ccd5a2cSjsg #define CG_CAC_REGION_2_WEIGHT_0 0x85 9347ccd5a2cSjsg #define WEIGHT_CB_EN0(x) ((x) << 0) 9357ccd5a2cSjsg #define WEIGHT_CB_EN0_MASK (0x3f << 0) 9367ccd5a2cSjsg #define WEIGHT_CB_EN0_SHIFT 0 9377ccd5a2cSjsg #define WEIGHT_CB_EN1(x) ((x) << 6) 9387ccd5a2cSjsg #define WEIGHT_CB_EN1_MASK (0x3f << 6) 9397ccd5a2cSjsg #define WEIGHT_CB_EN1_SHIFT 6 9407ccd5a2cSjsg #define WEIGHT_CB_EN2(x) ((x) << 12) 9417ccd5a2cSjsg #define WEIGHT_CB_EN2_MASK (0x3f << 12) 9427ccd5a2cSjsg #define WEIGHT_CB_EN2_SHIFT 12 9437ccd5a2cSjsg #define WEIGHT_CB_EN3(x) ((x) << 18) 9447ccd5a2cSjsg #define WEIGHT_CB_EN3_MASK (0x3f << 18) 9457ccd5a2cSjsg #define WEIGHT_CB_EN3_SHIFT 18 9467ccd5a2cSjsg #define CG_CAC_REGION_2_WEIGHT_1 0x86 9477ccd5a2cSjsg #define WEIGHT_DB_SIG0(x) ((x) << 0) 9487ccd5a2cSjsg #define WEIGHT_DB_SIG0_MASK (0x3f << 0) 9497ccd5a2cSjsg #define WEIGHT_DB_SIG0_SHIFT 0 9507ccd5a2cSjsg #define WEIGHT_DB_SIG1(x) ((x) << 6) 9517ccd5a2cSjsg #define WEIGHT_DB_SIG1_MASK (0x3f << 6) 9527ccd5a2cSjsg #define WEIGHT_DB_SIG1_SHIFT 6 9537ccd5a2cSjsg #define WEIGHT_DB_SIG2(x) ((x) << 12) 9547ccd5a2cSjsg #define WEIGHT_DB_SIG2_MASK (0x3f << 12) 9557ccd5a2cSjsg #define WEIGHT_DB_SIG2_SHIFT 12 9567ccd5a2cSjsg #define WEIGHT_DB_SIG3(x) ((x) << 18) 9577ccd5a2cSjsg #define WEIGHT_DB_SIG3_MASK (0x3f << 18) 9587ccd5a2cSjsg #define WEIGHT_DB_SIG3_SHIFT 18 9597ccd5a2cSjsg #define CG_CAC_REGION_2_WEIGHT_2 0x87 9607ccd5a2cSjsg #define WEIGHT_SXM_SIG0(x) ((x) << 0) 9617ccd5a2cSjsg #define WEIGHT_SXM_SIG0_MASK (0x3f << 0) 9627ccd5a2cSjsg #define WEIGHT_SXM_SIG0_SHIFT 0 9637ccd5a2cSjsg #define WEIGHT_SXM_SIG1(x) ((x) << 6) 9647ccd5a2cSjsg #define WEIGHT_SXM_SIG1_MASK (0x3f << 6) 9657ccd5a2cSjsg #define WEIGHT_SXM_SIG1_SHIFT 6 9667ccd5a2cSjsg #define WEIGHT_SXM_SIG2(x) ((x) << 12) 9677ccd5a2cSjsg #define WEIGHT_SXM_SIG2_MASK (0x3f << 12) 9687ccd5a2cSjsg #define WEIGHT_SXM_SIG2_SHIFT 12 9697ccd5a2cSjsg #define WEIGHT_SXS_SIG0(x) ((x) << 18) 9707ccd5a2cSjsg #define WEIGHT_SXS_SIG0_MASK (0x3f << 18) 9717ccd5a2cSjsg #define WEIGHT_SXS_SIG0_SHIFT 18 9727ccd5a2cSjsg #define WEIGHT_SXS_SIG1(x) ((x) << 24) 9737ccd5a2cSjsg #define WEIGHT_SXS_SIG1_MASK (0x3f << 24) 9747ccd5a2cSjsg #define WEIGHT_SXS_SIG1_SHIFT 24 9757ccd5a2cSjsg #define CG_CAC_REGION_3_WEIGHT_0 0x88 9767ccd5a2cSjsg #define WEIGHT_XBR_0(x) ((x) << 0) 9777ccd5a2cSjsg #define WEIGHT_XBR_0_MASK (0x3f << 0) 9787ccd5a2cSjsg #define WEIGHT_XBR_0_SHIFT 0 9797ccd5a2cSjsg #define WEIGHT_XBR_1(x) ((x) << 6) 9807ccd5a2cSjsg #define WEIGHT_XBR_1_MASK (0x3f << 6) 9817ccd5a2cSjsg #define WEIGHT_XBR_1_SHIFT 6 9827ccd5a2cSjsg #define WEIGHT_XBR_2(x) ((x) << 12) 9837ccd5a2cSjsg #define WEIGHT_XBR_2_MASK (0x3f << 12) 9847ccd5a2cSjsg #define WEIGHT_XBR_2_SHIFT 12 9857ccd5a2cSjsg #define WEIGHT_SPI_SIG0(x) ((x) << 18) 9867ccd5a2cSjsg #define WEIGHT_SPI_SIG0_MASK (0x3f << 18) 9877ccd5a2cSjsg #define WEIGHT_SPI_SIG0_SHIFT 18 9887ccd5a2cSjsg #define CG_CAC_REGION_3_WEIGHT_1 0x89 9897ccd5a2cSjsg #define WEIGHT_SPI_SIG1(x) ((x) << 0) 9907ccd5a2cSjsg #define WEIGHT_SPI_SIG1_MASK (0x3f << 0) 9917ccd5a2cSjsg #define WEIGHT_SPI_SIG1_SHIFT 0 9927ccd5a2cSjsg #define WEIGHT_SPI_SIG2(x) ((x) << 6) 9937ccd5a2cSjsg #define WEIGHT_SPI_SIG2_MASK (0x3f << 6) 9947ccd5a2cSjsg #define WEIGHT_SPI_SIG2_SHIFT 6 9957ccd5a2cSjsg #define WEIGHT_SPI_SIG3(x) ((x) << 12) 9967ccd5a2cSjsg #define WEIGHT_SPI_SIG3_MASK (0x3f << 12) 9977ccd5a2cSjsg #define WEIGHT_SPI_SIG3_SHIFT 12 9987ccd5a2cSjsg #define WEIGHT_SPI_SIG4(x) ((x) << 18) 9997ccd5a2cSjsg #define WEIGHT_SPI_SIG4_MASK (0x3f << 18) 10007ccd5a2cSjsg #define WEIGHT_SPI_SIG4_SHIFT 18 10017ccd5a2cSjsg #define WEIGHT_SPI_SIG5(x) ((x) << 24) 10027ccd5a2cSjsg #define WEIGHT_SPI_SIG5_MASK (0x3f << 24) 10037ccd5a2cSjsg #define WEIGHT_SPI_SIG5_SHIFT 24 10047ccd5a2cSjsg #define CG_CAC_REGION_4_WEIGHT_0 0x8a 10057ccd5a2cSjsg #define WEIGHT_LDS_SIG0(x) ((x) << 0) 10067ccd5a2cSjsg #define WEIGHT_LDS_SIG0_MASK (0x3f << 0) 10077ccd5a2cSjsg #define WEIGHT_LDS_SIG0_SHIFT 0 10087ccd5a2cSjsg #define WEIGHT_LDS_SIG1(x) ((x) << 6) 10097ccd5a2cSjsg #define WEIGHT_LDS_SIG1_MASK (0x3f << 6) 10107ccd5a2cSjsg #define WEIGHT_LDS_SIG1_SHIFT 6 10117ccd5a2cSjsg #define WEIGHT_SC(x) ((x) << 24) 10127ccd5a2cSjsg #define WEIGHT_SC_MASK (0x3f << 24) 10137ccd5a2cSjsg #define WEIGHT_SC_SHIFT 24 10147ccd5a2cSjsg #define CG_CAC_REGION_4_WEIGHT_1 0x8b 10157ccd5a2cSjsg #define WEIGHT_BIF(x) ((x) << 0) 10167ccd5a2cSjsg #define WEIGHT_BIF_MASK (0x3f << 0) 10177ccd5a2cSjsg #define WEIGHT_BIF_SHIFT 0 10187ccd5a2cSjsg #define WEIGHT_CP(x) ((x) << 6) 10197ccd5a2cSjsg #define WEIGHT_CP_MASK (0x3f << 6) 10207ccd5a2cSjsg #define WEIGHT_CP_SHIFT 6 10217ccd5a2cSjsg #define WEIGHT_PA_SIG0(x) ((x) << 12) 10227ccd5a2cSjsg #define WEIGHT_PA_SIG0_MASK (0x3f << 12) 10237ccd5a2cSjsg #define WEIGHT_PA_SIG0_SHIFT 12 10247ccd5a2cSjsg #define WEIGHT_PA_SIG1(x) ((x) << 18) 10257ccd5a2cSjsg #define WEIGHT_PA_SIG1_MASK (0x3f << 18) 10267ccd5a2cSjsg #define WEIGHT_PA_SIG1_SHIFT 18 10277ccd5a2cSjsg #define WEIGHT_VGT_SIG0(x) ((x) << 24) 10287ccd5a2cSjsg #define WEIGHT_VGT_SIG0_MASK (0x3f << 24) 10297ccd5a2cSjsg #define WEIGHT_VGT_SIG0_SHIFT 24 10307ccd5a2cSjsg #define CG_CAC_REGION_4_WEIGHT_2 0x8c 10317ccd5a2cSjsg #define WEIGHT_VGT_SIG1(x) ((x) << 0) 10327ccd5a2cSjsg #define WEIGHT_VGT_SIG1_MASK (0x3f << 0) 10337ccd5a2cSjsg #define WEIGHT_VGT_SIG1_SHIFT 0 10347ccd5a2cSjsg #define WEIGHT_VGT_SIG2(x) ((x) << 6) 10357ccd5a2cSjsg #define WEIGHT_VGT_SIG2_MASK (0x3f << 6) 10367ccd5a2cSjsg #define WEIGHT_VGT_SIG2_SHIFT 6 10377ccd5a2cSjsg #define WEIGHT_DC_SIG0(x) ((x) << 12) 10387ccd5a2cSjsg #define WEIGHT_DC_SIG0_MASK (0x3f << 12) 10397ccd5a2cSjsg #define WEIGHT_DC_SIG0_SHIFT 12 10407ccd5a2cSjsg #define WEIGHT_DC_SIG1(x) ((x) << 18) 10417ccd5a2cSjsg #define WEIGHT_DC_SIG1_MASK (0x3f << 18) 10427ccd5a2cSjsg #define WEIGHT_DC_SIG1_SHIFT 18 10437ccd5a2cSjsg #define WEIGHT_DC_SIG2(x) ((x) << 24) 10447ccd5a2cSjsg #define WEIGHT_DC_SIG2_MASK (0x3f << 24) 10457ccd5a2cSjsg #define WEIGHT_DC_SIG2_SHIFT 24 10467ccd5a2cSjsg #define CG_CAC_REGION_4_WEIGHT_3 0x8d 10477ccd5a2cSjsg #define WEIGHT_DC_SIG3(x) ((x) << 0) 10487ccd5a2cSjsg #define WEIGHT_DC_SIG3_MASK (0x3f << 0) 10497ccd5a2cSjsg #define WEIGHT_DC_SIG3_SHIFT 0 10507ccd5a2cSjsg #define WEIGHT_UVD_SIG0(x) ((x) << 6) 10517ccd5a2cSjsg #define WEIGHT_UVD_SIG0_MASK (0x3f << 6) 10527ccd5a2cSjsg #define WEIGHT_UVD_SIG0_SHIFT 6 10537ccd5a2cSjsg #define WEIGHT_UVD_SIG1(x) ((x) << 12) 10547ccd5a2cSjsg #define WEIGHT_UVD_SIG1_MASK (0x3f << 12) 10557ccd5a2cSjsg #define WEIGHT_UVD_SIG1_SHIFT 12 10567ccd5a2cSjsg #define WEIGHT_SPARE0(x) ((x) << 18) 10577ccd5a2cSjsg #define WEIGHT_SPARE0_MASK (0x3f << 18) 10587ccd5a2cSjsg #define WEIGHT_SPARE0_SHIFT 18 10597ccd5a2cSjsg #define WEIGHT_SPARE1(x) ((x) << 24) 10607ccd5a2cSjsg #define WEIGHT_SPARE1_MASK (0x3f << 24) 10617ccd5a2cSjsg #define WEIGHT_SPARE1_SHIFT 24 10627ccd5a2cSjsg #define CG_CAC_REGION_5_WEIGHT_0 0x8e 10637ccd5a2cSjsg #define WEIGHT_SQ_VSP(x) ((x) << 0) 10647ccd5a2cSjsg #define WEIGHT_SQ_VSP_MASK (0x3fff << 0) 10657ccd5a2cSjsg #define WEIGHT_SQ_VSP_SHIFT 0 10667ccd5a2cSjsg #define WEIGHT_SQ_VSP0(x) ((x) << 14) 10677ccd5a2cSjsg #define WEIGHT_SQ_VSP0_MASK (0x3fff << 14) 10687ccd5a2cSjsg #define WEIGHT_SQ_VSP0_SHIFT 14 10697ccd5a2cSjsg #define CG_CAC_REGION_4_OVERRIDE_4 0xab 10707ccd5a2cSjsg #define OVR_MODE_SPARE_0(x) ((x) << 16) 10717ccd5a2cSjsg #define OVR_MODE_SPARE_0_MASK (0x1 << 16) 10727ccd5a2cSjsg #define OVR_MODE_SPARE_0_SHIFT 16 10737ccd5a2cSjsg #define OVR_VAL_SPARE_0(x) ((x) << 17) 10747ccd5a2cSjsg #define OVR_VAL_SPARE_0_MASK (0x1 << 17) 10757ccd5a2cSjsg #define OVR_VAL_SPARE_0_SHIFT 17 10767ccd5a2cSjsg #define OVR_MODE_SPARE_1(x) ((x) << 18) 10777ccd5a2cSjsg #define OVR_MODE_SPARE_1_MASK (0x3f << 18) 10787ccd5a2cSjsg #define OVR_MODE_SPARE_1_SHIFT 18 10797ccd5a2cSjsg #define OVR_VAL_SPARE_1(x) ((x) << 19) 10807ccd5a2cSjsg #define OVR_VAL_SPARE_1_MASK (0x3f << 19) 10817ccd5a2cSjsg #define OVR_VAL_SPARE_1_SHIFT 19 10827ccd5a2cSjsg #define CG_CAC_REGION_5_WEIGHT_1 0xb7 10837ccd5a2cSjsg #define WEIGHT_SQ_GPR(x) ((x) << 0) 10847ccd5a2cSjsg #define WEIGHT_SQ_GPR_MASK (0x3fff << 0) 10857ccd5a2cSjsg #define WEIGHT_SQ_GPR_SHIFT 0 10867ccd5a2cSjsg #define WEIGHT_SQ_LDS(x) ((x) << 14) 10877ccd5a2cSjsg #define WEIGHT_SQ_LDS_MASK (0x3fff << 14) 10887ccd5a2cSjsg #define WEIGHT_SQ_LDS_SHIFT 14 10897ccd5a2cSjsg 10907ccd5a2cSjsg /* PCIE link stuff */ 10917ccd5a2cSjsg #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 10927ccd5a2cSjsg #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 10937ccd5a2cSjsg # define LC_LINK_WIDTH_SHIFT 0 10947ccd5a2cSjsg # define LC_LINK_WIDTH_MASK 0x7 10957ccd5a2cSjsg # define LC_LINK_WIDTH_X0 0 10967ccd5a2cSjsg # define LC_LINK_WIDTH_X1 1 10977ccd5a2cSjsg # define LC_LINK_WIDTH_X2 2 10987ccd5a2cSjsg # define LC_LINK_WIDTH_X4 3 10997ccd5a2cSjsg # define LC_LINK_WIDTH_X8 4 11007ccd5a2cSjsg # define LC_LINK_WIDTH_X16 6 11017ccd5a2cSjsg # define LC_LINK_WIDTH_RD_SHIFT 4 11027ccd5a2cSjsg # define LC_LINK_WIDTH_RD_MASK 0x70 11037ccd5a2cSjsg # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 11047ccd5a2cSjsg # define LC_RECONFIG_NOW (1 << 8) 11057ccd5a2cSjsg # define LC_RENEGOTIATION_SUPPORT (1 << 9) 11067ccd5a2cSjsg # define LC_RENEGOTIATE_EN (1 << 10) 11077ccd5a2cSjsg # define LC_SHORT_RECONFIG_EN (1 << 11) 11087ccd5a2cSjsg # define LC_UPCONFIGURE_SUPPORT (1 << 12) 11097ccd5a2cSjsg # define LC_UPCONFIGURE_DIS (1 << 13) 11107ccd5a2cSjsg #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 11117ccd5a2cSjsg # define LC_GEN2_EN_STRAP (1 << 0) 11127ccd5a2cSjsg # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 11137ccd5a2cSjsg # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 11147ccd5a2cSjsg # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 11157ccd5a2cSjsg # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 11167ccd5a2cSjsg # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 11177ccd5a2cSjsg # define LC_CURRENT_DATA_RATE (1 << 11) 11187ccd5a2cSjsg # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 11197ccd5a2cSjsg # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 11207ccd5a2cSjsg # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 11217ccd5a2cSjsg # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 11227ccd5a2cSjsg # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 11237ccd5a2cSjsg # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 11247ccd5a2cSjsg # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 11257ccd5a2cSjsg #define MM_CFGREGS_CNTL 0x544c 11267ccd5a2cSjsg # define MM_WR_TO_CFG_EN (1 << 3) 11277ccd5a2cSjsg #define LINK_CNTL2 0x88 /* F0 */ 11287ccd5a2cSjsg # define TARGET_LINK_SPEED_MASK (0xf << 0) 11297ccd5a2cSjsg # define SELECTABLE_DEEMPHASIS (1 << 6) 11307ccd5a2cSjsg 11317ccd5a2cSjsg /* 11327ccd5a2cSjsg * UVD 11337ccd5a2cSjsg */ 11347ccd5a2cSjsg #define UVD_SEMA_ADDR_LOW 0xEF00 11357ccd5a2cSjsg #define UVD_SEMA_ADDR_HIGH 0xEF04 11367ccd5a2cSjsg #define UVD_SEMA_CMD 0xEF08 11377ccd5a2cSjsg #define UVD_UDEC_ADDR_CONFIG 0xEF4C 11387ccd5a2cSjsg #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50 11397ccd5a2cSjsg #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54 1140*7f4dd379Sjsg #define UVD_NO_OP 0xEFFC 11417ccd5a2cSjsg #define UVD_RBC_RB_RPTR 0xF690 11427ccd5a2cSjsg #define UVD_RBC_RB_WPTR 0xF694 11437ccd5a2cSjsg #define UVD_STATUS 0xf6bc 11447ccd5a2cSjsg 11451099013bSjsg /* 11461099013bSjsg * PM4 11471099013bSjsg */ 11487ccd5a2cSjsg #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 11491099013bSjsg (((reg) >> 2) & 0xFFFF) | \ 11501099013bSjsg ((n) & 0x3FFF) << 16) 11511099013bSjsg #define CP_PACKET2 0x80000000 11521099013bSjsg #define PACKET2_PAD_SHIFT 0 11531099013bSjsg #define PACKET2_PAD_MASK (0x3fffffff << 0) 11541099013bSjsg 11551099013bSjsg #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 11561099013bSjsg 11577ccd5a2cSjsg #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 11581099013bSjsg (((op) & 0xFF) << 8) | \ 11591099013bSjsg ((n) & 0x3FFF) << 16) 11601099013bSjsg 11611099013bSjsg /* Packet 3 types */ 11621099013bSjsg #define PACKET3_NOP 0x10 11631099013bSjsg #define PACKET3_SET_BASE 0x11 11641099013bSjsg #define PACKET3_CLEAR_STATE 0x12 11651099013bSjsg #define PACKET3_INDEX_BUFFER_SIZE 0x13 11661099013bSjsg #define PACKET3_DEALLOC_STATE 0x14 11671099013bSjsg #define PACKET3_DISPATCH_DIRECT 0x15 11681099013bSjsg #define PACKET3_DISPATCH_INDIRECT 0x16 11691099013bSjsg #define PACKET3_INDIRECT_BUFFER_END 0x17 11701099013bSjsg #define PACKET3_MODE_CONTROL 0x18 11711099013bSjsg #define PACKET3_SET_PREDICATION 0x20 11721099013bSjsg #define PACKET3_REG_RMW 0x21 11731099013bSjsg #define PACKET3_COND_EXEC 0x22 11741099013bSjsg #define PACKET3_PRED_EXEC 0x23 11751099013bSjsg #define PACKET3_DRAW_INDIRECT 0x24 11761099013bSjsg #define PACKET3_DRAW_INDEX_INDIRECT 0x25 11771099013bSjsg #define PACKET3_INDEX_BASE 0x26 11781099013bSjsg #define PACKET3_DRAW_INDEX_2 0x27 11791099013bSjsg #define PACKET3_CONTEXT_CONTROL 0x28 11801099013bSjsg #define PACKET3_DRAW_INDEX_OFFSET 0x29 11811099013bSjsg #define PACKET3_INDEX_TYPE 0x2A 11821099013bSjsg #define PACKET3_DRAW_INDEX 0x2B 11831099013bSjsg #define PACKET3_DRAW_INDEX_AUTO 0x2D 11841099013bSjsg #define PACKET3_DRAW_INDEX_IMMD 0x2E 11851099013bSjsg #define PACKET3_NUM_INSTANCES 0x2F 11861099013bSjsg #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 11871099013bSjsg #define PACKET3_INDIRECT_BUFFER 0x32 11881099013bSjsg #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 11891099013bSjsg #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 11901099013bSjsg #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 11911099013bSjsg #define PACKET3_WRITE_DATA 0x37 11921099013bSjsg #define PACKET3_MEM_SEMAPHORE 0x39 11931099013bSjsg #define PACKET3_MPEG_INDEX 0x3A 11941099013bSjsg #define PACKET3_WAIT_REG_MEM 0x3C 11957ccd5a2cSjsg #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 11967ccd5a2cSjsg /* 0 - always 11977ccd5a2cSjsg * 1 - < 11987ccd5a2cSjsg * 2 - <= 11997ccd5a2cSjsg * 3 - == 12007ccd5a2cSjsg * 4 - != 12017ccd5a2cSjsg * 5 - >= 12027ccd5a2cSjsg * 6 - > 12037ccd5a2cSjsg */ 12047ccd5a2cSjsg #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 12057ccd5a2cSjsg /* 0 - reg 12067ccd5a2cSjsg * 1 - mem 12077ccd5a2cSjsg */ 12087ccd5a2cSjsg #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 12097ccd5a2cSjsg /* 0 - me 12107ccd5a2cSjsg * 1 - pfp 12117ccd5a2cSjsg */ 12121099013bSjsg #define PACKET3_MEM_WRITE 0x3D 12131099013bSjsg #define PACKET3_PFP_SYNC_ME 0x42 12141099013bSjsg #define PACKET3_SURFACE_SYNC 0x43 12151099013bSjsg # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 12161099013bSjsg # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 12171099013bSjsg # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 12181099013bSjsg # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 12191099013bSjsg # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 12201099013bSjsg # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 12211099013bSjsg # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 12221099013bSjsg # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 12231099013bSjsg # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 12241099013bSjsg # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 12251099013bSjsg # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 12261099013bSjsg # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 12271099013bSjsg # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 12281099013bSjsg # define PACKET3_FULL_CACHE_ENA (1 << 20) 12291099013bSjsg # define PACKET3_TC_ACTION_ENA (1 << 23) 12301099013bSjsg # define PACKET3_CB_ACTION_ENA (1 << 25) 12311099013bSjsg # define PACKET3_DB_ACTION_ENA (1 << 26) 12321099013bSjsg # define PACKET3_SH_ACTION_ENA (1 << 27) 12331099013bSjsg # define PACKET3_SX_ACTION_ENA (1 << 28) 1234bc26ceb1Sjsg # define PACKET3_ENGINE_ME (1 << 31) 12351099013bSjsg #define PACKET3_ME_INITIALIZE 0x44 12361099013bSjsg #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 12371099013bSjsg #define PACKET3_COND_WRITE 0x45 12381099013bSjsg #define PACKET3_EVENT_WRITE 0x46 12391099013bSjsg #define EVENT_TYPE(x) ((x) << 0) 12401099013bSjsg #define EVENT_INDEX(x) ((x) << 8) 12411099013bSjsg /* 0 - any non-TS event 12421099013bSjsg * 1 - ZPASS_DONE 12431099013bSjsg * 2 - SAMPLE_PIPELINESTAT 12441099013bSjsg * 3 - SAMPLE_STREAMOUTSTAT* 12451099013bSjsg * 4 - *S_PARTIAL_FLUSH 12461099013bSjsg * 5 - TS events 12471099013bSjsg */ 12481099013bSjsg #define PACKET3_EVENT_WRITE_EOP 0x47 12491099013bSjsg #define DATA_SEL(x) ((x) << 29) 12501099013bSjsg /* 0 - discard 12511099013bSjsg * 1 - send low 32bit data 12521099013bSjsg * 2 - send 64bit data 12531099013bSjsg * 3 - send 64bit counter value 12541099013bSjsg */ 12551099013bSjsg #define INT_SEL(x) ((x) << 24) 12561099013bSjsg /* 0 - none 12571099013bSjsg * 1 - interrupt only (DATA_SEL = 0) 12581099013bSjsg * 2 - interrupt when data write is confirmed 12591099013bSjsg */ 12601099013bSjsg #define PACKET3_EVENT_WRITE_EOS 0x48 12611099013bSjsg #define PACKET3_PREAMBLE_CNTL 0x4A 12621099013bSjsg # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 12631099013bSjsg # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 12641099013bSjsg #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 12651099013bSjsg #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 12661099013bSjsg #define PACKET3_ALU_PS_CONST_UPDATE 0x4E 12671099013bSjsg #define PACKET3_ALU_VS_CONST_UPDATE 0x4F 12681099013bSjsg #define PACKET3_ONE_REG_WRITE 0x57 12691099013bSjsg #define PACKET3_SET_CONFIG_REG 0x68 12701099013bSjsg #define PACKET3_SET_CONFIG_REG_START 0x00008000 12711099013bSjsg #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 12721099013bSjsg #define PACKET3_SET_CONTEXT_REG 0x69 12731099013bSjsg #define PACKET3_SET_CONTEXT_REG_START 0x00028000 12741099013bSjsg #define PACKET3_SET_CONTEXT_REG_END 0x00029000 12751099013bSjsg #define PACKET3_SET_ALU_CONST 0x6A 12761099013bSjsg /* alu const buffers only; no reg file */ 12771099013bSjsg #define PACKET3_SET_BOOL_CONST 0x6B 12781099013bSjsg #define PACKET3_SET_BOOL_CONST_START 0x0003a500 12791099013bSjsg #define PACKET3_SET_BOOL_CONST_END 0x0003a518 12801099013bSjsg #define PACKET3_SET_LOOP_CONST 0x6C 12811099013bSjsg #define PACKET3_SET_LOOP_CONST_START 0x0003a200 12821099013bSjsg #define PACKET3_SET_LOOP_CONST_END 0x0003a500 12831099013bSjsg #define PACKET3_SET_RESOURCE 0x6D 12841099013bSjsg #define PACKET3_SET_RESOURCE_START 0x00030000 12851099013bSjsg #define PACKET3_SET_RESOURCE_END 0x00038000 12861099013bSjsg #define PACKET3_SET_SAMPLER 0x6E 12871099013bSjsg #define PACKET3_SET_SAMPLER_START 0x0003c000 12881099013bSjsg #define PACKET3_SET_SAMPLER_END 0x0003c600 12891099013bSjsg #define PACKET3_SET_CTL_CONST 0x6F 12901099013bSjsg #define PACKET3_SET_CTL_CONST_START 0x0003cff0 12911099013bSjsg #define PACKET3_SET_CTL_CONST_END 0x0003ff0c 12921099013bSjsg #define PACKET3_SET_RESOURCE_OFFSET 0x70 12931099013bSjsg #define PACKET3_SET_ALU_CONST_VS 0x71 12941099013bSjsg #define PACKET3_SET_ALU_CONST_DI 0x72 12951099013bSjsg #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 12961099013bSjsg #define PACKET3_SET_RESOURCE_INDIRECT 0x74 12971099013bSjsg #define PACKET3_SET_APPEND_CNT 0x75 12981099013bSjsg #define PACKET3_ME_WRITE 0x7A 12991099013bSjsg 13001099013bSjsg /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 13011099013bSjsg #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 13021099013bSjsg #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 13031099013bSjsg 13041099013bSjsg #define DMA_RB_CNTL 0xd000 13051099013bSjsg # define DMA_RB_ENABLE (1 << 0) 13061099013bSjsg # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 13071099013bSjsg # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 13081099013bSjsg # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 13091099013bSjsg # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 13101099013bSjsg # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 13111099013bSjsg #define DMA_RB_BASE 0xd004 13121099013bSjsg #define DMA_RB_RPTR 0xd008 13131099013bSjsg #define DMA_RB_WPTR 0xd00c 13141099013bSjsg 13151099013bSjsg #define DMA_RB_RPTR_ADDR_HI 0xd01c 13161099013bSjsg #define DMA_RB_RPTR_ADDR_LO 0xd020 13171099013bSjsg 13181099013bSjsg #define DMA_IB_CNTL 0xd024 13191099013bSjsg # define DMA_IB_ENABLE (1 << 0) 13201099013bSjsg # define DMA_IB_SWAP_ENABLE (1 << 4) 13211099013bSjsg # define CMD_VMID_FORCE (1 << 31) 13221099013bSjsg #define DMA_IB_RPTR 0xd028 13231099013bSjsg #define DMA_CNTL 0xd02c 13241099013bSjsg # define TRAP_ENABLE (1 << 0) 13251099013bSjsg # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 13261099013bSjsg # define SEM_WAIT_INT_ENABLE (1 << 2) 13271099013bSjsg # define DATA_SWAP_ENABLE (1 << 3) 13281099013bSjsg # define FENCE_SWAP_ENABLE (1 << 4) 13291099013bSjsg # define CTXEMPTY_INT_ENABLE (1 << 28) 13301099013bSjsg #define DMA_STATUS_REG 0xd034 13311099013bSjsg # define DMA_IDLE (1 << 0) 13321099013bSjsg #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 13331099013bSjsg #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 13341099013bSjsg #define DMA_TILING_CONFIG 0xd0b8 13351099013bSjsg #define DMA_MODE 0xd0bc 13361099013bSjsg 13371099013bSjsg #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 13381099013bSjsg (((t) & 0x1) << 23) | \ 13391099013bSjsg (((s) & 0x1) << 22) | \ 13401099013bSjsg (((n) & 0xFFFFF) << 0)) 13411099013bSjsg 13421099013bSjsg #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 13431099013bSjsg (((vmid) & 0xF) << 20) | \ 13441099013bSjsg (((n) & 0xFFFFF) << 0)) 13451099013bSjsg 13467ccd5a2cSjsg #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 13477ccd5a2cSjsg (1 << 26) | \ 13487ccd5a2cSjsg (1 << 21) | \ 13497ccd5a2cSjsg (((n) & 0xFFFFF) << 0)) 13507ccd5a2cSjsg 13517ccd5a2cSjsg #define DMA_SRBM_POLL_PACKET ((9 << 28) | \ 13527ccd5a2cSjsg (1 << 27) | \ 13537ccd5a2cSjsg (1 << 26)) 13547ccd5a2cSjsg 13557ccd5a2cSjsg #define DMA_SRBM_READ_PACKET ((9 << 28) | \ 13567ccd5a2cSjsg (1 << 27)) 13577ccd5a2cSjsg 13581099013bSjsg /* async DMA Packet types */ 13591099013bSjsg #define DMA_PACKET_WRITE 0x2 13601099013bSjsg #define DMA_PACKET_COPY 0x3 13611099013bSjsg #define DMA_PACKET_INDIRECT_BUFFER 0x4 13621099013bSjsg #define DMA_PACKET_SEMAPHORE 0x5 13631099013bSjsg #define DMA_PACKET_FENCE 0x6 13641099013bSjsg #define DMA_PACKET_TRAP 0x7 13651099013bSjsg #define DMA_PACKET_SRBM_WRITE 0x9 13661099013bSjsg #define DMA_PACKET_CONSTANT_FILL 0xd 13671099013bSjsg #define DMA_PACKET_NOP 0xf 13681099013bSjsg 13691099013bSjsg #endif 1370