1*1099013bSjsg /* 2*1099013bSjsg * Copyright 2008 Advanced Micro Devices, Inc. 3*1099013bSjsg * Copyright 2008 Red Hat Inc. 4*1099013bSjsg * Copyright 2009 Jerome Glisse. 5*1099013bSjsg * 6*1099013bSjsg * Permission is hereby granted, free of charge, to any person obtaining a 7*1099013bSjsg * copy of this software and associated documentation files (the "Software"), 8*1099013bSjsg * to deal in the Software without restriction, including without limitation 9*1099013bSjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10*1099013bSjsg * and/or sell copies of the Software, and to permit persons to whom the 11*1099013bSjsg * Software is furnished to do so, subject to the following conditions: 12*1099013bSjsg * 13*1099013bSjsg * The above copyright notice and this permission notice shall be included in 14*1099013bSjsg * all copies or substantial portions of the Software. 15*1099013bSjsg * 16*1099013bSjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17*1099013bSjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18*1099013bSjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19*1099013bSjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20*1099013bSjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21*1099013bSjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22*1099013bSjsg * OTHER DEALINGS IN THE SOFTWARE. 23*1099013bSjsg * 24*1099013bSjsg * Authors: Dave Airlie 25*1099013bSjsg * Alex Deucher 26*1099013bSjsg * Jerome Glisse 27*1099013bSjsg */ 28*1099013bSjsg #ifndef __R100D_H__ 29*1099013bSjsg #define __R100D_H__ 30*1099013bSjsg 31*1099013bSjsg #define CP_PACKET0 0x00000000 32*1099013bSjsg #define PACKET0_BASE_INDEX_SHIFT 0 33*1099013bSjsg #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) 34*1099013bSjsg #define PACKET0_COUNT_SHIFT 16 35*1099013bSjsg #define PACKET0_COUNT_MASK (0x3fff << 16) 36*1099013bSjsg #define CP_PACKET1 0x40000000 37*1099013bSjsg #define CP_PACKET2 0x80000000 38*1099013bSjsg #define PACKET2_PAD_SHIFT 0 39*1099013bSjsg #define PACKET2_PAD_MASK (0x3fffffff << 0) 40*1099013bSjsg #define CP_PACKET3 0xC0000000 41*1099013bSjsg #define PACKET3_IT_OPCODE_SHIFT 8 42*1099013bSjsg #define PACKET3_IT_OPCODE_MASK (0xff << 8) 43*1099013bSjsg #define PACKET3_COUNT_SHIFT 16 44*1099013bSjsg #define PACKET3_COUNT_MASK (0x3fff << 16) 45*1099013bSjsg /* PACKET3 op code */ 46*1099013bSjsg #define PACKET3_NOP 0x10 47*1099013bSjsg #define PACKET3_3D_DRAW_VBUF 0x28 48*1099013bSjsg #define PACKET3_3D_DRAW_IMMD 0x29 49*1099013bSjsg #define PACKET3_3D_DRAW_INDX 0x2A 50*1099013bSjsg #define PACKET3_3D_LOAD_VBPNTR 0x2F 51*1099013bSjsg #define PACKET3_3D_CLEAR_ZMASK 0x32 52*1099013bSjsg #define PACKET3_INDX_BUFFER 0x33 53*1099013bSjsg #define PACKET3_3D_DRAW_VBUF_2 0x34 54*1099013bSjsg #define PACKET3_3D_DRAW_IMMD_2 0x35 55*1099013bSjsg #define PACKET3_3D_DRAW_INDX_2 0x36 56*1099013bSjsg #define PACKET3_3D_CLEAR_HIZ 0x37 57*1099013bSjsg #define PACKET3_BITBLT_MULTI 0x9B 58*1099013bSjsg 59*1099013bSjsg #define PACKET0(reg, n) (CP_PACKET0 | \ 60*1099013bSjsg REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ 61*1099013bSjsg REG_SET(PACKET0_COUNT, (n))) 62*1099013bSjsg #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 63*1099013bSjsg #define PACKET3(op, n) (CP_PACKET3 | \ 64*1099013bSjsg REG_SET(PACKET3_IT_OPCODE, (op)) | \ 65*1099013bSjsg REG_SET(PACKET3_COUNT, (n))) 66*1099013bSjsg 67*1099013bSjsg /* Registers */ 68*1099013bSjsg #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 69*1099013bSjsg #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 70*1099013bSjsg #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 71*1099013bSjsg #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE 72*1099013bSjsg #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 73*1099013bSjsg #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 74*1099013bSjsg #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD 75*1099013bSjsg #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) 76*1099013bSjsg #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) 77*1099013bSjsg #define C_0000F0_SOFT_RESET_SE 0xFFFFFFFB 78*1099013bSjsg #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 79*1099013bSjsg #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 80*1099013bSjsg #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 81*1099013bSjsg #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 82*1099013bSjsg #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) 83*1099013bSjsg #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF 84*1099013bSjsg #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) 85*1099013bSjsg #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) 86*1099013bSjsg #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF 87*1099013bSjsg #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) 88*1099013bSjsg #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) 89*1099013bSjsg #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF 90*1099013bSjsg #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) 91*1099013bSjsg #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) 92*1099013bSjsg #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F 93*1099013bSjsg #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) 94*1099013bSjsg #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) 95*1099013bSjsg #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF 96*1099013bSjsg #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) 97*1099013bSjsg #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) 98*1099013bSjsg #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF 99*1099013bSjsg #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) 100*1099013bSjsg #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) 101*1099013bSjsg #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF 102*1099013bSjsg #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) 103*1099013bSjsg #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) 104*1099013bSjsg #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF 105*1099013bSjsg #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) 106*1099013bSjsg #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) 107*1099013bSjsg #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF 108*1099013bSjsg #define R_000030_BUS_CNTL 0x000030 109*1099013bSjsg #define S_000030_BUS_DBL_RESYNC(x) (((x) & 0x1) << 0) 110*1099013bSjsg #define G_000030_BUS_DBL_RESYNC(x) (((x) >> 0) & 0x1) 111*1099013bSjsg #define C_000030_BUS_DBL_RESYNC 0xFFFFFFFE 112*1099013bSjsg #define S_000030_BUS_MSTR_RESET(x) (((x) & 0x1) << 1) 113*1099013bSjsg #define G_000030_BUS_MSTR_RESET(x) (((x) >> 1) & 0x1) 114*1099013bSjsg #define C_000030_BUS_MSTR_RESET 0xFFFFFFFD 115*1099013bSjsg #define S_000030_BUS_FLUSH_BUF(x) (((x) & 0x1) << 2) 116*1099013bSjsg #define G_000030_BUS_FLUSH_BUF(x) (((x) >> 2) & 0x1) 117*1099013bSjsg #define C_000030_BUS_FLUSH_BUF 0xFFFFFFFB 118*1099013bSjsg #define S_000030_BUS_STOP_REQ_DIS(x) (((x) & 0x1) << 3) 119*1099013bSjsg #define G_000030_BUS_STOP_REQ_DIS(x) (((x) >> 3) & 0x1) 120*1099013bSjsg #define C_000030_BUS_STOP_REQ_DIS 0xFFFFFFF7 121*1099013bSjsg #define S_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 4) 122*1099013bSjsg #define G_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) >> 4) & 0x1) 123*1099013bSjsg #define C_000030_BUS_PM4_READ_COMBINE_EN 0xFFFFFFEF 124*1099013bSjsg #define S_000030_BUS_WRT_COMBINE_EN(x) (((x) & 0x1) << 5) 125*1099013bSjsg #define G_000030_BUS_WRT_COMBINE_EN(x) (((x) >> 5) & 0x1) 126*1099013bSjsg #define C_000030_BUS_WRT_COMBINE_EN 0xFFFFFFDF 127*1099013bSjsg #define S_000030_BUS_MASTER_DIS(x) (((x) & 0x1) << 6) 128*1099013bSjsg #define G_000030_BUS_MASTER_DIS(x) (((x) >> 6) & 0x1) 129*1099013bSjsg #define C_000030_BUS_MASTER_DIS 0xFFFFFFBF 130*1099013bSjsg #define S_000030_BIOS_ROM_WRT_EN(x) (((x) & 0x1) << 7) 131*1099013bSjsg #define G_000030_BIOS_ROM_WRT_EN(x) (((x) >> 7) & 0x1) 132*1099013bSjsg #define C_000030_BIOS_ROM_WRT_EN 0xFFFFFF7F 133*1099013bSjsg #define S_000030_BM_DAC_CRIPPLE(x) (((x) & 0x1) << 8) 134*1099013bSjsg #define G_000030_BM_DAC_CRIPPLE(x) (((x) >> 8) & 0x1) 135*1099013bSjsg #define C_000030_BM_DAC_CRIPPLE 0xFFFFFEFF 136*1099013bSjsg #define S_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 9) 137*1099013bSjsg #define G_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) >> 9) & 0x1) 138*1099013bSjsg #define C_000030_BUS_NON_PM4_READ_COMBINE_EN 0xFFFFFDFF 139*1099013bSjsg #define S_000030_BUS_XFERD_DISCARD_EN(x) (((x) & 0x1) << 10) 140*1099013bSjsg #define G_000030_BUS_XFERD_DISCARD_EN(x) (((x) >> 10) & 0x1) 141*1099013bSjsg #define C_000030_BUS_XFERD_DISCARD_EN 0xFFFFFBFF 142*1099013bSjsg #define S_000030_BUS_SGL_READ_DISABLE(x) (((x) & 0x1) << 11) 143*1099013bSjsg #define G_000030_BUS_SGL_READ_DISABLE(x) (((x) >> 11) & 0x1) 144*1099013bSjsg #define C_000030_BUS_SGL_READ_DISABLE 0xFFFFF7FF 145*1099013bSjsg #define S_000030_BIOS_DIS_ROM(x) (((x) & 0x1) << 12) 146*1099013bSjsg #define G_000030_BIOS_DIS_ROM(x) (((x) >> 12) & 0x1) 147*1099013bSjsg #define C_000030_BIOS_DIS_ROM 0xFFFFEFFF 148*1099013bSjsg #define S_000030_BUS_PCI_READ_RETRY_EN(x) (((x) & 0x1) << 13) 149*1099013bSjsg #define G_000030_BUS_PCI_READ_RETRY_EN(x) (((x) >> 13) & 0x1) 150*1099013bSjsg #define C_000030_BUS_PCI_READ_RETRY_EN 0xFFFFDFFF 151*1099013bSjsg #define S_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) & 0x1) << 14) 152*1099013bSjsg #define G_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) >> 14) & 0x1) 153*1099013bSjsg #define C_000030_BUS_AGP_AD_STEPPING_EN 0xFFFFBFFF 154*1099013bSjsg #define S_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) & 0x1) << 15) 155*1099013bSjsg #define G_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) >> 15) & 0x1) 156*1099013bSjsg #define C_000030_BUS_PCI_WRT_RETRY_EN 0xFFFF7FFF 157*1099013bSjsg #define S_000030_BUS_RETRY_WS(x) (((x) & 0xF) << 16) 158*1099013bSjsg #define G_000030_BUS_RETRY_WS(x) (((x) >> 16) & 0xF) 159*1099013bSjsg #define C_000030_BUS_RETRY_WS 0xFFF0FFFF 160*1099013bSjsg #define S_000030_BUS_MSTR_RD_MULT(x) (((x) & 0x1) << 20) 161*1099013bSjsg #define G_000030_BUS_MSTR_RD_MULT(x) (((x) >> 20) & 0x1) 162*1099013bSjsg #define C_000030_BUS_MSTR_RD_MULT 0xFFEFFFFF 163*1099013bSjsg #define S_000030_BUS_MSTR_RD_LINE(x) (((x) & 0x1) << 21) 164*1099013bSjsg #define G_000030_BUS_MSTR_RD_LINE(x) (((x) >> 21) & 0x1) 165*1099013bSjsg #define C_000030_BUS_MSTR_RD_LINE 0xFFDFFFFF 166*1099013bSjsg #define S_000030_BUS_SUSPEND(x) (((x) & 0x1) << 22) 167*1099013bSjsg #define G_000030_BUS_SUSPEND(x) (((x) >> 22) & 0x1) 168*1099013bSjsg #define C_000030_BUS_SUSPEND 0xFFBFFFFF 169*1099013bSjsg #define S_000030_LAT_16X(x) (((x) & 0x1) << 23) 170*1099013bSjsg #define G_000030_LAT_16X(x) (((x) >> 23) & 0x1) 171*1099013bSjsg #define C_000030_LAT_16X 0xFF7FFFFF 172*1099013bSjsg #define S_000030_BUS_RD_DISCARD_EN(x) (((x) & 0x1) << 24) 173*1099013bSjsg #define G_000030_BUS_RD_DISCARD_EN(x) (((x) >> 24) & 0x1) 174*1099013bSjsg #define C_000030_BUS_RD_DISCARD_EN 0xFEFFFFFF 175*1099013bSjsg #define S_000030_ENFRCWRDY(x) (((x) & 0x1) << 25) 176*1099013bSjsg #define G_000030_ENFRCWRDY(x) (((x) >> 25) & 0x1) 177*1099013bSjsg #define C_000030_ENFRCWRDY 0xFDFFFFFF 178*1099013bSjsg #define S_000030_BUS_MSTR_WS(x) (((x) & 0x1) << 26) 179*1099013bSjsg #define G_000030_BUS_MSTR_WS(x) (((x) >> 26) & 0x1) 180*1099013bSjsg #define C_000030_BUS_MSTR_WS 0xFBFFFFFF 181*1099013bSjsg #define S_000030_BUS_PARKING_DIS(x) (((x) & 0x1) << 27) 182*1099013bSjsg #define G_000030_BUS_PARKING_DIS(x) (((x) >> 27) & 0x1) 183*1099013bSjsg #define C_000030_BUS_PARKING_DIS 0xF7FFFFFF 184*1099013bSjsg #define S_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) & 0x1) << 28) 185*1099013bSjsg #define G_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) >> 28) & 0x1) 186*1099013bSjsg #define C_000030_BUS_MSTR_DISCONNECT_EN 0xEFFFFFFF 187*1099013bSjsg #define S_000030_SERR_EN(x) (((x) & 0x1) << 29) 188*1099013bSjsg #define G_000030_SERR_EN(x) (((x) >> 29) & 0x1) 189*1099013bSjsg #define C_000030_SERR_EN 0xDFFFFFFF 190*1099013bSjsg #define S_000030_BUS_READ_BURST(x) (((x) & 0x1) << 30) 191*1099013bSjsg #define G_000030_BUS_READ_BURST(x) (((x) >> 30) & 0x1) 192*1099013bSjsg #define C_000030_BUS_READ_BURST 0xBFFFFFFF 193*1099013bSjsg #define S_000030_BUS_RDY_READ_DLY(x) (((x) & 0x1) << 31) 194*1099013bSjsg #define G_000030_BUS_RDY_READ_DLY(x) (((x) >> 31) & 0x1) 195*1099013bSjsg #define C_000030_BUS_RDY_READ_DLY 0x7FFFFFFF 196*1099013bSjsg #define R_000040_GEN_INT_CNTL 0x000040 197*1099013bSjsg #define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0) 198*1099013bSjsg #define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1) 199*1099013bSjsg #define C_000040_CRTC_VBLANK 0xFFFFFFFE 200*1099013bSjsg #define S_000040_CRTC_VLINE(x) (((x) & 0x1) << 1) 201*1099013bSjsg #define G_000040_CRTC_VLINE(x) (((x) >> 1) & 0x1) 202*1099013bSjsg #define C_000040_CRTC_VLINE 0xFFFFFFFD 203*1099013bSjsg #define S_000040_CRTC_VSYNC(x) (((x) & 0x1) << 2) 204*1099013bSjsg #define G_000040_CRTC_VSYNC(x) (((x) >> 2) & 0x1) 205*1099013bSjsg #define C_000040_CRTC_VSYNC 0xFFFFFFFB 206*1099013bSjsg #define S_000040_SNAPSHOT(x) (((x) & 0x1) << 3) 207*1099013bSjsg #define G_000040_SNAPSHOT(x) (((x) >> 3) & 0x1) 208*1099013bSjsg #define C_000040_SNAPSHOT 0xFFFFFFF7 209*1099013bSjsg #define S_000040_FP_DETECT(x) (((x) & 0x1) << 4) 210*1099013bSjsg #define G_000040_FP_DETECT(x) (((x) >> 4) & 0x1) 211*1099013bSjsg #define C_000040_FP_DETECT 0xFFFFFFEF 212*1099013bSjsg #define S_000040_CRTC2_VLINE(x) (((x) & 0x1) << 5) 213*1099013bSjsg #define G_000040_CRTC2_VLINE(x) (((x) >> 5) & 0x1) 214*1099013bSjsg #define C_000040_CRTC2_VLINE 0xFFFFFFDF 215*1099013bSjsg #define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12) 216*1099013bSjsg #define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1) 217*1099013bSjsg #define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF 218*1099013bSjsg #define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6) 219*1099013bSjsg #define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1) 220*1099013bSjsg #define C_000040_CRTC2_VSYNC 0xFFFFFFBF 221*1099013bSjsg #define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7) 222*1099013bSjsg #define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1) 223*1099013bSjsg #define C_000040_SNAPSHOT2 0xFFFFFF7F 224*1099013bSjsg #define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9) 225*1099013bSjsg #define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1) 226*1099013bSjsg #define C_000040_CRTC2_VBLANK 0xFFFFFDFF 227*1099013bSjsg #define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10) 228*1099013bSjsg #define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1) 229*1099013bSjsg #define C_000040_FP2_DETECT 0xFFFFFBFF 230*1099013bSjsg #define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11) 231*1099013bSjsg #define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1) 232*1099013bSjsg #define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF 233*1099013bSjsg #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) 234*1099013bSjsg #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) 235*1099013bSjsg #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF 236*1099013bSjsg #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) 237*1099013bSjsg #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) 238*1099013bSjsg #define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF 239*1099013bSjsg #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) 240*1099013bSjsg #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) 241*1099013bSjsg #define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF 242*1099013bSjsg #define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) 243*1099013bSjsg #define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) 244*1099013bSjsg #define C_000040_I2C_INT_EN 0xFFFDFFFF 245*1099013bSjsg #define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) 246*1099013bSjsg #define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) 247*1099013bSjsg #define C_000040_GUI_IDLE 0xFFF7FFFF 248*1099013bSjsg #define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) 249*1099013bSjsg #define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) 250*1099013bSjsg #define C_000040_VIPH_INT_EN 0xFEFFFFFF 251*1099013bSjsg #define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) 252*1099013bSjsg #define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) 253*1099013bSjsg #define C_000040_SW_INT_EN 0xFDFFFFFF 254*1099013bSjsg #define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) 255*1099013bSjsg #define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) 256*1099013bSjsg #define C_000040_GEYSERVILLE 0xF7FFFFFF 257*1099013bSjsg #define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) 258*1099013bSjsg #define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) 259*1099013bSjsg #define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF 260*1099013bSjsg #define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) 261*1099013bSjsg #define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) 262*1099013bSjsg #define C_000040_DVI_I2C_INT 0xDFFFFFFF 263*1099013bSjsg #define S_000040_GUIDMA(x) (((x) & 0x1) << 30) 264*1099013bSjsg #define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) 265*1099013bSjsg #define C_000040_GUIDMA 0xBFFFFFFF 266*1099013bSjsg #define S_000040_VIDDMA(x) (((x) & 0x1) << 31) 267*1099013bSjsg #define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) 268*1099013bSjsg #define C_000040_VIDDMA 0x7FFFFFFF 269*1099013bSjsg #define R_000044_GEN_INT_STATUS 0x000044 270*1099013bSjsg #define S_000044_CRTC_VBLANK_STAT(x) (((x) & 0x1) << 0) 271*1099013bSjsg #define G_000044_CRTC_VBLANK_STAT(x) (((x) >> 0) & 0x1) 272*1099013bSjsg #define C_000044_CRTC_VBLANK_STAT 0xFFFFFFFE 273*1099013bSjsg #define S_000044_CRTC_VBLANK_STAT_AK(x) (((x) & 0x1) << 0) 274*1099013bSjsg #define G_000044_CRTC_VBLANK_STAT_AK(x) (((x) >> 0) & 0x1) 275*1099013bSjsg #define C_000044_CRTC_VBLANK_STAT_AK 0xFFFFFFFE 276*1099013bSjsg #define S_000044_CRTC_VLINE_STAT(x) (((x) & 0x1) << 1) 277*1099013bSjsg #define G_000044_CRTC_VLINE_STAT(x) (((x) >> 1) & 0x1) 278*1099013bSjsg #define C_000044_CRTC_VLINE_STAT 0xFFFFFFFD 279*1099013bSjsg #define S_000044_CRTC_VLINE_STAT_AK(x) (((x) & 0x1) << 1) 280*1099013bSjsg #define G_000044_CRTC_VLINE_STAT_AK(x) (((x) >> 1) & 0x1) 281*1099013bSjsg #define C_000044_CRTC_VLINE_STAT_AK 0xFFFFFFFD 282*1099013bSjsg #define S_000044_CRTC_VSYNC_STAT(x) (((x) & 0x1) << 2) 283*1099013bSjsg #define G_000044_CRTC_VSYNC_STAT(x) (((x) >> 2) & 0x1) 284*1099013bSjsg #define C_000044_CRTC_VSYNC_STAT 0xFFFFFFFB 285*1099013bSjsg #define S_000044_CRTC_VSYNC_STAT_AK(x) (((x) & 0x1) << 2) 286*1099013bSjsg #define G_000044_CRTC_VSYNC_STAT_AK(x) (((x) >> 2) & 0x1) 287*1099013bSjsg #define C_000044_CRTC_VSYNC_STAT_AK 0xFFFFFFFB 288*1099013bSjsg #define S_000044_SNAPSHOT_STAT(x) (((x) & 0x1) << 3) 289*1099013bSjsg #define G_000044_SNAPSHOT_STAT(x) (((x) >> 3) & 0x1) 290*1099013bSjsg #define C_000044_SNAPSHOT_STAT 0xFFFFFFF7 291*1099013bSjsg #define S_000044_SNAPSHOT_STAT_AK(x) (((x) & 0x1) << 3) 292*1099013bSjsg #define G_000044_SNAPSHOT_STAT_AK(x) (((x) >> 3) & 0x1) 293*1099013bSjsg #define C_000044_SNAPSHOT_STAT_AK 0xFFFFFFF7 294*1099013bSjsg #define S_000044_FP_DETECT_STAT(x) (((x) & 0x1) << 4) 295*1099013bSjsg #define G_000044_FP_DETECT_STAT(x) (((x) >> 4) & 0x1) 296*1099013bSjsg #define C_000044_FP_DETECT_STAT 0xFFFFFFEF 297*1099013bSjsg #define S_000044_FP_DETECT_STAT_AK(x) (((x) & 0x1) << 4) 298*1099013bSjsg #define G_000044_FP_DETECT_STAT_AK(x) (((x) >> 4) & 0x1) 299*1099013bSjsg #define C_000044_FP_DETECT_STAT_AK 0xFFFFFFEF 300*1099013bSjsg #define S_000044_CRTC2_VLINE_STAT(x) (((x) & 0x1) << 5) 301*1099013bSjsg #define G_000044_CRTC2_VLINE_STAT(x) (((x) >> 5) & 0x1) 302*1099013bSjsg #define C_000044_CRTC2_VLINE_STAT 0xFFFFFFDF 303*1099013bSjsg #define S_000044_CRTC2_VLINE_STAT_AK(x) (((x) & 0x1) << 5) 304*1099013bSjsg #define G_000044_CRTC2_VLINE_STAT_AK(x) (((x) >> 5) & 0x1) 305*1099013bSjsg #define C_000044_CRTC2_VLINE_STAT_AK 0xFFFFFFDF 306*1099013bSjsg #define S_000044_CRTC2_VSYNC_STAT(x) (((x) & 0x1) << 6) 307*1099013bSjsg #define G_000044_CRTC2_VSYNC_STAT(x) (((x) >> 6) & 0x1) 308*1099013bSjsg #define C_000044_CRTC2_VSYNC_STAT 0xFFFFFFBF 309*1099013bSjsg #define S_000044_CRTC2_VSYNC_STAT_AK(x) (((x) & 0x1) << 6) 310*1099013bSjsg #define G_000044_CRTC2_VSYNC_STAT_AK(x) (((x) >> 6) & 0x1) 311*1099013bSjsg #define C_000044_CRTC2_VSYNC_STAT_AK 0xFFFFFFBF 312*1099013bSjsg #define S_000044_SNAPSHOT2_STAT(x) (((x) & 0x1) << 7) 313*1099013bSjsg #define G_000044_SNAPSHOT2_STAT(x) (((x) >> 7) & 0x1) 314*1099013bSjsg #define C_000044_SNAPSHOT2_STAT 0xFFFFFF7F 315*1099013bSjsg #define S_000044_SNAPSHOT2_STAT_AK(x) (((x) & 0x1) << 7) 316*1099013bSjsg #define G_000044_SNAPSHOT2_STAT_AK(x) (((x) >> 7) & 0x1) 317*1099013bSjsg #define C_000044_SNAPSHOT2_STAT_AK 0xFFFFFF7F 318*1099013bSjsg #define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8) 319*1099013bSjsg #define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1) 320*1099013bSjsg #define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF 321*1099013bSjsg #define S_000044_CRTC2_VBLANK_STAT(x) (((x) & 0x1) << 9) 322*1099013bSjsg #define G_000044_CRTC2_VBLANK_STAT(x) (((x) >> 9) & 0x1) 323*1099013bSjsg #define C_000044_CRTC2_VBLANK_STAT 0xFFFFFDFF 324*1099013bSjsg #define S_000044_CRTC2_VBLANK_STAT_AK(x) (((x) & 0x1) << 9) 325*1099013bSjsg #define G_000044_CRTC2_VBLANK_STAT_AK(x) (((x) >> 9) & 0x1) 326*1099013bSjsg #define C_000044_CRTC2_VBLANK_STAT_AK 0xFFFFFDFF 327*1099013bSjsg #define S_000044_FP2_DETECT_STAT(x) (((x) & 0x1) << 10) 328*1099013bSjsg #define G_000044_FP2_DETECT_STAT(x) (((x) >> 10) & 0x1) 329*1099013bSjsg #define C_000044_FP2_DETECT_STAT 0xFFFFFBFF 330*1099013bSjsg #define S_000044_FP2_DETECT_STAT_AK(x) (((x) & 0x1) << 10) 331*1099013bSjsg #define G_000044_FP2_DETECT_STAT_AK(x) (((x) >> 10) & 0x1) 332*1099013bSjsg #define C_000044_FP2_DETECT_STAT_AK 0xFFFFFBFF 333*1099013bSjsg #define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) & 0x1) << 11) 334*1099013bSjsg #define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) >> 11) & 0x1) 335*1099013bSjsg #define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT 0xFFFFF7FF 336*1099013bSjsg #define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) & 0x1) << 11) 337*1099013bSjsg #define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) >> 11) & 0x1) 338*1099013bSjsg #define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK 0xFFFFF7FF 339*1099013bSjsg #define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12) 340*1099013bSjsg #define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1) 341*1099013bSjsg #define C_000044_DMA_VIPH0_INT 0xFFFFEFFF 342*1099013bSjsg #define S_000044_DMA_VIPH0_INT_AK(x) (((x) & 0x1) << 12) 343*1099013bSjsg #define G_000044_DMA_VIPH0_INT_AK(x) (((x) >> 12) & 0x1) 344*1099013bSjsg #define C_000044_DMA_VIPH0_INT_AK 0xFFFFEFFF 345*1099013bSjsg #define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13) 346*1099013bSjsg #define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1) 347*1099013bSjsg #define C_000044_DMA_VIPH1_INT 0xFFFFDFFF 348*1099013bSjsg #define S_000044_DMA_VIPH1_INT_AK(x) (((x) & 0x1) << 13) 349*1099013bSjsg #define G_000044_DMA_VIPH1_INT_AK(x) (((x) >> 13) & 0x1) 350*1099013bSjsg #define C_000044_DMA_VIPH1_INT_AK 0xFFFFDFFF 351*1099013bSjsg #define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14) 352*1099013bSjsg #define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1) 353*1099013bSjsg #define C_000044_DMA_VIPH2_INT 0xFFFFBFFF 354*1099013bSjsg #define S_000044_DMA_VIPH2_INT_AK(x) (((x) & 0x1) << 14) 355*1099013bSjsg #define G_000044_DMA_VIPH2_INT_AK(x) (((x) >> 14) & 0x1) 356*1099013bSjsg #define C_000044_DMA_VIPH2_INT_AK 0xFFFFBFFF 357*1099013bSjsg #define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15) 358*1099013bSjsg #define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1) 359*1099013bSjsg #define C_000044_DMA_VIPH3_INT 0xFFFF7FFF 360*1099013bSjsg #define S_000044_DMA_VIPH3_INT_AK(x) (((x) & 0x1) << 15) 361*1099013bSjsg #define G_000044_DMA_VIPH3_INT_AK(x) (((x) >> 15) & 0x1) 362*1099013bSjsg #define C_000044_DMA_VIPH3_INT_AK 0xFFFF7FFF 363*1099013bSjsg #define S_000044_I2C_INT(x) (((x) & 0x1) << 17) 364*1099013bSjsg #define G_000044_I2C_INT(x) (((x) >> 17) & 0x1) 365*1099013bSjsg #define C_000044_I2C_INT 0xFFFDFFFF 366*1099013bSjsg #define S_000044_I2C_INT_AK(x) (((x) & 0x1) << 17) 367*1099013bSjsg #define G_000044_I2C_INT_AK(x) (((x) >> 17) & 0x1) 368*1099013bSjsg #define C_000044_I2C_INT_AK 0xFFFDFFFF 369*1099013bSjsg #define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19) 370*1099013bSjsg #define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1) 371*1099013bSjsg #define C_000044_GUI_IDLE_STAT 0xFFF7FFFF 372*1099013bSjsg #define S_000044_GUI_IDLE_STAT_AK(x) (((x) & 0x1) << 19) 373*1099013bSjsg #define G_000044_GUI_IDLE_STAT_AK(x) (((x) >> 19) & 0x1) 374*1099013bSjsg #define C_000044_GUI_IDLE_STAT_AK 0xFFF7FFFF 375*1099013bSjsg #define S_000044_VIPH_INT(x) (((x) & 0x1) << 24) 376*1099013bSjsg #define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1) 377*1099013bSjsg #define C_000044_VIPH_INT 0xFEFFFFFF 378*1099013bSjsg #define S_000044_SW_INT(x) (((x) & 0x1) << 25) 379*1099013bSjsg #define G_000044_SW_INT(x) (((x) >> 25) & 0x1) 380*1099013bSjsg #define C_000044_SW_INT 0xFDFFFFFF 381*1099013bSjsg #define S_000044_SW_INT_AK(x) (((x) & 0x1) << 25) 382*1099013bSjsg #define G_000044_SW_INT_AK(x) (((x) >> 25) & 0x1) 383*1099013bSjsg #define C_000044_SW_INT_AK 0xFDFFFFFF 384*1099013bSjsg #define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26) 385*1099013bSjsg #define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1) 386*1099013bSjsg #define C_000044_SW_INT_SET 0xFBFFFFFF 387*1099013bSjsg #define S_000044_GEYSERVILLE_STAT(x) (((x) & 0x1) << 27) 388*1099013bSjsg #define G_000044_GEYSERVILLE_STAT(x) (((x) >> 27) & 0x1) 389*1099013bSjsg #define C_000044_GEYSERVILLE_STAT 0xF7FFFFFF 390*1099013bSjsg #define S_000044_GEYSERVILLE_STAT_AK(x) (((x) & 0x1) << 27) 391*1099013bSjsg #define G_000044_GEYSERVILLE_STAT_AK(x) (((x) >> 27) & 0x1) 392*1099013bSjsg #define C_000044_GEYSERVILLE_STAT_AK 0xF7FFFFFF 393*1099013bSjsg #define S_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) & 0x1) << 28) 394*1099013bSjsg #define G_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) >> 28) & 0x1) 395*1099013bSjsg #define C_000044_HDCP_AUTHORIZED_INT_STAT 0xEFFFFFFF 396*1099013bSjsg #define S_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) & 0x1) << 28) 397*1099013bSjsg #define G_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) >> 28) & 0x1) 398*1099013bSjsg #define C_000044_HDCP_AUTHORIZED_INT_AK 0xEFFFFFFF 399*1099013bSjsg #define S_000044_DVI_I2C_INT_STAT(x) (((x) & 0x1) << 29) 400*1099013bSjsg #define G_000044_DVI_I2C_INT_STAT(x) (((x) >> 29) & 0x1) 401*1099013bSjsg #define C_000044_DVI_I2C_INT_STAT 0xDFFFFFFF 402*1099013bSjsg #define S_000044_DVI_I2C_INT_AK(x) (((x) & 0x1) << 29) 403*1099013bSjsg #define G_000044_DVI_I2C_INT_AK(x) (((x) >> 29) & 0x1) 404*1099013bSjsg #define C_000044_DVI_I2C_INT_AK 0xDFFFFFFF 405*1099013bSjsg #define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30) 406*1099013bSjsg #define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1) 407*1099013bSjsg #define C_000044_GUIDMA_STAT 0xBFFFFFFF 408*1099013bSjsg #define S_000044_GUIDMA_AK(x) (((x) & 0x1) << 30) 409*1099013bSjsg #define G_000044_GUIDMA_AK(x) (((x) >> 30) & 0x1) 410*1099013bSjsg #define C_000044_GUIDMA_AK 0xBFFFFFFF 411*1099013bSjsg #define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31) 412*1099013bSjsg #define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1) 413*1099013bSjsg #define C_000044_VIDDMA_STAT 0x7FFFFFFF 414*1099013bSjsg #define S_000044_VIDDMA_AK(x) (((x) & 0x1) << 31) 415*1099013bSjsg #define G_000044_VIDDMA_AK(x) (((x) >> 31) & 0x1) 416*1099013bSjsg #define C_000044_VIDDMA_AK 0x7FFFFFFF 417*1099013bSjsg #define R_000050_CRTC_GEN_CNTL 0x000050 418*1099013bSjsg #define S_000050_CRTC_DBL_SCAN_EN(x) (((x) & 0x1) << 0) 419*1099013bSjsg #define G_000050_CRTC_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) 420*1099013bSjsg #define C_000050_CRTC_DBL_SCAN_EN 0xFFFFFFFE 421*1099013bSjsg #define S_000050_CRTC_INTERLACE_EN(x) (((x) & 0x1) << 1) 422*1099013bSjsg #define G_000050_CRTC_INTERLACE_EN(x) (((x) >> 1) & 0x1) 423*1099013bSjsg #define C_000050_CRTC_INTERLACE_EN 0xFFFFFFFD 424*1099013bSjsg #define S_000050_CRTC_C_SYNC_EN(x) (((x) & 0x1) << 4) 425*1099013bSjsg #define G_000050_CRTC_C_SYNC_EN(x) (((x) >> 4) & 0x1) 426*1099013bSjsg #define C_000050_CRTC_C_SYNC_EN 0xFFFFFFEF 427*1099013bSjsg #define S_000050_CRTC_PIX_WIDTH(x) (((x) & 0xF) << 8) 428*1099013bSjsg #define G_000050_CRTC_PIX_WIDTH(x) (((x) >> 8) & 0xF) 429*1099013bSjsg #define C_000050_CRTC_PIX_WIDTH 0xFFFFF0FF 430*1099013bSjsg #define S_000050_CRTC_ICON_EN(x) (((x) & 0x1) << 15) 431*1099013bSjsg #define G_000050_CRTC_ICON_EN(x) (((x) >> 15) & 0x1) 432*1099013bSjsg #define C_000050_CRTC_ICON_EN 0xFFFF7FFF 433*1099013bSjsg #define S_000050_CRTC_CUR_EN(x) (((x) & 0x1) << 16) 434*1099013bSjsg #define G_000050_CRTC_CUR_EN(x) (((x) >> 16) & 0x1) 435*1099013bSjsg #define C_000050_CRTC_CUR_EN 0xFFFEFFFF 436*1099013bSjsg #define S_000050_CRTC_VSTAT_MODE(x) (((x) & 0x3) << 17) 437*1099013bSjsg #define G_000050_CRTC_VSTAT_MODE(x) (((x) >> 17) & 0x3) 438*1099013bSjsg #define C_000050_CRTC_VSTAT_MODE 0xFFF9FFFF 439*1099013bSjsg #define S_000050_CRTC_CUR_MODE(x) (((x) & 0x7) << 20) 440*1099013bSjsg #define G_000050_CRTC_CUR_MODE(x) (((x) >> 20) & 0x7) 441*1099013bSjsg #define C_000050_CRTC_CUR_MODE 0xFF8FFFFF 442*1099013bSjsg #define S_000050_CRTC_EXT_DISP_EN(x) (((x) & 0x1) << 24) 443*1099013bSjsg #define G_000050_CRTC_EXT_DISP_EN(x) (((x) >> 24) & 0x1) 444*1099013bSjsg #define C_000050_CRTC_EXT_DISP_EN 0xFEFFFFFF 445*1099013bSjsg #define S_000050_CRTC_EN(x) (((x) & 0x1) << 25) 446*1099013bSjsg #define G_000050_CRTC_EN(x) (((x) >> 25) & 0x1) 447*1099013bSjsg #define C_000050_CRTC_EN 0xFDFFFFFF 448*1099013bSjsg #define S_000050_CRTC_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) 449*1099013bSjsg #define G_000050_CRTC_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) 450*1099013bSjsg #define C_000050_CRTC_DISP_REQ_EN_B 0xFBFFFFFF 451*1099013bSjsg #define R_000054_CRTC_EXT_CNTL 0x000054 452*1099013bSjsg #define S_000054_CRTC_VGA_XOVERSCAN(x) (((x) & 0x1) << 0) 453*1099013bSjsg #define G_000054_CRTC_VGA_XOVERSCAN(x) (((x) >> 0) & 0x1) 454*1099013bSjsg #define C_000054_CRTC_VGA_XOVERSCAN 0xFFFFFFFE 455*1099013bSjsg #define S_000054_VGA_BLINK_RATE(x) (((x) & 0x3) << 1) 456*1099013bSjsg #define G_000054_VGA_BLINK_RATE(x) (((x) >> 1) & 0x3) 457*1099013bSjsg #define C_000054_VGA_BLINK_RATE 0xFFFFFFF9 458*1099013bSjsg #define S_000054_VGA_ATI_LINEAR(x) (((x) & 0x1) << 3) 459*1099013bSjsg #define G_000054_VGA_ATI_LINEAR(x) (((x) >> 3) & 0x1) 460*1099013bSjsg #define C_000054_VGA_ATI_LINEAR 0xFFFFFFF7 461*1099013bSjsg #define S_000054_VGA_128KAP_PAGING(x) (((x) & 0x1) << 4) 462*1099013bSjsg #define G_000054_VGA_128KAP_PAGING(x) (((x) >> 4) & 0x1) 463*1099013bSjsg #define C_000054_VGA_128KAP_PAGING 0xFFFFFFEF 464*1099013bSjsg #define S_000054_VGA_TEXT_132(x) (((x) & 0x1) << 5) 465*1099013bSjsg #define G_000054_VGA_TEXT_132(x) (((x) >> 5) & 0x1) 466*1099013bSjsg #define C_000054_VGA_TEXT_132 0xFFFFFFDF 467*1099013bSjsg #define S_000054_VGA_XCRT_CNT_EN(x) (((x) & 0x1) << 6) 468*1099013bSjsg #define G_000054_VGA_XCRT_CNT_EN(x) (((x) >> 6) & 0x1) 469*1099013bSjsg #define C_000054_VGA_XCRT_CNT_EN 0xFFFFFFBF 470*1099013bSjsg #define S_000054_CRTC_HSYNC_DIS(x) (((x) & 0x1) << 8) 471*1099013bSjsg #define G_000054_CRTC_HSYNC_DIS(x) (((x) >> 8) & 0x1) 472*1099013bSjsg #define C_000054_CRTC_HSYNC_DIS 0xFFFFFEFF 473*1099013bSjsg #define S_000054_CRTC_VSYNC_DIS(x) (((x) & 0x1) << 9) 474*1099013bSjsg #define G_000054_CRTC_VSYNC_DIS(x) (((x) >> 9) & 0x1) 475*1099013bSjsg #define C_000054_CRTC_VSYNC_DIS 0xFFFFFDFF 476*1099013bSjsg #define S_000054_CRTC_DISPLAY_DIS(x) (((x) & 0x1) << 10) 477*1099013bSjsg #define G_000054_CRTC_DISPLAY_DIS(x) (((x) >> 10) & 0x1) 478*1099013bSjsg #define C_000054_CRTC_DISPLAY_DIS 0xFFFFFBFF 479*1099013bSjsg #define S_000054_CRTC_SYNC_TRISTATE(x) (((x) & 0x1) << 11) 480*1099013bSjsg #define G_000054_CRTC_SYNC_TRISTATE(x) (((x) >> 11) & 0x1) 481*1099013bSjsg #define C_000054_CRTC_SYNC_TRISTATE 0xFFFFF7FF 482*1099013bSjsg #define S_000054_CRTC_HSYNC_TRISTATE(x) (((x) & 0x1) << 12) 483*1099013bSjsg #define G_000054_CRTC_HSYNC_TRISTATE(x) (((x) >> 12) & 0x1) 484*1099013bSjsg #define C_000054_CRTC_HSYNC_TRISTATE 0xFFFFEFFF 485*1099013bSjsg #define S_000054_CRTC_VSYNC_TRISTATE(x) (((x) & 0x1) << 13) 486*1099013bSjsg #define G_000054_CRTC_VSYNC_TRISTATE(x) (((x) >> 13) & 0x1) 487*1099013bSjsg #define C_000054_CRTC_VSYNC_TRISTATE 0xFFFFDFFF 488*1099013bSjsg #define S_000054_CRT_ON(x) (((x) & 0x1) << 15) 489*1099013bSjsg #define G_000054_CRT_ON(x) (((x) >> 15) & 0x1) 490*1099013bSjsg #define C_000054_CRT_ON 0xFFFF7FFF 491*1099013bSjsg #define S_000054_VGA_CUR_B_TEST(x) (((x) & 0x1) << 17) 492*1099013bSjsg #define G_000054_VGA_CUR_B_TEST(x) (((x) >> 17) & 0x1) 493*1099013bSjsg #define C_000054_VGA_CUR_B_TEST 0xFFFDFFFF 494*1099013bSjsg #define S_000054_VGA_PACK_DIS(x) (((x) & 0x1) << 18) 495*1099013bSjsg #define G_000054_VGA_PACK_DIS(x) (((x) >> 18) & 0x1) 496*1099013bSjsg #define C_000054_VGA_PACK_DIS 0xFFFBFFFF 497*1099013bSjsg #define S_000054_VGA_MEM_PS_EN(x) (((x) & 0x1) << 19) 498*1099013bSjsg #define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1) 499*1099013bSjsg #define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF 500*1099013bSjsg #define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24) 501*1099013bSjsg #define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F) 502*1099013bSjsg #define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF 503*1099013bSjsg #define R_000148_MC_FB_LOCATION 0x000148 504*1099013bSjsg #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) 505*1099013bSjsg #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) 506*1099013bSjsg #define C_000148_MC_FB_START 0xFFFF0000 507*1099013bSjsg #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) 508*1099013bSjsg #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) 509*1099013bSjsg #define C_000148_MC_FB_TOP 0x0000FFFF 510*1099013bSjsg #define R_00014C_MC_AGP_LOCATION 0x00014C 511*1099013bSjsg #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) 512*1099013bSjsg #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) 513*1099013bSjsg #define C_00014C_MC_AGP_START 0xFFFF0000 514*1099013bSjsg #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) 515*1099013bSjsg #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) 516*1099013bSjsg #define C_00014C_MC_AGP_TOP 0x0000FFFF 517*1099013bSjsg #define R_000170_AGP_BASE 0x000170 518*1099013bSjsg #define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 519*1099013bSjsg #define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 520*1099013bSjsg #define C_000170_AGP_BASE_ADDR 0x00000000 521*1099013bSjsg #define R_00023C_DISPLAY_BASE_ADDR 0x00023C 522*1099013bSjsg #define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 523*1099013bSjsg #define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 524*1099013bSjsg #define C_00023C_DISPLAY_BASE_ADDR 0x00000000 525*1099013bSjsg #define R_000260_CUR_OFFSET 0x000260 526*1099013bSjsg #define S_000260_CUR_OFFSET(x) (((x) & 0x7FFFFFF) << 0) 527*1099013bSjsg #define G_000260_CUR_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) 528*1099013bSjsg #define C_000260_CUR_OFFSET 0xF8000000 529*1099013bSjsg #define S_000260_CUR_LOCK(x) (((x) & 0x1) << 31) 530*1099013bSjsg #define G_000260_CUR_LOCK(x) (((x) >> 31) & 0x1) 531*1099013bSjsg #define C_000260_CUR_LOCK 0x7FFFFFFF 532*1099013bSjsg #define R_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00033C 533*1099013bSjsg #define S_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 534*1099013bSjsg #define G_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 535*1099013bSjsg #define C_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00000000 536*1099013bSjsg #define R_000360_CUR2_OFFSET 0x000360 537*1099013bSjsg #define S_000360_CUR2_OFFSET(x) (((x) & 0x7FFFFFF) << 0) 538*1099013bSjsg #define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) 539*1099013bSjsg #define C_000360_CUR2_OFFSET 0xF8000000 540*1099013bSjsg #define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) 541*1099013bSjsg #define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) 542*1099013bSjsg #define C_000360_CUR2_LOCK 0x7FFFFFFF 543*1099013bSjsg #define R_0003C2_GENMO_WT 0x0003C2 544*1099013bSjsg #define S_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) 545*1099013bSjsg #define G_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) 546*1099013bSjsg #define C_0003C2_GENMO_MONO_ADDRESS_B 0xFE 547*1099013bSjsg #define S_0003C2_VGA_RAM_EN(x) (((x) & 0x1) << 1) 548*1099013bSjsg #define G_0003C2_VGA_RAM_EN(x) (((x) >> 1) & 0x1) 549*1099013bSjsg #define C_0003C2_VGA_RAM_EN 0xFD 550*1099013bSjsg #define S_0003C2_VGA_CKSEL(x) (((x) & 0x3) << 2) 551*1099013bSjsg #define G_0003C2_VGA_CKSEL(x) (((x) >> 2) & 0x3) 552*1099013bSjsg #define C_0003C2_VGA_CKSEL 0xF3 553*1099013bSjsg #define S_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) 554*1099013bSjsg #define G_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) 555*1099013bSjsg #define C_0003C2_ODD_EVEN_MD_PGSEL 0xDF 556*1099013bSjsg #define S_0003C2_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) 557*1099013bSjsg #define G_0003C2_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) 558*1099013bSjsg #define C_0003C2_VGA_HSYNC_POL 0xBF 559*1099013bSjsg #define S_0003C2_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) 560*1099013bSjsg #define G_0003C2_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) 561*1099013bSjsg #define C_0003C2_VGA_VSYNC_POL 0x7F 562*1099013bSjsg #define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 563*1099013bSjsg #define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) 564*1099013bSjsg #define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) 565*1099013bSjsg #define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE 566*1099013bSjsg #define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1) 567*1099013bSjsg #define G_0003F8_CRTC2_INTERLACE_EN(x) (((x) >> 1) & 0x1) 568*1099013bSjsg #define C_0003F8_CRTC2_INTERLACE_EN 0xFFFFFFFD 569*1099013bSjsg #define S_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) & 0x1) << 4) 570*1099013bSjsg #define G_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) >> 4) & 0x1) 571*1099013bSjsg #define C_0003F8_CRTC2_SYNC_TRISTATE 0xFFFFFFEF 572*1099013bSjsg #define S_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) & 0x1) << 5) 573*1099013bSjsg #define G_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) >> 5) & 0x1) 574*1099013bSjsg #define C_0003F8_CRTC2_HSYNC_TRISTATE 0xFFFFFFDF 575*1099013bSjsg #define S_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) & 0x1) << 6) 576*1099013bSjsg #define G_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) >> 6) & 0x1) 577*1099013bSjsg #define C_0003F8_CRTC2_VSYNC_TRISTATE 0xFFFFFFBF 578*1099013bSjsg #define S_0003F8_CRT2_ON(x) (((x) & 0x1) << 7) 579*1099013bSjsg #define G_0003F8_CRT2_ON(x) (((x) >> 7) & 0x1) 580*1099013bSjsg #define C_0003F8_CRT2_ON 0xFFFFFF7F 581*1099013bSjsg #define S_0003F8_CRTC2_PIX_WIDTH(x) (((x) & 0xF) << 8) 582*1099013bSjsg #define G_0003F8_CRTC2_PIX_WIDTH(x) (((x) >> 8) & 0xF) 583*1099013bSjsg #define C_0003F8_CRTC2_PIX_WIDTH 0xFFFFF0FF 584*1099013bSjsg #define S_0003F8_CRTC2_ICON_EN(x) (((x) & 0x1) << 15) 585*1099013bSjsg #define G_0003F8_CRTC2_ICON_EN(x) (((x) >> 15) & 0x1) 586*1099013bSjsg #define C_0003F8_CRTC2_ICON_EN 0xFFFF7FFF 587*1099013bSjsg #define S_0003F8_CRTC2_CUR_EN(x) (((x) & 0x1) << 16) 588*1099013bSjsg #define G_0003F8_CRTC2_CUR_EN(x) (((x) >> 16) & 0x1) 589*1099013bSjsg #define C_0003F8_CRTC2_CUR_EN 0xFFFEFFFF 590*1099013bSjsg #define S_0003F8_CRTC2_CUR_MODE(x) (((x) & 0x7) << 20) 591*1099013bSjsg #define G_0003F8_CRTC2_CUR_MODE(x) (((x) >> 20) & 0x7) 592*1099013bSjsg #define C_0003F8_CRTC2_CUR_MODE 0xFF8FFFFF 593*1099013bSjsg #define S_0003F8_CRTC2_DISPLAY_DIS(x) (((x) & 0x1) << 23) 594*1099013bSjsg #define G_0003F8_CRTC2_DISPLAY_DIS(x) (((x) >> 23) & 0x1) 595*1099013bSjsg #define C_0003F8_CRTC2_DISPLAY_DIS 0xFF7FFFFF 596*1099013bSjsg #define S_0003F8_CRTC2_EN(x) (((x) & 0x1) << 25) 597*1099013bSjsg #define G_0003F8_CRTC2_EN(x) (((x) >> 25) & 0x1) 598*1099013bSjsg #define C_0003F8_CRTC2_EN 0xFDFFFFFF 599*1099013bSjsg #define S_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) 600*1099013bSjsg #define G_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) 601*1099013bSjsg #define C_0003F8_CRTC2_DISP_REQ_EN_B 0xFBFFFFFF 602*1099013bSjsg #define S_0003F8_CRTC2_C_SYNC_EN(x) (((x) & 0x1) << 27) 603*1099013bSjsg #define G_0003F8_CRTC2_C_SYNC_EN(x) (((x) >> 27) & 0x1) 604*1099013bSjsg #define C_0003F8_CRTC2_C_SYNC_EN 0xF7FFFFFF 605*1099013bSjsg #define S_0003F8_CRTC2_HSYNC_DIS(x) (((x) & 0x1) << 28) 606*1099013bSjsg #define G_0003F8_CRTC2_HSYNC_DIS(x) (((x) >> 28) & 0x1) 607*1099013bSjsg #define C_0003F8_CRTC2_HSYNC_DIS 0xEFFFFFFF 608*1099013bSjsg #define S_0003F8_CRTC2_VSYNC_DIS(x) (((x) & 0x1) << 29) 609*1099013bSjsg #define G_0003F8_CRTC2_VSYNC_DIS(x) (((x) >> 29) & 0x1) 610*1099013bSjsg #define C_0003F8_CRTC2_VSYNC_DIS 0xDFFFFFFF 611*1099013bSjsg #define R_000420_OV0_SCALE_CNTL 0x000420 612*1099013bSjsg #define S_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) & 0x1) << 1) 613*1099013bSjsg #define G_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) >> 1) & 0x1) 614*1099013bSjsg #define C_000420_OV0_NO_READ_BEHIND_SCAN 0xFFFFFFFD 615*1099013bSjsg #define S_000420_OV0_HORZ_PICK_NEAREST(x) (((x) & 0x1) << 2) 616*1099013bSjsg #define G_000420_OV0_HORZ_PICK_NEAREST(x) (((x) >> 2) & 0x1) 617*1099013bSjsg #define C_000420_OV0_HORZ_PICK_NEAREST 0xFFFFFFFB 618*1099013bSjsg #define S_000420_OV0_VERT_PICK_NEAREST(x) (((x) & 0x1) << 3) 619*1099013bSjsg #define G_000420_OV0_VERT_PICK_NEAREST(x) (((x) >> 3) & 0x1) 620*1099013bSjsg #define C_000420_OV0_VERT_PICK_NEAREST 0xFFFFFFF7 621*1099013bSjsg #define S_000420_OV0_SIGNED_UV(x) (((x) & 0x1) << 4) 622*1099013bSjsg #define G_000420_OV0_SIGNED_UV(x) (((x) >> 4) & 0x1) 623*1099013bSjsg #define C_000420_OV0_SIGNED_UV 0xFFFFFFEF 624*1099013bSjsg #define S_000420_OV0_GAMMA_SEL(x) (((x) & 0x7) << 5) 625*1099013bSjsg #define G_000420_OV0_GAMMA_SEL(x) (((x) >> 5) & 0x7) 626*1099013bSjsg #define C_000420_OV0_GAMMA_SEL 0xFFFFFF1F 627*1099013bSjsg #define S_000420_OV0_SURFACE_FORMAT(x) (((x) & 0xF) << 8) 628*1099013bSjsg #define G_000420_OV0_SURFACE_FORMAT(x) (((x) >> 8) & 0xF) 629*1099013bSjsg #define C_000420_OV0_SURFACE_FORMAT 0xFFFFF0FF 630*1099013bSjsg #define S_000420_OV0_ADAPTIVE_DEINT(x) (((x) & 0x1) << 12) 631*1099013bSjsg #define G_000420_OV0_ADAPTIVE_DEINT(x) (((x) >> 12) & 0x1) 632*1099013bSjsg #define C_000420_OV0_ADAPTIVE_DEINT 0xFFFFEFFF 633*1099013bSjsg #define S_000420_OV0_CRTC_SEL(x) (((x) & 0x1) << 14) 634*1099013bSjsg #define G_000420_OV0_CRTC_SEL(x) (((x) >> 14) & 0x1) 635*1099013bSjsg #define C_000420_OV0_CRTC_SEL 0xFFFFBFFF 636*1099013bSjsg #define S_000420_OV0_BURST_PER_PLANE(x) (((x) & 0x7F) << 16) 637*1099013bSjsg #define G_000420_OV0_BURST_PER_PLANE(x) (((x) >> 16) & 0x7F) 638*1099013bSjsg #define C_000420_OV0_BURST_PER_PLANE 0xFF80FFFF 639*1099013bSjsg #define S_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) & 0x1) << 24) 640*1099013bSjsg #define G_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) >> 24) & 0x1) 641*1099013bSjsg #define C_000420_OV0_DOUBLE_BUFFER_REGS 0xFEFFFFFF 642*1099013bSjsg #define S_000420_OV0_BANDWIDTH(x) (((x) & 0x1) << 26) 643*1099013bSjsg #define G_000420_OV0_BANDWIDTH(x) (((x) >> 26) & 0x1) 644*1099013bSjsg #define C_000420_OV0_BANDWIDTH 0xFBFFFFFF 645*1099013bSjsg #define S_000420_OV0_LIN_TRANS_BYPASS(x) (((x) & 0x1) << 28) 646*1099013bSjsg #define G_000420_OV0_LIN_TRANS_BYPASS(x) (((x) >> 28) & 0x1) 647*1099013bSjsg #define C_000420_OV0_LIN_TRANS_BYPASS 0xEFFFFFFF 648*1099013bSjsg #define S_000420_OV0_INT_EMU(x) (((x) & 0x1) << 29) 649*1099013bSjsg #define G_000420_OV0_INT_EMU(x) (((x) >> 29) & 0x1) 650*1099013bSjsg #define C_000420_OV0_INT_EMU 0xDFFFFFFF 651*1099013bSjsg #define S_000420_OV0_OVERLAY_EN(x) (((x) & 0x1) << 30) 652*1099013bSjsg #define G_000420_OV0_OVERLAY_EN(x) (((x) >> 30) & 0x1) 653*1099013bSjsg #define C_000420_OV0_OVERLAY_EN 0xBFFFFFFF 654*1099013bSjsg #define S_000420_OV0_SOFT_RESET(x) (((x) & 0x1) << 31) 655*1099013bSjsg #define G_000420_OV0_SOFT_RESET(x) (((x) >> 31) & 0x1) 656*1099013bSjsg #define C_000420_OV0_SOFT_RESET 0x7FFFFFFF 657*1099013bSjsg #define R_00070C_CP_RB_RPTR_ADDR 0x00070C 658*1099013bSjsg #define S_00070C_RB_RPTR_SWAP(x) (((x) & 0x3) << 0) 659*1099013bSjsg #define G_00070C_RB_RPTR_SWAP(x) (((x) >> 0) & 0x3) 660*1099013bSjsg #define C_00070C_RB_RPTR_SWAP 0xFFFFFFFC 661*1099013bSjsg #define S_00070C_RB_RPTR_ADDR(x) (((x) & 0x3FFFFFFF) << 2) 662*1099013bSjsg #define G_00070C_RB_RPTR_ADDR(x) (((x) >> 2) & 0x3FFFFFFF) 663*1099013bSjsg #define C_00070C_RB_RPTR_ADDR 0x00000003 664*1099013bSjsg #define R_000740_CP_CSQ_CNTL 0x000740 665*1099013bSjsg #define S_000740_CSQ_CNT_PRIMARY(x) (((x) & 0xFF) << 0) 666*1099013bSjsg #define G_000740_CSQ_CNT_PRIMARY(x) (((x) >> 0) & 0xFF) 667*1099013bSjsg #define C_000740_CSQ_CNT_PRIMARY 0xFFFFFF00 668*1099013bSjsg #define S_000740_CSQ_CNT_INDIRECT(x) (((x) & 0xFF) << 8) 669*1099013bSjsg #define G_000740_CSQ_CNT_INDIRECT(x) (((x) >> 8) & 0xFF) 670*1099013bSjsg #define C_000740_CSQ_CNT_INDIRECT 0xFFFF00FF 671*1099013bSjsg #define S_000740_CSQ_MODE(x) (((x) & 0xF) << 28) 672*1099013bSjsg #define G_000740_CSQ_MODE(x) (((x) >> 28) & 0xF) 673*1099013bSjsg #define C_000740_CSQ_MODE 0x0FFFFFFF 674*1099013bSjsg #define R_000770_SCRATCH_UMSK 0x000770 675*1099013bSjsg #define S_000770_SCRATCH_UMSK(x) (((x) & 0x3F) << 0) 676*1099013bSjsg #define G_000770_SCRATCH_UMSK(x) (((x) >> 0) & 0x3F) 677*1099013bSjsg #define C_000770_SCRATCH_UMSK 0xFFFFFFC0 678*1099013bSjsg #define S_000770_SCRATCH_SWAP(x) (((x) & 0x3) << 16) 679*1099013bSjsg #define G_000770_SCRATCH_SWAP(x) (((x) >> 16) & 0x3) 680*1099013bSjsg #define C_000770_SCRATCH_SWAP 0xFFFCFFFF 681*1099013bSjsg #define R_000774_SCRATCH_ADDR 0x000774 682*1099013bSjsg #define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5) 683*1099013bSjsg #define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF) 684*1099013bSjsg #define C_000774_SCRATCH_ADDR 0x0000001F 685*1099013bSjsg #define R_0007C0_CP_STAT 0x0007C0 686*1099013bSjsg #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 687*1099013bSjsg #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 688*1099013bSjsg #define C_0007C0_MRU_BUSY 0xFFFFFFFE 689*1099013bSjsg #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 690*1099013bSjsg #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 691*1099013bSjsg #define C_0007C0_MWU_BUSY 0xFFFFFFFD 692*1099013bSjsg #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 693*1099013bSjsg #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 694*1099013bSjsg #define C_0007C0_RSIU_BUSY 0xFFFFFFFB 695*1099013bSjsg #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 696*1099013bSjsg #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 697*1099013bSjsg #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 698*1099013bSjsg #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 699*1099013bSjsg #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) 700*1099013bSjsg #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF 701*1099013bSjsg #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) 702*1099013bSjsg #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) 703*1099013bSjsg #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF 704*1099013bSjsg #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) 705*1099013bSjsg #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) 706*1099013bSjsg #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF 707*1099013bSjsg #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) 708*1099013bSjsg #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) 709*1099013bSjsg #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF 710*1099013bSjsg #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) 711*1099013bSjsg #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) 712*1099013bSjsg #define C_0007C0_CSI_BUSY 0xFFFFDFFF 713*1099013bSjsg #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) 714*1099013bSjsg #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) 715*1099013bSjsg #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF 716*1099013bSjsg #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) 717*1099013bSjsg #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) 718*1099013bSjsg #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF 719*1099013bSjsg #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) 720*1099013bSjsg #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) 721*1099013bSjsg #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF 722*1099013bSjsg #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) 723*1099013bSjsg #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) 724*1099013bSjsg #define C_0007C0_CP_BUSY 0x7FFFFFFF 725*1099013bSjsg #define R_000E40_RBBM_STATUS 0x000E40 726*1099013bSjsg #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 727*1099013bSjsg #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 728*1099013bSjsg #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 729*1099013bSjsg #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) 730*1099013bSjsg #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) 731*1099013bSjsg #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF 732*1099013bSjsg #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) 733*1099013bSjsg #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) 734*1099013bSjsg #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF 735*1099013bSjsg #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) 736*1099013bSjsg #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) 737*1099013bSjsg #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF 738*1099013bSjsg #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) 739*1099013bSjsg #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) 740*1099013bSjsg #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF 741*1099013bSjsg #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) 742*1099013bSjsg #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) 743*1099013bSjsg #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF 744*1099013bSjsg #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) 745*1099013bSjsg #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) 746*1099013bSjsg #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF 747*1099013bSjsg #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) 748*1099013bSjsg #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) 749*1099013bSjsg #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF 750*1099013bSjsg #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) 751*1099013bSjsg #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) 752*1099013bSjsg #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF 753*1099013bSjsg #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) 754*1099013bSjsg #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) 755*1099013bSjsg #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF 756*1099013bSjsg #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) 757*1099013bSjsg #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) 758*1099013bSjsg #define C_000E40_E2_BUSY 0xFFFDFFFF 759*1099013bSjsg #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) 760*1099013bSjsg #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) 761*1099013bSjsg #define C_000E40_RB2D_BUSY 0xFFFBFFFF 762*1099013bSjsg #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) 763*1099013bSjsg #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) 764*1099013bSjsg #define C_000E40_RB3D_BUSY 0xFFF7FFFF 765*1099013bSjsg #define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20) 766*1099013bSjsg #define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1) 767*1099013bSjsg #define C_000E40_SE_BUSY 0xFFEFFFFF 768*1099013bSjsg #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) 769*1099013bSjsg #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) 770*1099013bSjsg #define C_000E40_RE_BUSY 0xFFDFFFFF 771*1099013bSjsg #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) 772*1099013bSjsg #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) 773*1099013bSjsg #define C_000E40_TAM_BUSY 0xFFBFFFFF 774*1099013bSjsg #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) 775*1099013bSjsg #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) 776*1099013bSjsg #define C_000E40_TDM_BUSY 0xFF7FFFFF 777*1099013bSjsg #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) 778*1099013bSjsg #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) 779*1099013bSjsg #define C_000E40_PB_BUSY 0xFEFFFFFF 780*1099013bSjsg #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) 781*1099013bSjsg #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 782*1099013bSjsg #define C_000E40_GUI_ACTIVE 0x7FFFFFFF 783*1099013bSjsg 784*1099013bSjsg 785*1099013bSjsg #define R_00000D_SCLK_CNTL 0x00000D 786*1099013bSjsg #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) 787*1099013bSjsg #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) 788*1099013bSjsg #define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8 789*1099013bSjsg #define S_00000D_TCLK_SRC_SEL(x) (((x) & 0x7) << 8) 790*1099013bSjsg #define G_00000D_TCLK_SRC_SEL(x) (((x) >> 8) & 0x7) 791*1099013bSjsg #define C_00000D_TCLK_SRC_SEL 0xFFFFF8FF 792*1099013bSjsg #define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16) 793*1099013bSjsg #define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1) 794*1099013bSjsg #define C_00000D_FORCE_CP 0xFFFEFFFF 795*1099013bSjsg #define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17) 796*1099013bSjsg #define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1) 797*1099013bSjsg #define C_00000D_FORCE_HDP 0xFFFDFFFF 798*1099013bSjsg #define S_00000D_FORCE_DISP(x) (((x) & 0x1) << 18) 799*1099013bSjsg #define G_00000D_FORCE_DISP(x) (((x) >> 18) & 0x1) 800*1099013bSjsg #define C_00000D_FORCE_DISP 0xFFFBFFFF 801*1099013bSjsg #define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19) 802*1099013bSjsg #define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1) 803*1099013bSjsg #define C_00000D_FORCE_TOP 0xFFF7FFFF 804*1099013bSjsg #define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) 805*1099013bSjsg #define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) 806*1099013bSjsg #define C_00000D_FORCE_E2 0xFFEFFFFF 807*1099013bSjsg #define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) 808*1099013bSjsg #define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) 809*1099013bSjsg #define C_00000D_FORCE_SE 0xFFDFFFFF 810*1099013bSjsg #define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) 811*1099013bSjsg #define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) 812*1099013bSjsg #define C_00000D_FORCE_IDCT 0xFFBFFFFF 813*1099013bSjsg #define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23) 814*1099013bSjsg #define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1) 815*1099013bSjsg #define C_00000D_FORCE_VIP 0xFF7FFFFF 816*1099013bSjsg #define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) 817*1099013bSjsg #define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) 818*1099013bSjsg #define C_00000D_FORCE_RE 0xFEFFFFFF 819*1099013bSjsg #define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) 820*1099013bSjsg #define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) 821*1099013bSjsg #define C_00000D_FORCE_PB 0xFDFFFFFF 822*1099013bSjsg #define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26) 823*1099013bSjsg #define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1) 824*1099013bSjsg #define C_00000D_FORCE_TAM 0xFBFFFFFF 825*1099013bSjsg #define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27) 826*1099013bSjsg #define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1) 827*1099013bSjsg #define C_00000D_FORCE_TDM 0xF7FFFFFF 828*1099013bSjsg #define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) 829*1099013bSjsg #define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) 830*1099013bSjsg #define C_00000D_FORCE_RB 0xEFFFFFFF 831*1099013bSjsg 832*1099013bSjsg /* PLL regs */ 833*1099013bSjsg #define SCLK_CNTL 0xd 834*1099013bSjsg #define FORCE_HDP (1 << 17) 835*1099013bSjsg #define CLK_PWRMGT_CNTL 0x14 836*1099013bSjsg #define GLOBAL_PMAN_EN (1 << 10) 837*1099013bSjsg #define DISP_PM (1 << 20) 838*1099013bSjsg #define PLL_PWRMGT_CNTL 0x15 839*1099013bSjsg #define MPLL_TURNOFF (1 << 0) 840*1099013bSjsg #define SPLL_TURNOFF (1 << 1) 841*1099013bSjsg #define PPLL_TURNOFF (1 << 2) 842*1099013bSjsg #define P2PLL_TURNOFF (1 << 3) 843*1099013bSjsg #define TVPLL_TURNOFF (1 << 4) 844*1099013bSjsg #define MOBILE_SU (1 << 16) 845*1099013bSjsg #define SU_SCLK_USE_BCLK (1 << 17) 846*1099013bSjsg #define SCLK_CNTL2 0x1e 847*1099013bSjsg #define REDUCED_SPEED_SCLK_MODE (1 << 16) 848*1099013bSjsg #define REDUCED_SPEED_SCLK_SEL(x) ((x) << 17) 849*1099013bSjsg #define MCLK_MISC 0x1f 850*1099013bSjsg #define EN_MCLK_TRISTATE_IN_SUSPEND (1 << 18) 851*1099013bSjsg #define SCLK_MORE_CNTL 0x35 852*1099013bSjsg #define REDUCED_SPEED_SCLK_EN (1 << 16) 853*1099013bSjsg #define IO_CG_VOLTAGE_DROP (1 << 17) 854*1099013bSjsg #define VOLTAGE_DELAY_SEL(x) ((x) << 20) 855*1099013bSjsg #define VOLTAGE_DROP_SYNC (1 << 19) 856*1099013bSjsg 857*1099013bSjsg /* mmreg */ 858*1099013bSjsg #define DISP_PWR_MAN 0xd08 859*1099013bSjsg #define DISP_D3_GRPH_RST (1 << 18) 860*1099013bSjsg #define DISP_D3_SUBPIC_RST (1 << 19) 861*1099013bSjsg #define DISP_D3_OV0_RST (1 << 20) 862*1099013bSjsg #define DISP_D1D2_GRPH_RST (1 << 21) 863*1099013bSjsg #define DISP_D1D2_SUBPIC_RST (1 << 22) 864*1099013bSjsg #define DISP_D1D2_OV0_RST (1 << 23) 865*1099013bSjsg #define DISP_DVO_ENABLE_RST (1 << 24) 866*1099013bSjsg #define TV_ENABLE_RST (1 << 25) 867*1099013bSjsg #define AUTO_PWRUP_EN (1 << 26) 868*1099013bSjsg 869*1099013bSjsg #endif 870