1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/acpi.h> 30 #include <linux/pci.h> 31 #include <linux/slab.h> 32 33 #include <drm/drm_device.h> 34 35 #include "atom.h" 36 #include "radeon.h" 37 #include "radeon_reg.h" 38 39 #if defined(__amd64__) || defined(__i386__) 40 #include <dev/isa/isareg.h> 41 #include <dev/isa/isavar.h> 42 #endif 43 44 #if defined (__loongson__) 45 #include <machine/autoconf.h> 46 #endif 47 48 /* 49 * BIOS. 50 */ 51 52 /* If you boot an IGP board with a discrete card as the primary, 53 * the IGP rom is not accessible via the rom bar as the IGP rom is 54 * part of the system bios. On boot, the system bios puts a 55 * copy of the igp rom at the start of vram if a discrete card is 56 * present. 57 */ 58 #ifdef __linux__ 59 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 60 { 61 uint8_t __iomem *bios; 62 resource_size_t vram_base; 63 resource_size_t size = 256 * 1024; /* ??? */ 64 65 if (!(rdev->flags & RADEON_IS_IGP)) 66 if (!radeon_card_posted(rdev)) 67 return false; 68 69 rdev->bios = NULL; 70 vram_base = pci_resource_start(rdev->pdev, 0); 71 bios = ioremap(vram_base, size); 72 if (!bios) { 73 return false; 74 } 75 76 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 77 iounmap(bios); 78 return false; 79 } 80 rdev->bios = kmalloc(size, GFP_KERNEL); 81 if (rdev->bios == NULL) { 82 iounmap(bios); 83 return false; 84 } 85 memcpy_fromio(rdev->bios, bios, size); 86 iounmap(bios); 87 return true; 88 } 89 #else 90 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 91 { 92 bus_size_t size = 256 * 1024; /* ??? */ 93 bus_space_handle_t bsh; 94 bus_space_tag_t bst = rdev->memt; 95 96 if (!(rdev->flags & RADEON_IS_IGP)) 97 if (!radeon_card_posted(rdev)) 98 return false; 99 100 rdev->bios = NULL; 101 102 if (bus_space_map(bst, rdev->fb_aper_offset, size, 0, &bsh) != 0) 103 return false; 104 105 rdev->bios = kmalloc(size, GFP_KERNEL); 106 bus_space_read_region_1(rdev->memt, bsh, 0, rdev->bios, size); 107 bus_space_unmap(bst, bsh, size); 108 109 if (size == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 110 kfree(rdev->bios); 111 rdev->bios = NULL; 112 return false; 113 } 114 115 return true; 116 } 117 #endif 118 119 #ifdef __linux__ 120 static bool radeon_read_bios(struct radeon_device *rdev) 121 { 122 uint8_t __iomem *bios, val1, val2; 123 size_t size; 124 125 rdev->bios = NULL; 126 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 127 bios = pci_map_rom(rdev->pdev, &size); 128 if (!bios) { 129 return false; 130 } 131 132 val1 = readb(&bios[0]); 133 val2 = readb(&bios[1]); 134 135 if (size == 0 || val1 != 0x55 || val2 != 0xaa) { 136 pci_unmap_rom(rdev->pdev, bios); 137 return false; 138 } 139 rdev->bios = kzalloc(size, GFP_KERNEL); 140 if (rdev->bios == NULL) { 141 pci_unmap_rom(rdev->pdev, bios); 142 return false; 143 } 144 memcpy_fromio(rdev->bios, bios, size); 145 pci_unmap_rom(rdev->pdev, bios); 146 return true; 147 } 148 #else 149 static bool radeon_read_bios(struct radeon_device *rdev) 150 { 151 bus_size_t size; 152 pcireg_t address, mask; 153 bus_space_handle_t romh; 154 int rc; 155 156 rdev->bios = NULL; 157 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 158 159 address = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG); 160 pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); 161 mask = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG); 162 address |= PCI_ROM_ENABLE; 163 pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, address); 164 165 size = PCI_ROM_SIZE(mask); 166 if (size == 0) 167 return false; 168 rc = bus_space_map(rdev->memt, PCI_ROM_ADDR(address), size, 0, &romh); 169 if (rc != 0) { 170 printf(": can't map PCI ROM (%d)\n", rc); 171 return false; 172 } 173 174 rdev->bios = kmalloc(size, GFP_KERNEL); 175 bus_space_read_region_1(rdev->memt, romh, 0, rdev->bios, size); 176 bus_space_unmap(rdev->memt, romh, size); 177 178 if (size == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 179 kfree(rdev->bios); 180 rdev->bios = NULL; 181 return false; 182 } 183 return true; 184 } 185 186 #endif 187 188 #ifdef __linux__ 189 static bool radeon_read_platform_bios(struct radeon_device *rdev) 190 { 191 phys_addr_t rom = rdev->pdev->rom; 192 size_t romlen = rdev->pdev->romlen; 193 void __iomem *bios; 194 195 rdev->bios = NULL; 196 197 if (!rom || romlen == 0) 198 return false; 199 200 rdev->bios = kzalloc(romlen, GFP_KERNEL); 201 if (!rdev->bios) 202 return false; 203 204 bios = ioremap(rom, romlen); 205 if (!bios) 206 goto free_bios; 207 208 memcpy_fromio(rdev->bios, bios, romlen); 209 iounmap(bios); 210 211 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) 212 goto free_bios; 213 214 return true; 215 free_bios: 216 kfree(rdev->bios); 217 return false; 218 } 219 #else 220 static bool radeon_read_platform_bios(struct radeon_device *rdev) 221 { 222 #if defined(__amd64__) || defined(__i386__) || defined(__loongson__) 223 uint8_t __iomem *bios; 224 bus_size_t size = 256 * 1024; /* ??? */ 225 uint8_t *found = NULL; 226 int i; 227 228 if (!(rdev->flags & RADEON_IS_IGP)) 229 if (!radeon_card_posted(rdev)) 230 return false; 231 232 rdev->bios = NULL; 233 234 #if defined(__loongson__) 235 if (loongson_videobios == NULL) 236 return false; 237 bios = loongson_videobios; 238 #else 239 bios = (u8 *)ISA_HOLE_VADDR(0xc0000); 240 #endif 241 242 for (i = 0; i + 2 < size; i++) { 243 if (bios[i] == 0x55 && bios[i + 1] == 0xaa) { 244 found = bios + i; 245 break; 246 } 247 248 } 249 if (found == NULL) { 250 DRM_ERROR("bios size zero or checksum mismatch\n"); 251 return false; 252 } 253 254 rdev->bios = kmalloc(size, GFP_KERNEL); 255 if (rdev->bios == NULL) 256 return false; 257 258 memcpy(rdev->bios, found, size); 259 260 return true; 261 #endif 262 return false; 263 } 264 #endif 265 266 #ifdef CONFIG_ACPI 267 /* ATRM is used to get the BIOS on the discrete cards in 268 * dual-gpu systems. 269 */ 270 /* retrieve the ROM in 4k blocks */ 271 #define ATRM_BIOS_PAGE 4096 272 /** 273 * radeon_atrm_call - fetch a chunk of the vbios 274 * 275 * @atrm_handle: acpi ATRM handle 276 * @bios: vbios image pointer 277 * @offset: offset of vbios image data to fetch 278 * @len: length of vbios image data to fetch 279 * 280 * Executes ATRM to fetch a chunk of the discrete 281 * vbios image on PX systems (all asics). 282 * Returns the length of the buffer fetched. 283 */ 284 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 285 int offset, int len) 286 { 287 acpi_status status; 288 union acpi_object atrm_arg_elements[2], *obj; 289 struct acpi_object_list atrm_arg; 290 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 291 292 atrm_arg.count = 2; 293 atrm_arg.pointer = &atrm_arg_elements[0]; 294 295 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 296 atrm_arg_elements[0].integer.value = offset; 297 298 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 299 atrm_arg_elements[1].integer.value = len; 300 301 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 302 if (ACPI_FAILURE(status)) { 303 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 304 return -ENODEV; 305 } 306 307 obj = (union acpi_object *)buffer.pointer; 308 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 309 len = obj->buffer.length; 310 kfree(buffer.pointer); 311 return len; 312 } 313 314 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 315 { 316 int ret; 317 int size = 256 * 1024; 318 int i; 319 struct pci_dev *pdev = NULL; 320 acpi_handle dhandle, atrm_handle; 321 acpi_status status; 322 bool found = false; 323 324 /* ATRM is for the discrete card only */ 325 if (rdev->flags & RADEON_IS_IGP) 326 return false; 327 328 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 329 dhandle = ACPI_HANDLE(&pdev->dev); 330 if (!dhandle) 331 continue; 332 333 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 334 if (!ACPI_FAILURE(status)) { 335 found = true; 336 break; 337 } 338 } 339 340 if (!found) { 341 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 342 dhandle = ACPI_HANDLE(&pdev->dev); 343 if (!dhandle) 344 continue; 345 346 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 347 if (!ACPI_FAILURE(status)) { 348 found = true; 349 break; 350 } 351 } 352 } 353 354 if (!found) 355 return false; 356 357 rdev->bios = kmalloc(size, GFP_KERNEL); 358 if (!rdev->bios) { 359 DRM_ERROR("Unable to allocate bios\n"); 360 return false; 361 } 362 363 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 364 ret = radeon_atrm_call(atrm_handle, 365 rdev->bios, 366 (i * ATRM_BIOS_PAGE), 367 ATRM_BIOS_PAGE); 368 if (ret < ATRM_BIOS_PAGE) 369 break; 370 } 371 372 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 373 kfree(rdev->bios); 374 return false; 375 } 376 return true; 377 } 378 #else 379 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 380 { 381 return false; 382 } 383 #endif 384 385 static bool ni_read_disabled_bios(struct radeon_device *rdev) 386 { 387 u32 bus_cntl; 388 u32 d1vga_control; 389 u32 d2vga_control; 390 u32 vga_render_control; 391 u32 rom_cntl; 392 bool r; 393 394 bus_cntl = RREG32(R600_BUS_CNTL); 395 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 396 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 397 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 398 rom_cntl = RREG32(R600_ROM_CNTL); 399 400 /* enable the rom */ 401 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 402 if (!ASIC_IS_NODCE(rdev)) { 403 /* Disable VGA mode */ 404 WREG32(AVIVO_D1VGA_CONTROL, 405 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 406 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 407 WREG32(AVIVO_D2VGA_CONTROL, 408 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 409 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 410 WREG32(AVIVO_VGA_RENDER_CONTROL, 411 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 412 } 413 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 414 415 r = radeon_read_bios(rdev); 416 417 /* restore regs */ 418 WREG32(R600_BUS_CNTL, bus_cntl); 419 if (!ASIC_IS_NODCE(rdev)) { 420 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 421 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 422 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 423 } 424 WREG32(R600_ROM_CNTL, rom_cntl); 425 return r; 426 } 427 428 static bool r700_read_disabled_bios(struct radeon_device *rdev) 429 { 430 uint32_t viph_control; 431 uint32_t bus_cntl; 432 uint32_t d1vga_control; 433 uint32_t d2vga_control; 434 uint32_t vga_render_control; 435 uint32_t rom_cntl; 436 uint32_t cg_spll_func_cntl = 0; 437 uint32_t cg_spll_status; 438 bool r; 439 440 viph_control = RREG32(RADEON_VIPH_CONTROL); 441 bus_cntl = RREG32(R600_BUS_CNTL); 442 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 443 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 444 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 445 rom_cntl = RREG32(R600_ROM_CNTL); 446 447 /* disable VIP */ 448 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 449 /* enable the rom */ 450 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 451 /* Disable VGA mode */ 452 WREG32(AVIVO_D1VGA_CONTROL, 453 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 454 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 455 WREG32(AVIVO_D2VGA_CONTROL, 456 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 457 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 458 WREG32(AVIVO_VGA_RENDER_CONTROL, 459 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 460 461 if (rdev->family == CHIP_RV730) { 462 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 463 464 /* enable bypass mode */ 465 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 466 R600_SPLL_BYPASS_EN)); 467 468 /* wait for SPLL_CHG_STATUS to change to 1 */ 469 cg_spll_status = 0; 470 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 471 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 472 473 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 474 } else 475 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 476 477 r = radeon_read_bios(rdev); 478 479 /* restore regs */ 480 if (rdev->family == CHIP_RV730) { 481 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 482 483 /* wait for SPLL_CHG_STATUS to change to 1 */ 484 cg_spll_status = 0; 485 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 486 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 487 } 488 WREG32(RADEON_VIPH_CONTROL, viph_control); 489 WREG32(R600_BUS_CNTL, bus_cntl); 490 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 491 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 492 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 493 WREG32(R600_ROM_CNTL, rom_cntl); 494 return r; 495 } 496 497 static bool r600_read_disabled_bios(struct radeon_device *rdev) 498 { 499 uint32_t viph_control; 500 uint32_t bus_cntl; 501 uint32_t d1vga_control; 502 uint32_t d2vga_control; 503 uint32_t vga_render_control; 504 uint32_t rom_cntl; 505 uint32_t general_pwrmgt; 506 uint32_t low_vid_lower_gpio_cntl; 507 uint32_t medium_vid_lower_gpio_cntl; 508 uint32_t high_vid_lower_gpio_cntl; 509 uint32_t ctxsw_vid_lower_gpio_cntl; 510 uint32_t lower_gpio_enable; 511 bool r; 512 513 /* 514 * Some machines with RV610 running amd64 pass initial checks but later 515 * fail atombios specific checks. Return early here so the bios will be 516 * read from 0xc0000 in radeon_read_platform_bios() instead. 517 * RV610 0x1002:0x94C3 0x1028:0x0402 0x00 518 * RV610 0x1002:0x94C1 0x1028:0x0D02 0x00 519 */ 520 if (rdev->family == CHIP_RV610) 521 return false; 522 523 viph_control = RREG32(RADEON_VIPH_CONTROL); 524 bus_cntl = RREG32(R600_BUS_CNTL); 525 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 526 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 527 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 528 rom_cntl = RREG32(R600_ROM_CNTL); 529 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 530 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 531 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 532 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 533 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 534 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 535 536 /* disable VIP */ 537 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 538 /* enable the rom */ 539 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 540 /* Disable VGA mode */ 541 WREG32(AVIVO_D1VGA_CONTROL, 542 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 543 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 544 WREG32(AVIVO_D2VGA_CONTROL, 545 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 546 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 547 WREG32(AVIVO_VGA_RENDER_CONTROL, 548 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 549 550 WREG32(R600_ROM_CNTL, 551 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 552 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 553 R600_SCK_OVERWRITE)); 554 555 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 556 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 557 (low_vid_lower_gpio_cntl & ~0x400)); 558 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 559 (medium_vid_lower_gpio_cntl & ~0x400)); 560 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 561 (high_vid_lower_gpio_cntl & ~0x400)); 562 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 563 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 564 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 565 566 r = radeon_read_bios(rdev); 567 568 /* restore regs */ 569 WREG32(RADEON_VIPH_CONTROL, viph_control); 570 WREG32(R600_BUS_CNTL, bus_cntl); 571 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 572 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 573 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 574 WREG32(R600_ROM_CNTL, rom_cntl); 575 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 576 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 577 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 578 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 579 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 580 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 581 return r; 582 } 583 584 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 585 { 586 uint32_t seprom_cntl1; 587 uint32_t viph_control; 588 uint32_t bus_cntl; 589 uint32_t d1vga_control; 590 uint32_t d2vga_control; 591 uint32_t vga_render_control; 592 uint32_t gpiopad_a; 593 uint32_t gpiopad_en; 594 uint32_t gpiopad_mask; 595 bool r; 596 597 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 598 viph_control = RREG32(RADEON_VIPH_CONTROL); 599 bus_cntl = RREG32(RV370_BUS_CNTL); 600 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 601 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 602 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 603 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 604 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 605 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 606 607 WREG32(RADEON_SEPROM_CNTL1, 608 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 609 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 610 WREG32(RADEON_GPIOPAD_A, 0); 611 WREG32(RADEON_GPIOPAD_EN, 0); 612 WREG32(RADEON_GPIOPAD_MASK, 0); 613 614 /* disable VIP */ 615 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 616 617 /* enable the rom */ 618 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 619 620 /* Disable VGA mode */ 621 WREG32(AVIVO_D1VGA_CONTROL, 622 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 623 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 624 WREG32(AVIVO_D2VGA_CONTROL, 625 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 626 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 627 WREG32(AVIVO_VGA_RENDER_CONTROL, 628 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 629 630 r = radeon_read_bios(rdev); 631 632 /* restore regs */ 633 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 634 WREG32(RADEON_VIPH_CONTROL, viph_control); 635 WREG32(RV370_BUS_CNTL, bus_cntl); 636 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 637 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 638 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 639 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 640 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 641 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 642 return r; 643 } 644 645 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 646 { 647 uint32_t seprom_cntl1; 648 uint32_t viph_control; 649 uint32_t bus_cntl; 650 uint32_t crtc_gen_cntl; 651 uint32_t crtc2_gen_cntl; 652 uint32_t crtc_ext_cntl; 653 uint32_t fp2_gen_cntl; 654 bool r; 655 656 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 657 viph_control = RREG32(RADEON_VIPH_CONTROL); 658 if (rdev->flags & RADEON_IS_PCIE) 659 bus_cntl = RREG32(RV370_BUS_CNTL); 660 else 661 bus_cntl = RREG32(RADEON_BUS_CNTL); 662 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 663 crtc2_gen_cntl = 0; 664 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 665 fp2_gen_cntl = 0; 666 667 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 668 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 669 } 670 671 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 672 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 673 } 674 675 WREG32(RADEON_SEPROM_CNTL1, 676 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 677 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 678 679 /* disable VIP */ 680 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 681 682 /* enable the rom */ 683 if (rdev->flags & RADEON_IS_PCIE) 684 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 685 else 686 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 687 688 /* Turn off mem requests and CRTC for both controllers */ 689 WREG32(RADEON_CRTC_GEN_CNTL, 690 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 691 (RADEON_CRTC_DISP_REQ_EN_B | 692 RADEON_CRTC_EXT_DISP_EN))); 693 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 694 WREG32(RADEON_CRTC2_GEN_CNTL, 695 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 696 RADEON_CRTC2_DISP_REQ_EN_B)); 697 } 698 /* Turn off CRTC */ 699 WREG32(RADEON_CRTC_EXT_CNTL, 700 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 701 (RADEON_CRTC_SYNC_TRISTAT | 702 RADEON_CRTC_DISPLAY_DIS))); 703 704 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 705 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 706 } 707 708 r = radeon_read_bios(rdev); 709 710 /* restore regs */ 711 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 712 WREG32(RADEON_VIPH_CONTROL, viph_control); 713 if (rdev->flags & RADEON_IS_PCIE) 714 WREG32(RV370_BUS_CNTL, bus_cntl); 715 else 716 WREG32(RADEON_BUS_CNTL, bus_cntl); 717 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 718 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 719 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 720 } 721 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 722 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 723 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 724 } 725 return r; 726 } 727 728 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 729 { 730 if (rdev->flags & RADEON_IS_IGP) 731 return igp_read_bios_from_vram(rdev); 732 else if (rdev->family >= CHIP_BARTS) 733 return ni_read_disabled_bios(rdev); 734 else if (rdev->family >= CHIP_RV770) 735 return r700_read_disabled_bios(rdev); 736 else if (rdev->family >= CHIP_R600) 737 return r600_read_disabled_bios(rdev); 738 else if (rdev->family >= CHIP_RS600) 739 return avivo_read_disabled_bios(rdev); 740 else 741 return legacy_read_disabled_bios(rdev); 742 } 743 744 #ifdef CONFIG_ACPI 745 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 746 { 747 struct acpi_table_header *hdr; 748 acpi_size tbl_size; 749 UEFI_ACPI_VFCT *vfct; 750 unsigned offset; 751 752 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr))) 753 return false; 754 tbl_size = hdr->length; 755 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 756 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 757 return false; 758 } 759 760 vfct = (UEFI_ACPI_VFCT *)hdr; 761 offset = vfct->VBIOSImageOffset; 762 763 while (offset < tbl_size) { 764 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset); 765 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader; 766 767 offset += sizeof(VFCT_IMAGE_HEADER); 768 if (offset > tbl_size) { 769 DRM_ERROR("ACPI VFCT image header truncated\n"); 770 return false; 771 } 772 773 offset += vhdr->ImageLength; 774 if (offset > tbl_size) { 775 DRM_ERROR("ACPI VFCT image truncated\n"); 776 return false; 777 } 778 779 if (vhdr->ImageLength && 780 vhdr->PCIBus == rdev->pdev->bus->number && 781 vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) && 782 vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) && 783 vhdr->VendorID == rdev->pdev->vendor && 784 vhdr->DeviceID == rdev->pdev->device) { 785 rdev->bios = kmemdup(&vbios->VbiosContent, 786 vhdr->ImageLength, 787 GFP_KERNEL); 788 789 if (!rdev->bios) 790 return false; 791 return true; 792 } 793 } 794 795 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 796 return false; 797 } 798 #else 799 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 800 { 801 return false; 802 } 803 #endif 804 805 bool radeon_get_bios(struct radeon_device *rdev) 806 { 807 bool r; 808 uint16_t tmp; 809 810 r = radeon_atrm_get_bios(rdev); 811 if (!r) 812 r = radeon_acpi_vfct_bios(rdev); 813 if (!r) 814 r = igp_read_bios_from_vram(rdev); 815 if (!r) 816 r = radeon_read_bios(rdev); 817 if (!r) 818 r = radeon_read_disabled_bios(rdev); 819 if (!r) 820 r = radeon_read_platform_bios(rdev); 821 if (!r || rdev->bios == NULL) { 822 DRM_ERROR("Unable to locate a BIOS ROM\n"); 823 rdev->bios = NULL; 824 return false; 825 } 826 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 827 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 828 goto free_bios; 829 } 830 831 tmp = RBIOS16(0x18); 832 if (RBIOS8(tmp + 0x14) != 0x0) { 833 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 834 goto free_bios; 835 } 836 837 rdev->bios_header_start = RBIOS16(0x48); 838 if (!rdev->bios_header_start) { 839 goto free_bios; 840 } 841 tmp = rdev->bios_header_start + 4; 842 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 843 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 844 rdev->is_atom_bios = true; 845 } else { 846 rdev->is_atom_bios = false; 847 } 848 849 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 850 return true; 851 free_bios: 852 kfree(rdev->bios); 853 rdev->bios = NULL; 854 return false; 855 } 856