1 /* 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 33 #include <linux/compat.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pci.h> 39 40 #include <drm/drm_aperture.h> 41 #include <drm/drm_crtc_helper.h> 42 #include <drm/drm_drv.h> 43 #include <drm/drm_fb_helper.h> 44 #include <drm/drm_file.h> 45 #include <drm/drm_gem.h> 46 #include <drm/drm_ioctl.h> 47 #include <drm/drm_pciids.h> 48 #include <drm/drm_probe_helper.h> 49 #include <drm/drm_vblank.h> 50 #include <drm/radeon_drm.h> 51 52 #include "radeon_drv.h" 53 #include "radeon.h" 54 #include "radeon_kms.h" 55 #include "radeon_ttm.h" 56 #include "radeon_device.h" 57 #include "radeon_prime.h" 58 59 /* 60 * KMS wrapper. 61 * - 2.0.0 - initial interface 62 * - 2.1.0 - add square tiling interface 63 * - 2.2.0 - add r6xx/r7xx const buffer support 64 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 65 * - 2.4.0 - add crtc id query 66 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 67 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 68 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 69 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 70 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 71 * 2.10.0 - fusion 2D tiling 72 * 2.11.0 - backend map, initial compute support for the CS checker 73 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 74 * 2.13.0 - virtual memory support, streamout 75 * 2.14.0 - add evergreen tiling informations 76 * 2.15.0 - add max_pipes query 77 * 2.16.0 - fix evergreen 2D tiled surface calculation 78 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 79 * 2.18.0 - r600-eg: allow "invalid" DB formats 80 * 2.19.0 - r600-eg: MSAA textures 81 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 82 * 2.21.0 - r600-r700: FMASK and CMASK 83 * 2.22.0 - r600 only: RESOLVE_BOX allowed 84 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 85 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 86 * 2.25.0 - eg+: new info request for num SE and num SH 87 * 2.26.0 - r600-eg: fix htile size computation 88 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 89 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 90 * 2.29.0 - R500 FP16 color clear registers 91 * 2.30.0 - fix for FMASK texturing 92 * 2.31.0 - Add fastfb support for rs690 93 * 2.32.0 - new info request for rings working 94 * 2.33.0 - Add SI tiling mode array query 95 * 2.34.0 - Add CIK tiling mode array query 96 * 2.35.0 - Add CIK macrotile mode array query 97 * 2.36.0 - Fix CIK DCE tiling setup 98 * 2.37.0 - allow GS ring setup on r6xx/r7xx 99 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 100 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 101 * 2.39.0 - Add INFO query for number of active CUs 102 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 103 * CS to GPU on >= r600 104 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 105 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 106 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 107 * 2.44.0 - SET_APPEND_CNT packet3 support 108 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 109 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 110 * 2.47.0 - Add UVD_NO_OP register support 111 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 112 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 113 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 114 */ 115 #define KMS_DRIVER_MAJOR 2 116 #define KMS_DRIVER_MINOR 50 117 #define KMS_DRIVER_PATCHLEVEL 0 118 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 119 bool fbcon, bool freeze); 120 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 121 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 122 unsigned int flags, int *vpos, int *hpos, 123 ktime_t *stime, ktime_t *etime, 124 const struct drm_display_mode *mode); 125 extern bool radeon_is_px(struct drm_device *dev); 126 int radeon_mode_dumb_mmap(struct drm_file *filp, 127 struct drm_device *dev, 128 uint32_t handle, uint64_t *offset_p); 129 int radeon_mode_dumb_create(struct drm_file *file_priv, 130 struct drm_device *dev, 131 struct drm_mode_create_dumb *args); 132 133 /* atpx handler */ 134 #if defined(CONFIG_VGA_SWITCHEROO) 135 void radeon_register_atpx_handler(void); 136 void radeon_unregister_atpx_handler(void); 137 bool radeon_has_atpx_dgpu_power_cntl(void); 138 bool radeon_is_atpx_hybrid(void); 139 #else 140 #ifdef notyet 141 static inline void radeon_register_atpx_handler(void) {} 142 static inline void radeon_unregister_atpx_handler(void) {} 143 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 144 static inline bool radeon_is_atpx_hybrid(void) { return false; } 145 #endif 146 #endif 147 148 int radeon_no_wb; 149 int radeon_modeset = -1; 150 int radeon_dynclks = -1; 151 int radeon_r4xx_atom = 0; 152 int radeon_agpmode = -1; 153 int radeon_vram_limit = 0; 154 int radeon_gart_size = -1; /* auto */ 155 int radeon_benchmarking = 0; 156 int radeon_testing = 0; 157 int radeon_connector_table = 0; 158 int radeon_tv = 1; 159 int radeon_audio = -1; 160 int radeon_disp_priority = 0; 161 int radeon_hw_i2c = 0; 162 int radeon_pcie_gen2 = -1; 163 int radeon_msi = -1; 164 int radeon_lockup_timeout = 10000; 165 int radeon_fastfb = 0; 166 int radeon_dpm = -1; 167 int radeon_aspm = -1; 168 int radeon_runtime_pm = -1; 169 int radeon_hard_reset = 0; 170 int radeon_vm_size = 8; 171 int radeon_vm_block_size = -1; 172 int radeon_deep_color = 0; 173 int radeon_use_pflipirq = 2; 174 int radeon_bapm = -1; 175 int radeon_backlight = -1; 176 int radeon_auxch = -1; 177 int radeon_uvd = 1; 178 int radeon_vce = 1; 179 180 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 181 module_param_named(no_wb, radeon_no_wb, int, 0444); 182 183 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 184 module_param_named(modeset, radeon_modeset, int, 0400); 185 186 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 187 module_param_named(dynclks, radeon_dynclks, int, 0444); 188 189 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 190 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 191 192 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 193 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 194 195 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 196 module_param_named(agpmode, radeon_agpmode, int, 0444); 197 198 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 199 module_param_named(gartsize, radeon_gart_size, int, 0600); 200 201 MODULE_PARM_DESC(benchmark, "Run benchmark"); 202 module_param_named(benchmark, radeon_benchmarking, int, 0444); 203 204 MODULE_PARM_DESC(test, "Run tests"); 205 module_param_named(test, radeon_testing, int, 0444); 206 207 MODULE_PARM_DESC(connector_table, "Force connector table"); 208 module_param_named(connector_table, radeon_connector_table, int, 0444); 209 210 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 211 module_param_named(tv, radeon_tv, int, 0444); 212 213 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 214 module_param_named(audio, radeon_audio, int, 0444); 215 216 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 217 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 218 219 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 220 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 221 222 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 223 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 224 225 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 226 module_param_named(msi, radeon_msi, int, 0444); 227 228 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 229 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 230 231 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 232 module_param_named(fastfb, radeon_fastfb, int, 0444); 233 234 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 235 module_param_named(dpm, radeon_dpm, int, 0444); 236 237 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 238 module_param_named(aspm, radeon_aspm, int, 0444); 239 240 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 241 module_param_named(runpm, radeon_runtime_pm, int, 0444); 242 243 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 244 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 245 246 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 247 module_param_named(vm_size, radeon_vm_size, int, 0444); 248 249 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 250 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 251 252 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 253 module_param_named(deep_color, radeon_deep_color, int, 0444); 254 255 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 256 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 257 258 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 259 module_param_named(bapm, radeon_bapm, int, 0444); 260 261 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 262 module_param_named(backlight, radeon_backlight, int, 0444); 263 264 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 265 module_param_named(auxch, radeon_auxch, int, 0444); 266 267 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 268 module_param_named(uvd, radeon_uvd, int, 0444); 269 270 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 271 module_param_named(vce, radeon_vce, int, 0444); 272 273 int radeon_si_support = 1; 274 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 275 module_param_named(si_support, radeon_si_support, int, 0444); 276 277 int radeon_cik_support = 1; 278 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 279 module_param_named(cik_support, radeon_cik_support, int, 0444); 280 281 static const struct pci_device_id pciidlist[] = { 282 radeon_PCI_IDS 283 }; 284 285 MODULE_DEVICE_TABLE(pci, pciidlist); 286 287 static const struct drm_driver kms_driver; 288 289 #ifdef __linux__ 290 static int radeon_pci_probe(struct pci_dev *pdev, 291 const struct pci_device_id *ent) 292 { 293 unsigned long flags = 0; 294 struct drm_device *dev; 295 int ret; 296 297 if (!ent) 298 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */ 299 300 flags = ent->driver_data; 301 302 if (!radeon_si_support) { 303 switch (flags & RADEON_FAMILY_MASK) { 304 case CHIP_TAHITI: 305 case CHIP_PITCAIRN: 306 case CHIP_VERDE: 307 case CHIP_OLAND: 308 case CHIP_HAINAN: 309 dev_info(&pdev->dev, 310 "SI support disabled by module param\n"); 311 return -ENODEV; 312 } 313 } 314 if (!radeon_cik_support) { 315 switch (flags & RADEON_FAMILY_MASK) { 316 case CHIP_KAVERI: 317 case CHIP_BONAIRE: 318 case CHIP_HAWAII: 319 case CHIP_KABINI: 320 case CHIP_MULLINS: 321 dev_info(&pdev->dev, 322 "CIK support disabled by module param\n"); 323 return -ENODEV; 324 } 325 } 326 327 if (vga_switcheroo_client_probe_defer(pdev)) 328 return -EPROBE_DEFER; 329 330 /* Get rid of things like offb */ 331 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &kms_driver); 332 if (ret) 333 return ret; 334 335 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 336 if (IS_ERR(dev)) 337 return PTR_ERR(dev); 338 339 ret = pci_enable_device(pdev); 340 if (ret) 341 goto err_free; 342 343 pci_set_drvdata(pdev, dev); 344 345 ret = drm_dev_register(dev, ent->driver_data); 346 if (ret) 347 goto err_agp; 348 349 return 0; 350 351 err_agp: 352 pci_disable_device(pdev); 353 err_free: 354 drm_dev_put(dev); 355 return ret; 356 } 357 358 static void 359 radeon_pci_remove(struct pci_dev *pdev) 360 { 361 struct drm_device *dev = pci_get_drvdata(pdev); 362 363 drm_put_dev(dev); 364 } 365 366 static void 367 radeon_pci_shutdown(struct pci_dev *pdev) 368 { 369 /* if we are running in a VM, make sure the device 370 * torn down properly on reboot/shutdown 371 */ 372 if (radeon_device_is_virtual()) 373 radeon_pci_remove(pdev); 374 375 #if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64) 376 /* 377 * Some adapters need to be suspended before a 378 * shutdown occurs in order to prevent an error 379 * during kexec, shutdown or reboot. 380 * Make this power and Loongson specific because 381 * it breaks some other boards. 382 */ 383 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false); 384 #endif 385 } 386 387 static int radeon_pmops_suspend(struct device *dev) 388 { 389 struct drm_device *drm_dev = dev_get_drvdata(dev); 390 return radeon_suspend_kms(drm_dev, true, true, false); 391 } 392 393 static int radeon_pmops_resume(struct device *dev) 394 { 395 struct drm_device *drm_dev = dev_get_drvdata(dev); 396 397 /* GPU comes up enabled by the bios on resume */ 398 if (radeon_is_px(drm_dev)) { 399 pm_runtime_disable(dev); 400 pm_runtime_set_active(dev); 401 pm_runtime_enable(dev); 402 } 403 404 return radeon_resume_kms(drm_dev, true, true); 405 } 406 407 static int radeon_pmops_freeze(struct device *dev) 408 { 409 struct drm_device *drm_dev = dev_get_drvdata(dev); 410 return radeon_suspend_kms(drm_dev, false, true, true); 411 } 412 413 static int radeon_pmops_thaw(struct device *dev) 414 { 415 struct drm_device *drm_dev = dev_get_drvdata(dev); 416 return radeon_resume_kms(drm_dev, false, true); 417 } 418 419 static int radeon_pmops_runtime_suspend(struct device *dev) 420 { 421 struct pci_dev *pdev = to_pci_dev(dev); 422 struct drm_device *drm_dev = pci_get_drvdata(pdev); 423 424 if (!radeon_is_px(drm_dev)) { 425 pm_runtime_forbid(dev); 426 return -EBUSY; 427 } 428 429 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 430 drm_kms_helper_poll_disable(drm_dev); 431 432 radeon_suspend_kms(drm_dev, false, false, false); 433 pci_save_state(pdev); 434 pci_disable_device(pdev); 435 pci_ignore_hotplug(pdev); 436 if (radeon_is_atpx_hybrid()) 437 pci_set_power_state(pdev, PCI_D3cold); 438 else if (!radeon_has_atpx_dgpu_power_cntl()) 439 pci_set_power_state(pdev, PCI_D3hot); 440 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 441 442 return 0; 443 } 444 445 static int radeon_pmops_runtime_resume(struct device *dev) 446 { 447 struct pci_dev *pdev = to_pci_dev(dev); 448 struct drm_device *drm_dev = pci_get_drvdata(pdev); 449 int ret; 450 451 if (!radeon_is_px(drm_dev)) 452 return -EINVAL; 453 454 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 455 456 if (radeon_is_atpx_hybrid() || 457 !radeon_has_atpx_dgpu_power_cntl()) 458 pci_set_power_state(pdev, PCI_D0); 459 pci_restore_state(pdev); 460 ret = pci_enable_device(pdev); 461 if (ret) 462 return ret; 463 pci_set_master(pdev); 464 465 ret = radeon_resume_kms(drm_dev, false, false); 466 drm_kms_helper_poll_enable(drm_dev); 467 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 468 return 0; 469 } 470 471 static int radeon_pmops_runtime_idle(struct device *dev) 472 { 473 struct drm_device *drm_dev = dev_get_drvdata(dev); 474 struct drm_crtc *crtc; 475 476 if (!radeon_is_px(drm_dev)) { 477 pm_runtime_forbid(dev); 478 return -EBUSY; 479 } 480 481 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 482 if (crtc->enabled) { 483 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 484 return -EBUSY; 485 } 486 } 487 488 pm_runtime_mark_last_busy(dev); 489 pm_runtime_autosuspend(dev); 490 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 491 return 1; 492 } 493 494 long radeon_drm_ioctl(struct file *filp, 495 unsigned int cmd, unsigned long arg) 496 { 497 struct drm_file *file_priv = filp->private_data; 498 struct drm_device *dev; 499 long ret; 500 dev = file_priv->minor->dev; 501 ret = pm_runtime_get_sync(dev->dev); 502 if (ret < 0) { 503 pm_runtime_put_autosuspend(dev->dev); 504 return ret; 505 } 506 507 ret = drm_ioctl(filp, cmd, arg); 508 509 pm_runtime_mark_last_busy(dev->dev); 510 pm_runtime_put_autosuspend(dev->dev); 511 return ret; 512 } 513 514 #ifdef CONFIG_COMPAT 515 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 516 { 517 unsigned int nr = DRM_IOCTL_NR(cmd); 518 519 if (nr < DRM_COMMAND_BASE) 520 return drm_compat_ioctl(filp, cmd, arg); 521 522 return radeon_drm_ioctl(filp, cmd, arg); 523 } 524 #endif 525 526 static const struct dev_pm_ops radeon_pm_ops = { 527 .suspend = radeon_pmops_suspend, 528 .resume = radeon_pmops_resume, 529 .freeze = radeon_pmops_freeze, 530 .thaw = radeon_pmops_thaw, 531 .poweroff = radeon_pmops_freeze, 532 .restore = radeon_pmops_resume, 533 .runtime_suspend = radeon_pmops_runtime_suspend, 534 .runtime_resume = radeon_pmops_runtime_resume, 535 .runtime_idle = radeon_pmops_runtime_idle, 536 }; 537 538 static const struct file_operations radeon_driver_kms_fops = { 539 .owner = THIS_MODULE, 540 .open = drm_open, 541 .release = drm_release, 542 .unlocked_ioctl = radeon_drm_ioctl, 543 .mmap = drm_gem_mmap, 544 .poll = drm_poll, 545 .read = drm_read, 546 #ifdef CONFIG_COMPAT 547 .compat_ioctl = radeon_kms_compat_ioctl, 548 #endif 549 }; 550 551 #endif /* __linux__ */ 552 553 static const struct drm_ioctl_desc radeon_ioctls_kms[] = { 554 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 555 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 556 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 557 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 558 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), 559 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), 560 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), 561 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), 562 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), 563 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), 564 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), 565 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), 566 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), 567 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), 568 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 569 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), 570 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), 571 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), 572 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), 573 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), 574 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), 575 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 576 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), 577 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), 578 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), 579 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), 580 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), 581 /* KMS */ 582 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 583 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 584 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 585 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 586 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH), 587 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH), 588 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 589 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 590 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 591 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 592 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 593 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 594 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 595 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 596 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 597 }; 598 599 static const struct drm_driver kms_driver = { 600 .driver_features = 601 DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET, 602 #ifdef notyet 603 .load = radeon_driver_load_kms, 604 #endif 605 .open = radeon_driver_open_kms, 606 #ifdef __OpenBSD__ 607 .mmap = drm_gem_mmap, 608 #endif 609 .postclose = radeon_driver_postclose_kms, 610 .lastclose = radeon_driver_lastclose_kms, 611 #ifdef notyet 612 .unload = radeon_driver_unload_kms, 613 #endif 614 .ioctls = radeon_ioctls_kms, 615 .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms), 616 #ifdef __OpenBSD__ 617 .gem_size = sizeof(struct radeon_bo), 618 #endif 619 .dumb_create = radeon_mode_dumb_create, 620 .dumb_map_offset = radeon_mode_dumb_mmap, 621 #ifdef __linux__ 622 .fops = &radeon_driver_kms_fops, 623 #endif 624 625 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 626 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 627 #ifdef notyet 628 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 629 #endif 630 .gem_prime_mmap = drm_gem_prime_mmap, 631 632 .name = DRIVER_NAME, 633 .desc = DRIVER_DESC, 634 .date = DRIVER_DATE, 635 .major = KMS_DRIVER_MAJOR, 636 .minor = KMS_DRIVER_MINOR, 637 .patchlevel = KMS_DRIVER_PATCHLEVEL, 638 }; 639 640 #ifdef __linux__ 641 static struct pci_driver radeon_kms_pci_driver = { 642 .name = DRIVER_NAME, 643 .id_table = pciidlist, 644 .probe = radeon_pci_probe, 645 .remove = radeon_pci_remove, 646 .shutdown = radeon_pci_shutdown, 647 .driver.pm = &radeon_pm_ops, 648 }; 649 #endif 650 651 #ifdef notyet 652 static int __init radeon_module_init(void) 653 { 654 if (drm_firmware_drivers_only() && radeon_modeset == -1) 655 radeon_modeset = 0; 656 657 if (radeon_modeset == 0) 658 return -EINVAL; 659 660 DRM_INFO("radeon kernel modesetting enabled.\n"); 661 radeon_register_atpx_handler(); 662 663 return pci_register_driver(&radeon_kms_pci_driver); 664 } 665 666 static void __exit radeon_module_exit(void) 667 { 668 pci_unregister_driver(&radeon_kms_pci_driver); 669 radeon_unregister_atpx_handler(); 670 mmu_notifier_synchronize(); 671 } 672 #endif /* notyet */ 673 674 module_init(radeon_module_init); 675 module_exit(radeon_module_exit); 676 677 MODULE_AUTHOR(DRIVER_AUTHOR); 678 MODULE_DESCRIPTION(DRIVER_DESC); 679 MODULE_LICENSE("GPL and additional rights"); 680 681 #if defined(CONFIG_VGA_SWITCHEROO) 682 bool radeon_has_atpx(void); 683 #else 684 static inline bool radeon_has_atpx(void) { return false; } 685 #endif 686 687 #include <drm/drm_drv.h> 688 #include "vga.h" 689 690 #if NVGA > 0 691 #include <dev/ic/mc6845reg.h> 692 #include <dev/ic/pcdisplayvar.h> 693 #include <dev/ic/vgareg.h> 694 #include <dev/ic/vgavar.h> 695 696 extern int vga_console_attached; 697 #endif 698 699 #ifdef __amd64__ 700 #include "efifb.h" 701 #include <machine/biosvar.h> 702 #endif 703 704 #if NEFIFB > 0 705 #include <machine/efifbvar.h> 706 #endif 707 708 int radeondrm_probe(struct device *, void *, void *); 709 void radeondrm_attach_kms(struct device *, struct device *, void *); 710 int radeondrm_detach_kms(struct device *, int); 711 int radeondrm_activate_kms(struct device *, int); 712 void radeondrm_attachhook(struct device *); 713 int radeondrm_forcedetach(struct radeon_device *); 714 715 bool radeon_msi_ok(struct radeon_device *); 716 irqreturn_t radeon_driver_irq_handler_kms(void *); 717 718 /* 719 * set if the mountroot hook has a fatal error 720 * such as not being able to find the firmware on newer cards 721 */ 722 int radeon_fatal_error; 723 724 const struct cfattach radeondrm_ca = { 725 sizeof (struct radeon_device), radeondrm_probe, radeondrm_attach_kms, 726 radeondrm_detach_kms, radeondrm_activate_kms 727 }; 728 729 struct cfdriver radeondrm_cd = { 730 NULL, "radeondrm", DV_DULL 731 }; 732 733 int 734 radeondrm_probe(struct device *parent, void *match, void *aux) 735 { 736 if (radeon_fatal_error) 737 return 0; 738 if (drm_pciprobe(aux, pciidlist)) 739 return 20; 740 return 0; 741 } 742 743 int 744 radeondrm_detach_kms(struct device *self, int flags) 745 { 746 struct radeon_device *rdev = (struct radeon_device *)self; 747 748 if (rdev == NULL) 749 return 0; 750 751 pci_intr_disestablish(rdev->pc, rdev->irqh); 752 753 #ifdef notyet 754 pm_runtime_get_sync(dev->dev); 755 756 radeon_kfd_device_fini(rdev); 757 #endif 758 759 radeon_acpi_fini(rdev); 760 761 radeon_modeset_fini(rdev); 762 radeon_device_fini(rdev); 763 764 if (rdev->ddev != NULL) { 765 config_detach(rdev->ddev->dev, flags); 766 rdev->ddev = NULL; 767 } 768 769 return 0; 770 } 771 772 void radeondrm_burner(void *, u_int, u_int); 773 int radeondrm_wsioctl(void *, u_long, caddr_t, int, struct proc *); 774 paddr_t radeondrm_wsmmap(void *, off_t, int); 775 int radeondrm_alloc_screen(void *, const struct wsscreen_descr *, 776 void **, int *, int *, uint32_t *); 777 void radeondrm_free_screen(void *, void *); 778 int radeondrm_show_screen(void *, void *, int, 779 void (*)(void *, int, int), void *); 780 void radeondrm_doswitch(void *); 781 void radeondrm_enter_ddb(void *, void *); 782 #ifdef __sparc64__ 783 void radeondrm_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t); 784 #endif 785 void radeondrm_setpal(struct radeon_device *, struct rasops_info *); 786 787 struct wsscreen_descr radeondrm_stdscreen = { 788 "std", 789 0, 0, 790 0, 791 0, 0, 792 WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 793 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS 794 }; 795 796 const struct wsscreen_descr *radeondrm_scrlist[] = { 797 &radeondrm_stdscreen, 798 }; 799 800 struct wsscreen_list radeondrm_screenlist = { 801 nitems(radeondrm_scrlist), radeondrm_scrlist 802 }; 803 804 struct wsdisplay_accessops radeondrm_accessops = { 805 .ioctl = radeondrm_wsioctl, 806 .mmap = radeondrm_wsmmap, 807 .alloc_screen = radeondrm_alloc_screen, 808 .free_screen = radeondrm_free_screen, 809 .show_screen = radeondrm_show_screen, 810 .enter_ddb = radeondrm_enter_ddb, 811 .getchar = rasops_getchar, 812 .load_font = rasops_load_font, 813 .list_font = rasops_list_font, 814 .scrollback = rasops_scrollback, 815 .burn_screen = radeondrm_burner 816 }; 817 818 int 819 radeondrm_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 820 { 821 struct rasops_info *ri = v; 822 struct wsdisplay_fbinfo *wdf; 823 struct wsdisplay_param *dp = (struct wsdisplay_param *)data; 824 825 switch (cmd) { 826 case WSDISPLAYIO_GTYPE: 827 *(u_int *)data = WSDISPLAY_TYPE_RADEONDRM; 828 return 0; 829 case WSDISPLAYIO_GINFO: 830 wdf = (struct wsdisplay_fbinfo *)data; 831 wdf->width = ri->ri_width; 832 wdf->height = ri->ri_height; 833 wdf->depth = ri->ri_depth; 834 wdf->stride = ri->ri_stride; 835 wdf->offset = 0; 836 wdf->cmsize = 0; 837 return 0; 838 case WSDISPLAYIO_GETPARAM: 839 if (ws_get_param == NULL) 840 return 0; 841 return ws_get_param(dp); 842 case WSDISPLAYIO_SETPARAM: 843 if (ws_set_param == NULL) 844 return 0; 845 return ws_set_param(dp); 846 case WSDISPLAYIO_SVIDEO: 847 case WSDISPLAYIO_GVIDEO: 848 return 0; 849 default: 850 return -1; 851 } 852 } 853 854 paddr_t 855 radeondrm_wsmmap(void *v, off_t off, int prot) 856 { 857 return (-1); 858 } 859 860 int 861 radeondrm_alloc_screen(void *v, const struct wsscreen_descr *type, 862 void **cookiep, int *curxp, int *curyp, uint32_t *attrp) 863 { 864 return rasops_alloc_screen(v, cookiep, curxp, curyp, attrp); 865 } 866 867 void 868 radeondrm_free_screen(void *v, void *cookie) 869 { 870 return rasops_free_screen(v, cookie); 871 } 872 873 int 874 radeondrm_show_screen(void *v, void *cookie, int waitok, 875 void (*cb)(void *, int, int), void *cbarg) 876 { 877 struct rasops_info *ri = v; 878 struct radeon_device *rdev = ri->ri_hw; 879 880 if (cookie == ri->ri_active) 881 return (0); 882 883 rdev->switchcb = cb; 884 rdev->switchcbarg = cbarg; 885 rdev->switchcookie = cookie; 886 if (cb) { 887 task_add(systq, &rdev->switchtask); 888 return (EAGAIN); 889 } 890 891 radeondrm_doswitch(v); 892 893 return (0); 894 } 895 896 void 897 radeondrm_doswitch(void *v) 898 { 899 struct rasops_info *ri = v; 900 struct radeon_device *rdev = ri->ri_hw; 901 902 rasops_show_screen(ri, rdev->switchcookie, 0, NULL, NULL); 903 #ifdef __sparc64__ 904 fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor); 905 #else 906 radeondrm_setpal(rdev, ri); 907 #endif 908 drm_fb_helper_restore_fbdev_mode_unlocked((void *)rdev->mode_info.rfbdev); 909 910 if (rdev->switchcb) 911 (rdev->switchcb)(rdev->switchcbarg, 0, 0); 912 } 913 914 void 915 radeondrm_enter_ddb(void *v, void *cookie) 916 { 917 struct rasops_info *ri = v; 918 struct radeon_device *rdev = ri->ri_hw; 919 struct drm_fb_helper *fb_helper = (void *)rdev->mode_info.rfbdev; 920 921 if (cookie == ri->ri_active) 922 return; 923 924 rasops_show_screen(ri, cookie, 0, NULL, NULL); 925 drm_fb_helper_debug_enter(fb_helper->fbdev); 926 } 927 928 #ifdef __sparc64__ 929 void 930 radeondrm_setcolor(void *v, u_int index, u_int8_t r, u_int8_t g, u_int8_t b) 931 { 932 struct sunfb *sf = v; 933 struct radeon_device *rdev = sf->sf_ro.ri_hw; 934 935 /* see legacy_crtc_load_lut() */ 936 if (rdev->family < CHIP_RS600) { 937 WREG8(RADEON_PALETTE_INDEX, index); 938 WREG32(RADEON_PALETTE_30_DATA, 939 (r << 22) | (g << 12) | (b << 2)); 940 } else { 941 printf("%s: setcolor family %d not handled\n", 942 rdev->self.dv_xname, rdev->family); 943 } 944 } 945 #endif 946 947 void 948 radeondrm_setpal(struct radeon_device *rdev, struct rasops_info *ri) 949 { 950 struct drm_device *dev = rdev->ddev; 951 struct drm_crtc *crtc; 952 uint16_t *r_base, *g_base, *b_base; 953 int i, index, ret = 0; 954 const u_char *p; 955 956 if (ri->ri_depth != 8) 957 return; 958 959 for (i = 0; i < rdev->num_crtc; i++) { 960 struct drm_modeset_acquire_ctx ctx; 961 crtc = &rdev->mode_info.crtcs[i]->base; 962 963 r_base = crtc->gamma_store; 964 g_base = r_base + crtc->gamma_size; 965 b_base = g_base + crtc->gamma_size; 966 967 DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret); 968 969 p = rasops_cmap; 970 for (index = 0; index < 256; index++) { 971 r_base[index] = *p++ << 8; 972 g_base[index] = *p++ << 8; 973 b_base[index] = *p++ << 8; 974 } 975 976 crtc->funcs->gamma_set(crtc, NULL, NULL, NULL, 0, NULL); 977 978 DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); 979 } 980 } 981 982 void 983 radeondrm_attach_kms(struct device *parent, struct device *self, void *aux) 984 { 985 struct radeon_device *rdev = (struct radeon_device *)self; 986 struct drm_device *dev; 987 struct pci_attach_args *pa = aux; 988 const struct pci_device_id *id_entry; 989 int is_agp; 990 pcireg_t type; 991 int i; 992 uint8_t rmmio_bar; 993 paddr_t fb_aper; 994 pcireg_t addr, mask; 995 int s; 996 997 #if defined(__sparc64__) || defined(__macppc__) 998 extern int fbnode; 999 #endif 1000 1001 id_entry = drm_find_description(PCI_VENDOR(pa->pa_id), 1002 PCI_PRODUCT(pa->pa_id), pciidlist); 1003 rdev->flags = id_entry->driver_data; 1004 rdev->family = rdev->flags & RADEON_FAMILY_MASK; 1005 rdev->pc = pa->pa_pc; 1006 rdev->pa_tag = pa->pa_tag; 1007 rdev->iot = pa->pa_iot; 1008 rdev->memt = pa->pa_memt; 1009 rdev->dmat = pa->pa_dmat; 1010 1011 #if defined(__sparc64__) || defined(__macppc__) 1012 if (fbnode == PCITAG_NODE(rdev->pa_tag)) 1013 rdev->console = rdev->primary = 1; 1014 #else 1015 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY && 1016 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA && 1017 (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) 1018 & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 1019 == (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) { 1020 rdev->primary = 1; 1021 #if NVGA > 0 1022 rdev->console = vga_is_console(pa->pa_iot, -1); 1023 vga_console_attached = 1; 1024 #endif 1025 } 1026 1027 #if NEFIFB > 0 1028 if (efifb_is_primary(pa)) { 1029 rdev->primary = 1; 1030 rdev->console = efifb_is_console(pa); 1031 efifb_detach(); 1032 } 1033 #endif 1034 #endif 1035 1036 #define RADEON_PCI_MEM 0x10 1037 1038 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM); 1039 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 1040 pci_mapreg_info(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM, 1041 type, &rdev->fb_aper_offset, &rdev->fb_aper_size, NULL)) { 1042 printf(": can't get frambuffer info\n"); 1043 return; 1044 } 1045 if (rdev->fb_aper_offset == 0) { 1046 bus_size_t start, end; 1047 bus_addr_t base; 1048 1049 KASSERT(pa->pa_memex != NULL); 1050 1051 start = max(PCI_MEM_START, pa->pa_memex->ex_start); 1052 end = min(PCI_MEM_END, pa->pa_memex->ex_end); 1053 if (extent_alloc_subregion(pa->pa_memex, start, end, 1054 rdev->fb_aper_size, rdev->fb_aper_size, 0, 0, 0, &base)) { 1055 printf(": can't reserve framebuffer space\n"); 1056 return; 1057 } 1058 pci_conf_write(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM, base); 1059 if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT) 1060 pci_conf_write(pa->pa_pc, pa->pa_tag, 1061 RADEON_PCI_MEM + 4, (uint64_t)base >> 32); 1062 rdev->fb_aper_offset = base; 1063 } 1064 1065 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 1066 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i); 1067 if (type == PCI_MAPREG_TYPE_IO) { 1068 pci_mapreg_map(pa, i, type, 0, NULL, 1069 &rdev->rio_mem, NULL, &rdev->rio_mem_size, 0); 1070 break; 1071 } 1072 if (type == PCI_MAPREG_MEM_TYPE_64BIT) 1073 i += 4; 1074 } 1075 1076 if (rdev->family >= CHIP_BONAIRE) { 1077 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x18); 1078 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 1079 pci_mapreg_map(pa, 0x18, type, BUS_SPACE_MAP_LINEAR, NULL, 1080 &rdev->doorbell.bsh, &rdev->doorbell.base, 1081 &rdev->doorbell.size, 0)) { 1082 printf(": can't map doorbell space\n"); 1083 return; 1084 } 1085 rdev->doorbell.ptr = bus_space_vaddr(rdev->memt, 1086 rdev->doorbell.bsh); 1087 } 1088 1089 if (rdev->family >= CHIP_BONAIRE) 1090 rmmio_bar = 0x24; 1091 else 1092 rmmio_bar = 0x18; 1093 1094 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, rmmio_bar); 1095 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 1096 pci_mapreg_map(pa, rmmio_bar, type, BUS_SPACE_MAP_LINEAR, NULL, 1097 &rdev->rmmio_bsh, &rdev->rmmio_base, &rdev->rmmio_size, 0)) { 1098 printf(": can't map rmmio space\n"); 1099 return; 1100 } 1101 rdev->rmmio = bus_space_vaddr(rdev->memt, rdev->rmmio_bsh); 1102 1103 /* 1104 * Make sure we have a base address for the ROM such that we 1105 * can map it later. 1106 */ 1107 s = splhigh(); 1108 addr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 1109 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); 1110 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 1111 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, addr); 1112 splx(s); 1113 1114 if (addr == 0 && PCI_ROM_SIZE(mask) != 0 && pa->pa_memex) { 1115 bus_size_t size, start, end; 1116 bus_addr_t base; 1117 1118 size = PCI_ROM_SIZE(mask); 1119 start = max(PCI_MEM_START, pa->pa_memex->ex_start); 1120 end = min(PCI_MEM_END, pa->pa_memex->ex_end); 1121 if (extent_alloc_subregion(pa->pa_memex, start, end, size, 1122 size, 0, 0, 0, &base) == 0) 1123 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, base); 1124 } 1125 1126 /* update BUS flag */ 1127 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, NULL, NULL)) { 1128 rdev->flags |= RADEON_IS_AGP; 1129 } else if (pci_get_capability(pa->pa_pc, pa->pa_tag, 1130 PCI_CAP_PCIEXPRESS, NULL, NULL)) { 1131 rdev->flags |= RADEON_IS_PCIE; 1132 } else { 1133 rdev->flags |= RADEON_IS_PCI; 1134 } 1135 1136 if ((radeon_runtime_pm != 0) && 1137 radeon_has_atpx() && 1138 ((rdev->flags & RADEON_IS_IGP) == 0)) 1139 rdev->flags |= RADEON_IS_PX; 1140 1141 DRM_DEBUG("%s card detected\n", 1142 ((rdev->flags & RADEON_IS_AGP) ? "AGP" : 1143 (((rdev->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); 1144 1145 is_agp = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, 1146 NULL, NULL); 1147 1148 printf("\n"); 1149 1150 dev = drm_attach_pci(&kms_driver, pa, is_agp, rdev->primary, 1151 self, NULL); 1152 if (dev == NULL) { 1153 printf("%s: drm attach failed\n", rdev->self.dv_xname); 1154 return; 1155 } 1156 rdev->ddev = dev; 1157 rdev->pdev = dev->pdev; 1158 1159 if (!radeon_msi_ok(rdev)) 1160 pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED; 1161 1162 rdev->msi_enabled = 0; 1163 if (pci_intr_map_msi(pa, &rdev->intrh) == 0) 1164 rdev->msi_enabled = 1; 1165 else if (pci_intr_map(pa, &rdev->intrh) != 0) { 1166 printf("%s: couldn't map interrupt\n", rdev->self.dv_xname); 1167 return; 1168 } 1169 printf("%s: %s\n", rdev->self.dv_xname, 1170 pci_intr_string(pa->pa_pc, rdev->intrh)); 1171 1172 rdev->irqh = pci_intr_establish(pa->pa_pc, rdev->intrh, IPL_TTY, 1173 radeon_driver_irq_handler_kms, rdev->ddev, rdev->self.dv_xname); 1174 if (rdev->irqh == NULL) { 1175 printf("%s: couldn't establish interrupt\n", 1176 rdev->self.dv_xname); 1177 return; 1178 } 1179 rdev->pdev->irq = -1; 1180 1181 #ifdef __sparc64__ 1182 { 1183 struct rasops_info *ri; 1184 int node, console; 1185 1186 node = PCITAG_NODE(pa->pa_tag); 1187 console = (fbnode == node); 1188 1189 fb_setsize(&rdev->sf, 8, 1152, 900, node, 0); 1190 1191 /* 1192 * The firmware sets up the framebuffer such that it starts at 1193 * an offset from the start of video memory. 1194 */ 1195 rdev->fb_offset = 1196 bus_space_read_4(rdev->memt, rdev->rmmio_bsh, RADEON_CRTC_OFFSET); 1197 if (bus_space_map(rdev->memt, rdev->fb_aper_offset + rdev->fb_offset, 1198 rdev->sf.sf_fbsize, BUS_SPACE_MAP_LINEAR, &rdev->memh)) { 1199 printf("%s: can't map video memory\n", rdev->self.dv_xname); 1200 return; 1201 } 1202 1203 ri = &rdev->sf.sf_ro; 1204 ri->ri_bits = bus_space_vaddr(rdev->memt, rdev->memh); 1205 ri->ri_hw = rdev; 1206 ri->ri_updatecursor = NULL; 1207 1208 fbwscons_init(&rdev->sf, RI_VCONS | RI_WRONLY | RI_BSWAP, console); 1209 if (console) 1210 fbwscons_console_init(&rdev->sf, -1); 1211 } 1212 #endif 1213 1214 fb_aper = bus_space_mmap(rdev->memt, rdev->fb_aper_offset, 0, 0, 0); 1215 if (fb_aper != -1) 1216 rasops_claim_framebuffer(fb_aper, rdev->fb_aper_size, self); 1217 1218 rdev->shutdown = true; 1219 config_mountroot(self, radeondrm_attachhook); 1220 } 1221 1222 int 1223 radeondrm_forcedetach(struct radeon_device *rdev) 1224 { 1225 struct pci_softc *sc = (struct pci_softc *)rdev->self.dv_parent; 1226 pcitag_t tag = rdev->pa_tag; 1227 1228 #if NVGA > 0 1229 if (rdev->primary) 1230 vga_console_attached = 0; 1231 #endif 1232 1233 /* reprobe pci device for non efi systems */ 1234 #if NEFIFB > 0 1235 if (bios_efiinfo == NULL && !efifb_cb_found()) { 1236 #endif 1237 config_detach(&rdev->self, 0); 1238 return pci_probe_device(sc, tag, NULL, NULL); 1239 #if NEFIFB > 0 1240 } else if (rdev->primary) { 1241 efifb_reattach(); 1242 } 1243 #endif 1244 1245 return 0; 1246 } 1247 1248 void 1249 radeondrm_attachhook(struct device *self) 1250 { 1251 struct radeon_device *rdev = (struct radeon_device *)self; 1252 struct drm_device *dev = rdev->ddev; 1253 int r, acpi_status; 1254 1255 /* radeon_device_init should report only fatal error 1256 * like memory allocation failure or iomapping failure, 1257 * or memory manager initialization failure, it must 1258 * properly initialize the GPU MC controller and permit 1259 * VRAM allocation 1260 */ 1261 r = radeon_device_init(rdev, rdev->ddev, rdev->ddev->pdev, rdev->flags); 1262 if (r) { 1263 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 1264 radeon_fatal_error = 1; 1265 radeondrm_forcedetach(rdev); 1266 return; 1267 } 1268 1269 /* Again modeset_init should fail only on fatal error 1270 * otherwise it should provide enough functionalities 1271 * for shadowfb to run 1272 */ 1273 r = radeon_modeset_init(rdev); 1274 if (r) 1275 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); 1276 1277 /* Call ACPI methods: require modeset init 1278 * but failure is not fatal 1279 */ 1280 if (!r) { 1281 acpi_status = radeon_acpi_init(rdev); 1282 if (acpi_status) 1283 DRM_DEBUG("Error during ACPI methods call\n"); 1284 } 1285 1286 #ifdef notyet 1287 radeon_kfd_device_probe(rdev); 1288 radeon_kfd_device_init(rdev); 1289 #endif 1290 1291 if (radeon_is_px(rdev->ddev)) { 1292 pm_runtime_use_autosuspend(dev->dev); 1293 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 1294 pm_runtime_set_active(dev->dev); 1295 pm_runtime_allow(dev->dev); 1296 pm_runtime_mark_last_busy(dev->dev); 1297 pm_runtime_put_autosuspend(dev->dev); 1298 } 1299 1300 { 1301 struct wsemuldisplaydev_attach_args aa; 1302 struct rasops_info *ri = &rdev->ro; 1303 1304 task_set(&rdev->switchtask, radeondrm_doswitch, ri); 1305 1306 if (ri->ri_bits == NULL) 1307 return; 1308 1309 #ifdef __sparc64__ 1310 fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor); 1311 ri = &rdev->sf.sf_ro; 1312 #else 1313 radeondrm_setpal(rdev, ri); 1314 ri->ri_flg = RI_CENTER | RI_VCONS | RI_WRONLY; 1315 rasops_init(ri, 160, 160); 1316 1317 ri->ri_hw = rdev; 1318 #endif 1319 1320 radeondrm_stdscreen.capabilities = ri->ri_caps; 1321 radeondrm_stdscreen.nrows = ri->ri_rows; 1322 radeondrm_stdscreen.ncols = ri->ri_cols; 1323 radeondrm_stdscreen.textops = &ri->ri_ops; 1324 radeondrm_stdscreen.fontwidth = ri->ri_font->fontwidth; 1325 radeondrm_stdscreen.fontheight = ri->ri_font->fontheight; 1326 1327 aa.console = rdev->console; 1328 aa.primary = rdev->primary; 1329 aa.scrdata = &radeondrm_screenlist; 1330 aa.accessops = &radeondrm_accessops; 1331 aa.accesscookie = ri; 1332 aa.defaultscreens = 0; 1333 1334 if (rdev->console) { 1335 uint32_t defattr; 1336 1337 ri->ri_ops.pack_attr(ri->ri_active, 0, 0, 0, &defattr); 1338 wsdisplay_cnattach(&radeondrm_stdscreen, ri->ri_active, 1339 ri->ri_ccol, ri->ri_crow, defattr); 1340 } 1341 1342 /* 1343 * Now that we've taken over the console, disable decoding of 1344 * VGA legacy addresses, and opt out of arbitration. 1345 */ 1346 radeon_vga_set_state(rdev, false); 1347 pci_disable_legacy_vga(&rdev->self); 1348 1349 printf("%s: %dx%d, %dbpp\n", rdev->self.dv_xname, 1350 ri->ri_width, ri->ri_height, ri->ri_depth); 1351 1352 config_found_sm(&rdev->self, &aa, wsemuldisplaydevprint, 1353 wsemuldisplaydevsubmatch); 1354 1355 /* 1356 * in linux via radeon_pci_probe -> drm_get_pci_dev -> drm_dev_register 1357 */ 1358 drm_dev_register(rdev->ddev, rdev->flags); 1359 } 1360 } 1361 1362 int 1363 radeondrm_activate_kms(struct device *self, int act) 1364 { 1365 struct radeon_device *rdev = (struct radeon_device *)self; 1366 int rv = 0; 1367 1368 if (rdev->ddev == NULL || radeon_fatal_error) 1369 return (0); 1370 1371 switch (act) { 1372 case DVACT_QUIESCE: 1373 rv = config_activate_children(self, act); 1374 radeon_suspend_kms(rdev->ddev, true, true, false); 1375 break; 1376 case DVACT_SUSPEND: 1377 break; 1378 case DVACT_RESUME: 1379 break; 1380 case DVACT_WAKEUP: 1381 radeon_resume_kms(rdev->ddev, true, true); 1382 rv = config_activate_children(self, act); 1383 break; 1384 } 1385 1386 return (rv); 1387 } 1388