11099013bSjsg /*
21099013bSjsg * Copyright 2008 Advanced Micro Devices, Inc.
31099013bSjsg * Copyright 2008 Red Hat Inc.
41099013bSjsg * Copyright 2009 Jerome Glisse.
51099013bSjsg *
61099013bSjsg * Permission is hereby granted, free of charge, to any person obtaining a
71099013bSjsg * copy of this software and associated documentation files (the "Software"),
81099013bSjsg * to deal in the Software without restriction, including without limitation
91099013bSjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
101099013bSjsg * and/or sell copies of the Software, and to permit persons to whom the
111099013bSjsg * Software is furnished to do so, subject to the following conditions:
121099013bSjsg *
131099013bSjsg * The above copyright notice and this permission notice shall be included in
141099013bSjsg * all copies or substantial portions of the Software.
151099013bSjsg *
161099013bSjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
171099013bSjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
181099013bSjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
191099013bSjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
201099013bSjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
211099013bSjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
221099013bSjsg * OTHER DEALINGS IN THE SOFTWARE.
231099013bSjsg *
241099013bSjsg * Authors: Dave Airlie
251099013bSjsg * Alex Deucher
261099013bSjsg * Jerome Glisse
271099013bSjsg */
28c349dbc7Sjsg
29c349dbc7Sjsg #include <linux/pci.h>
30c349dbc7Sjsg
31c349dbc7Sjsg #include "atom.h"
321099013bSjsg #include "radeon.h"
331099013bSjsg #include "radeon_asic.h"
347ccd5a2cSjsg #include "radeon_audio.h"
351099013bSjsg #include "rs690d.h"
361099013bSjsg
rs690_mc_wait_for_idle(struct radeon_device * rdev)371099013bSjsg int rs690_mc_wait_for_idle(struct radeon_device *rdev)
381099013bSjsg {
391099013bSjsg unsigned i;
401099013bSjsg uint32_t tmp;
411099013bSjsg
421099013bSjsg for (i = 0; i < rdev->usec_timeout; i++) {
431099013bSjsg /* read MC_STATUS */
441099013bSjsg tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
451099013bSjsg if (G_000090_MC_SYSTEM_IDLE(tmp))
461099013bSjsg return 0;
471099013bSjsg udelay(1);
481099013bSjsg }
491099013bSjsg return -1;
501099013bSjsg }
511099013bSjsg
rs690_gpu_init(struct radeon_device * rdev)521099013bSjsg static void rs690_gpu_init(struct radeon_device *rdev)
531099013bSjsg {
541099013bSjsg /* FIXME: is this correct ? */
551099013bSjsg r420_pipes_init(rdev);
561099013bSjsg if (rs690_mc_wait_for_idle(rdev)) {
577f4dd379Sjsg pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n");
581099013bSjsg }
591099013bSjsg }
601099013bSjsg
611099013bSjsg union igp_info {
621099013bSjsg struct _ATOM_INTEGRATED_SYSTEM_INFO info;
631099013bSjsg struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
641099013bSjsg };
651099013bSjsg
rs690_pm_info(struct radeon_device * rdev)661099013bSjsg void rs690_pm_info(struct radeon_device *rdev)
671099013bSjsg {
681099013bSjsg int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
691099013bSjsg union igp_info *info;
701099013bSjsg uint16_t data_offset;
711099013bSjsg uint8_t frev, crev;
721099013bSjsg fixed20_12 tmp;
731099013bSjsg
741099013bSjsg if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
751099013bSjsg &frev, &crev, &data_offset)) {
761099013bSjsg info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
771099013bSjsg
781099013bSjsg /* Get various system informations from bios */
791099013bSjsg switch (crev) {
801099013bSjsg case 1:
811099013bSjsg tmp.full = dfixed_const(100);
821099013bSjsg rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
831099013bSjsg rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
841099013bSjsg if (le16_to_cpu(info->info.usK8MemoryClock))
851099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
861099013bSjsg else if (rdev->clock.default_mclk) {
871099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
881099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
891099013bSjsg } else
901099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(400);
911099013bSjsg rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
921099013bSjsg rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
931099013bSjsg break;
941099013bSjsg case 2:
951099013bSjsg tmp.full = dfixed_const(100);
961099013bSjsg rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
971099013bSjsg rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
981099013bSjsg if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
991099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
1001099013bSjsg else if (rdev->clock.default_mclk)
1011099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
1021099013bSjsg else
1031099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(66700);
1041099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
1051099013bSjsg rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
1061099013bSjsg rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
1071099013bSjsg rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
1081099013bSjsg break;
1091099013bSjsg default:
1101099013bSjsg /* We assume the slower possible clock ie worst case */
1111099013bSjsg rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
1121099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(200);
1131099013bSjsg rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
1141099013bSjsg rdev->pm.igp_ht_link_width.full = dfixed_const(8);
1151099013bSjsg DRM_ERROR("No integrated system info for your GPU, using safe default\n");
1161099013bSjsg break;
1171099013bSjsg }
1181099013bSjsg } else {
1191099013bSjsg /* We assume the slower possible clock ie worst case */
1201099013bSjsg rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
1211099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(200);
1221099013bSjsg rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
1231099013bSjsg rdev->pm.igp_ht_link_width.full = dfixed_const(8);
1241099013bSjsg DRM_ERROR("No integrated system info for your GPU, using safe default\n");
1251099013bSjsg }
1261099013bSjsg /* Compute various bandwidth */
1271099013bSjsg /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
1281099013bSjsg tmp.full = dfixed_const(4);
1291099013bSjsg rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
1301099013bSjsg /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
1311099013bSjsg * = ht_clk * ht_width / 5
1321099013bSjsg */
1331099013bSjsg tmp.full = dfixed_const(5);
1341099013bSjsg rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
1351099013bSjsg rdev->pm.igp_ht_link_width);
1361099013bSjsg rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
1371099013bSjsg if (tmp.full < rdev->pm.max_bandwidth.full) {
1381099013bSjsg /* HT link is a limiting factor */
1391099013bSjsg rdev->pm.max_bandwidth.full = tmp.full;
1401099013bSjsg }
1411099013bSjsg /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
1421099013bSjsg * = (sideport_clk * 14) / 10
1431099013bSjsg */
1441099013bSjsg tmp.full = dfixed_const(14);
1451099013bSjsg rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
1461099013bSjsg tmp.full = dfixed_const(10);
1471099013bSjsg rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
1481099013bSjsg }
1491099013bSjsg
rs690_mc_init(struct radeon_device * rdev)1501099013bSjsg static void rs690_mc_init(struct radeon_device *rdev)
1511099013bSjsg {
1521099013bSjsg u64 base;
1537ccd5a2cSjsg uint32_t h_addr, l_addr;
1547ccd5a2cSjsg unsigned long long k8_addr;
1551099013bSjsg
1561099013bSjsg rs400_gart_adjust_size(rdev);
1571099013bSjsg rdev->mc.vram_is_ddr = true;
1581099013bSjsg rdev->mc.vram_width = 128;
1591099013bSjsg rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1601099013bSjsg rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1611099013bSjsg rdev->mc.aper_base = rdev->fb_aper_offset;
1621099013bSjsg rdev->mc.aper_size = rdev->fb_aper_size;
1631099013bSjsg rdev->mc.visible_vram_size = rdev->mc.aper_size;
1641099013bSjsg base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
1651099013bSjsg base = G_000100_MC_FB_START(base) << 16;
1661099013bSjsg rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
167dc633288Sjsg /* Some boards seem to be configured for 128MB of sideport memory,
168dc633288Sjsg * but really only have 64MB. Just skip the sideport and use
169dc633288Sjsg * UMA memory.
170dc633288Sjsg */
171dc633288Sjsg if (rdev->mc.igp_sideport_enabled &&
172dc633288Sjsg (rdev->mc.real_vram_size == (384 * 1024 * 1024))) {
173dc633288Sjsg base += 128 * 1024 * 1024;
174dc633288Sjsg rdev->mc.real_vram_size -= 128 * 1024 * 1024;
175dc633288Sjsg rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
176dc633288Sjsg }
177dc633288Sjsg
1787ccd5a2cSjsg /* Use K8 direct mapping for fast fb access. */
1797ccd5a2cSjsg rdev->fastfb_working = false;
1807ccd5a2cSjsg h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
1817ccd5a2cSjsg l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
1827ccd5a2cSjsg k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1837ccd5a2cSjsg #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1847ccd5a2cSjsg if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1857ccd5a2cSjsg #endif
1867ccd5a2cSjsg {
1877ccd5a2cSjsg /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1887ccd5a2cSjsg * memory is present.
1897ccd5a2cSjsg */
190*5ca02815Sjsg if (!rdev->mc.igp_sideport_enabled && radeon_fastfb == 1) {
1917ccd5a2cSjsg DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1927ccd5a2cSjsg (unsigned long long)rdev->mc.aper_base, k8_addr);
1937ccd5a2cSjsg rdev->mc.aper_base = (resource_size_t)k8_addr;
1947ccd5a2cSjsg rdev->fastfb_working = true;
1957ccd5a2cSjsg }
1967ccd5a2cSjsg }
1977ccd5a2cSjsg
1981099013bSjsg rs690_pm_info(rdev);
1991099013bSjsg radeon_vram_location(rdev, &rdev->mc, base);
2001099013bSjsg rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
2011099013bSjsg radeon_gtt_location(rdev, &rdev->mc);
2021099013bSjsg radeon_update_bandwidth_info(rdev);
2031099013bSjsg }
2041099013bSjsg
rs690_line_buffer_adjust(struct radeon_device * rdev,struct drm_display_mode * mode1,struct drm_display_mode * mode2)2051099013bSjsg void rs690_line_buffer_adjust(struct radeon_device *rdev,
2061099013bSjsg struct drm_display_mode *mode1,
2071099013bSjsg struct drm_display_mode *mode2)
2081099013bSjsg {
2091099013bSjsg u32 tmp;
2101099013bSjsg
2117ccd5a2cSjsg /* Guess line buffer size to be 8192 pixels */
2127ccd5a2cSjsg u32 lb_size = 8192;
2137ccd5a2cSjsg
2141099013bSjsg /*
2151099013bSjsg * Line Buffer Setup
2161099013bSjsg * There is a single line buffer shared by both display controllers.
2171099013bSjsg * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
2181099013bSjsg * the display controllers. The paritioning can either be done
2191099013bSjsg * manually or via one of four preset allocations specified in bits 1:0:
2201099013bSjsg * 0 - line buffer is divided in half and shared between crtc
2211099013bSjsg * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
2221099013bSjsg * 2 - D1 gets the whole buffer
2231099013bSjsg * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
2241099013bSjsg * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
2251099013bSjsg * allocation mode. In manual allocation mode, D1 always starts at 0,
2261099013bSjsg * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
2271099013bSjsg */
2281099013bSjsg tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
2291099013bSjsg tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
2301099013bSjsg /* auto */
2311099013bSjsg if (mode1 && mode2) {
2321099013bSjsg if (mode1->hdisplay > mode2->hdisplay) {
2331099013bSjsg if (mode1->hdisplay > 2560)
2341099013bSjsg tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
2351099013bSjsg else
2361099013bSjsg tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
2371099013bSjsg } else if (mode2->hdisplay > mode1->hdisplay) {
2381099013bSjsg if (mode2->hdisplay > 2560)
2391099013bSjsg tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
2401099013bSjsg else
2411099013bSjsg tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
2421099013bSjsg } else
2431099013bSjsg tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
2441099013bSjsg } else if (mode1) {
2451099013bSjsg tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
2461099013bSjsg } else if (mode2) {
2471099013bSjsg tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
2481099013bSjsg }
2491099013bSjsg WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
2507ccd5a2cSjsg
2517ccd5a2cSjsg /* Save number of lines the linebuffer leads before the scanout */
2527ccd5a2cSjsg if (mode1)
2537ccd5a2cSjsg rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
2547ccd5a2cSjsg
2557ccd5a2cSjsg if (mode2)
2567ccd5a2cSjsg rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
2571099013bSjsg }
2581099013bSjsg
2591099013bSjsg struct rs690_watermark {
2601099013bSjsg u32 lb_request_fifo_depth;
2611099013bSjsg fixed20_12 num_line_pair;
2621099013bSjsg fixed20_12 estimated_width;
2631099013bSjsg fixed20_12 worst_case_latency;
2641099013bSjsg fixed20_12 consumption_rate;
2651099013bSjsg fixed20_12 active_time;
2661099013bSjsg fixed20_12 dbpp;
2671099013bSjsg fixed20_12 priority_mark_max;
2681099013bSjsg fixed20_12 priority_mark;
2691099013bSjsg fixed20_12 sclk;
2701099013bSjsg };
2711099013bSjsg
rs690_crtc_bandwidth_compute(struct radeon_device * rdev,struct radeon_crtc * crtc,struct rs690_watermark * wm,bool low)2721099013bSjsg static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
2731099013bSjsg struct radeon_crtc *crtc,
2747ccd5a2cSjsg struct rs690_watermark *wm,
2757ccd5a2cSjsg bool low)
2761099013bSjsg {
2771099013bSjsg struct drm_display_mode *mode = &crtc->base.mode;
2781099013bSjsg fixed20_12 a, b, c;
2791099013bSjsg fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
2801099013bSjsg fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
2817ccd5a2cSjsg fixed20_12 sclk, core_bandwidth, max_bandwidth;
2827ccd5a2cSjsg u32 selected_sclk;
2831099013bSjsg
2841099013bSjsg if (!crtc->base.enabled) {
2851099013bSjsg /* FIXME: wouldn't it better to set priority mark to maximum */
2861099013bSjsg wm->lb_request_fifo_depth = 4;
2871099013bSjsg return;
2881099013bSjsg }
2891099013bSjsg
2907ccd5a2cSjsg if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) &&
2917ccd5a2cSjsg (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
2927ccd5a2cSjsg selected_sclk = radeon_dpm_get_sclk(rdev, low);
2937ccd5a2cSjsg else
2947ccd5a2cSjsg selected_sclk = rdev->pm.current_sclk;
2957ccd5a2cSjsg
2967ccd5a2cSjsg /* sclk in Mhz */
2977ccd5a2cSjsg a.full = dfixed_const(100);
2987ccd5a2cSjsg sclk.full = dfixed_const(selected_sclk);
2997ccd5a2cSjsg sclk.full = dfixed_div(sclk, a);
3007ccd5a2cSjsg
3017ccd5a2cSjsg /* core_bandwidth = sclk(Mhz) * 16 */
3027ccd5a2cSjsg a.full = dfixed_const(16);
3037ccd5a2cSjsg core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
3047ccd5a2cSjsg
3051099013bSjsg if (crtc->vsc.full > dfixed_const(2))
3061099013bSjsg wm->num_line_pair.full = dfixed_const(2);
3071099013bSjsg else
3081099013bSjsg wm->num_line_pair.full = dfixed_const(1);
3091099013bSjsg
3101099013bSjsg b.full = dfixed_const(mode->crtc_hdisplay);
3111099013bSjsg c.full = dfixed_const(256);
3121099013bSjsg a.full = dfixed_div(b, c);
3131099013bSjsg request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
3141099013bSjsg request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
3151099013bSjsg if (a.full < dfixed_const(4)) {
3161099013bSjsg wm->lb_request_fifo_depth = 4;
3171099013bSjsg } else {
3181099013bSjsg wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
3191099013bSjsg }
3201099013bSjsg
3211099013bSjsg /* Determine consumption rate
3221099013bSjsg * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
3231099013bSjsg * vtaps = number of vertical taps,
3241099013bSjsg * vsc = vertical scaling ratio, defined as source/destination
3251099013bSjsg * hsc = horizontal scaling ration, defined as source/destination
3261099013bSjsg */
3271099013bSjsg a.full = dfixed_const(mode->clock);
3281099013bSjsg b.full = dfixed_const(1000);
3291099013bSjsg a.full = dfixed_div(a, b);
3301099013bSjsg pclk.full = dfixed_div(b, a);
3311099013bSjsg if (crtc->rmx_type != RMX_OFF) {
3321099013bSjsg b.full = dfixed_const(2);
3331099013bSjsg if (crtc->vsc.full > b.full)
3341099013bSjsg b.full = crtc->vsc.full;
3351099013bSjsg b.full = dfixed_mul(b, crtc->hsc);
3361099013bSjsg c.full = dfixed_const(2);
3371099013bSjsg b.full = dfixed_div(b, c);
3381099013bSjsg consumption_time.full = dfixed_div(pclk, b);
3391099013bSjsg } else {
3401099013bSjsg consumption_time.full = pclk.full;
3411099013bSjsg }
3421099013bSjsg a.full = dfixed_const(1);
3431099013bSjsg wm->consumption_rate.full = dfixed_div(a, consumption_time);
3441099013bSjsg
3451099013bSjsg
3461099013bSjsg /* Determine line time
3471099013bSjsg * LineTime = total time for one line of displayhtotal
3481099013bSjsg * LineTime = total number of horizontal pixels
3491099013bSjsg * pclk = pixel clock period(ns)
3501099013bSjsg */
3511099013bSjsg a.full = dfixed_const(crtc->base.mode.crtc_htotal);
3521099013bSjsg line_time.full = dfixed_mul(a, pclk);
3531099013bSjsg
3541099013bSjsg /* Determine active time
3551099013bSjsg * ActiveTime = time of active region of display within one line,
3561099013bSjsg * hactive = total number of horizontal active pixels
3571099013bSjsg * htotal = total number of horizontal pixels
3581099013bSjsg */
3591099013bSjsg a.full = dfixed_const(crtc->base.mode.crtc_htotal);
3601099013bSjsg b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
3611099013bSjsg wm->active_time.full = dfixed_mul(line_time, b);
3621099013bSjsg wm->active_time.full = dfixed_div(wm->active_time, a);
3631099013bSjsg
3641099013bSjsg /* Maximun bandwidth is the minimun bandwidth of all component */
3657ccd5a2cSjsg max_bandwidth = core_bandwidth;
3661099013bSjsg if (rdev->mc.igp_sideport_enabled) {
3677ccd5a2cSjsg if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
3681099013bSjsg rdev->pm.sideport_bandwidth.full)
3697ccd5a2cSjsg max_bandwidth = rdev->pm.sideport_bandwidth;
3701591a329Skettenis read_delay_latency.full = dfixed_const(370 * 800);
3711591a329Skettenis a.full = dfixed_const(1000);
3721591a329Skettenis b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a);
3731591a329Skettenis read_delay_latency.full = dfixed_div(read_delay_latency, b);
3741591a329Skettenis read_delay_latency.full = dfixed_mul(read_delay_latency, a);
3751099013bSjsg } else {
3767ccd5a2cSjsg if (max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
3771099013bSjsg rdev->pm.k8_bandwidth.full)
3787ccd5a2cSjsg max_bandwidth = rdev->pm.k8_bandwidth;
3797ccd5a2cSjsg if (max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
3801099013bSjsg rdev->pm.ht_bandwidth.full)
3817ccd5a2cSjsg max_bandwidth = rdev->pm.ht_bandwidth;
3821099013bSjsg read_delay_latency.full = dfixed_const(5000);
3831099013bSjsg }
3841099013bSjsg
3851099013bSjsg /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
3861099013bSjsg a.full = dfixed_const(16);
3877ccd5a2cSjsg sclk.full = dfixed_mul(max_bandwidth, a);
3881099013bSjsg a.full = dfixed_const(1000);
3897ccd5a2cSjsg sclk.full = dfixed_div(a, sclk);
3901099013bSjsg /* Determine chunk time
3911099013bSjsg * ChunkTime = the time it takes the DCP to send one chunk of data
3921099013bSjsg * to the LB which consists of pipeline delay and inter chunk gap
3931099013bSjsg * sclk = system clock(ns)
3941099013bSjsg */
3951099013bSjsg a.full = dfixed_const(256 * 13);
3967ccd5a2cSjsg chunk_time.full = dfixed_mul(sclk, a);
3971099013bSjsg a.full = dfixed_const(10);
3981099013bSjsg chunk_time.full = dfixed_div(chunk_time, a);
3991099013bSjsg
4001099013bSjsg /* Determine the worst case latency
4011099013bSjsg * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
4021099013bSjsg * WorstCaseLatency = worst case time from urgent to when the MC starts
4031099013bSjsg * to return data
4041099013bSjsg * READ_DELAY_IDLE_MAX = constant of 1us
4051099013bSjsg * ChunkTime = time it takes the DCP to send one chunk of data to the LB
4061099013bSjsg * which consists of pipeline delay and inter chunk gap
4071099013bSjsg */
4081099013bSjsg if (dfixed_trunc(wm->num_line_pair) > 1) {
4091099013bSjsg a.full = dfixed_const(3);
4101099013bSjsg wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
4111099013bSjsg wm->worst_case_latency.full += read_delay_latency.full;
4121099013bSjsg } else {
4131099013bSjsg a.full = dfixed_const(2);
4141099013bSjsg wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
4151099013bSjsg wm->worst_case_latency.full += read_delay_latency.full;
4161099013bSjsg }
4171099013bSjsg
4181099013bSjsg /* Determine the tolerable latency
4191099013bSjsg * TolerableLatency = Any given request has only 1 line time
4201099013bSjsg * for the data to be returned
4211099013bSjsg * LBRequestFifoDepth = Number of chunk requests the LB can
4221099013bSjsg * put into the request FIFO for a display
4231099013bSjsg * LineTime = total time for one line of display
4241099013bSjsg * ChunkTime = the time it takes the DCP to send one chunk
4251099013bSjsg * of data to the LB which consists of
4261099013bSjsg * pipeline delay and inter chunk gap
4271099013bSjsg */
4281099013bSjsg if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
4291099013bSjsg tolerable_latency.full = line_time.full;
4301099013bSjsg } else {
4311099013bSjsg tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
4321099013bSjsg tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
4331099013bSjsg tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
4341099013bSjsg tolerable_latency.full = line_time.full - tolerable_latency.full;
4351099013bSjsg }
4361099013bSjsg /* We assume worst case 32bits (4 bytes) */
4371099013bSjsg wm->dbpp.full = dfixed_const(4 * 8);
4381099013bSjsg
4391099013bSjsg /* Determine the maximum priority mark
4401099013bSjsg * width = viewport width in pixels
4411099013bSjsg */
4421099013bSjsg a.full = dfixed_const(16);
4431099013bSjsg wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
4441099013bSjsg wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
4451099013bSjsg wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
4461099013bSjsg
4471099013bSjsg /* Determine estimated width */
4481099013bSjsg estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
4491099013bSjsg estimated_width.full = dfixed_div(estimated_width, consumption_time);
4501099013bSjsg if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
4511099013bSjsg wm->priority_mark.full = dfixed_const(10);
4521099013bSjsg } else {
4531099013bSjsg a.full = dfixed_const(16);
4541099013bSjsg wm->priority_mark.full = dfixed_div(estimated_width, a);
4551099013bSjsg wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
4561099013bSjsg wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
4571099013bSjsg }
4581099013bSjsg }
4591099013bSjsg
rs690_compute_mode_priority(struct radeon_device * rdev,struct rs690_watermark * wm0,struct rs690_watermark * wm1,struct drm_display_mode * mode0,struct drm_display_mode * mode1,u32 * d1mode_priority_a_cnt,u32 * d2mode_priority_a_cnt)4607ccd5a2cSjsg static void rs690_compute_mode_priority(struct radeon_device *rdev,
4617ccd5a2cSjsg struct rs690_watermark *wm0,
4627ccd5a2cSjsg struct rs690_watermark *wm1,
4637ccd5a2cSjsg struct drm_display_mode *mode0,
4647ccd5a2cSjsg struct drm_display_mode *mode1,
4657ccd5a2cSjsg u32 *d1mode_priority_a_cnt,
4667ccd5a2cSjsg u32 *d2mode_priority_a_cnt)
4677ccd5a2cSjsg {
4687ccd5a2cSjsg fixed20_12 priority_mark02, priority_mark12, fill_rate;
4697ccd5a2cSjsg fixed20_12 a, b;
4707ccd5a2cSjsg
4717ccd5a2cSjsg *d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
4727ccd5a2cSjsg *d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
4737ccd5a2cSjsg
4747ccd5a2cSjsg if (mode0 && mode1) {
4757ccd5a2cSjsg if (dfixed_trunc(wm0->dbpp) > 64)
4767ccd5a2cSjsg a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
4777ccd5a2cSjsg else
4787ccd5a2cSjsg a.full = wm0->num_line_pair.full;
4797ccd5a2cSjsg if (dfixed_trunc(wm1->dbpp) > 64)
4807ccd5a2cSjsg b.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
4817ccd5a2cSjsg else
4827ccd5a2cSjsg b.full = wm1->num_line_pair.full;
4837ccd5a2cSjsg a.full += b.full;
4847ccd5a2cSjsg fill_rate.full = dfixed_div(wm0->sclk, a);
4857ccd5a2cSjsg if (wm0->consumption_rate.full > fill_rate.full) {
4867ccd5a2cSjsg b.full = wm0->consumption_rate.full - fill_rate.full;
4877ccd5a2cSjsg b.full = dfixed_mul(b, wm0->active_time);
4887ccd5a2cSjsg a.full = dfixed_mul(wm0->worst_case_latency,
4897ccd5a2cSjsg wm0->consumption_rate);
4907ccd5a2cSjsg a.full = a.full + b.full;
4917ccd5a2cSjsg b.full = dfixed_const(16 * 1000);
4927ccd5a2cSjsg priority_mark02.full = dfixed_div(a, b);
4937ccd5a2cSjsg } else {
4947ccd5a2cSjsg a.full = dfixed_mul(wm0->worst_case_latency,
4957ccd5a2cSjsg wm0->consumption_rate);
4967ccd5a2cSjsg b.full = dfixed_const(16 * 1000);
4977ccd5a2cSjsg priority_mark02.full = dfixed_div(a, b);
4987ccd5a2cSjsg }
4997ccd5a2cSjsg if (wm1->consumption_rate.full > fill_rate.full) {
5007ccd5a2cSjsg b.full = wm1->consumption_rate.full - fill_rate.full;
5017ccd5a2cSjsg b.full = dfixed_mul(b, wm1->active_time);
5027ccd5a2cSjsg a.full = dfixed_mul(wm1->worst_case_latency,
5037ccd5a2cSjsg wm1->consumption_rate);
5047ccd5a2cSjsg a.full = a.full + b.full;
5057ccd5a2cSjsg b.full = dfixed_const(16 * 1000);
5067ccd5a2cSjsg priority_mark12.full = dfixed_div(a, b);
5077ccd5a2cSjsg } else {
5087ccd5a2cSjsg a.full = dfixed_mul(wm1->worst_case_latency,
5097ccd5a2cSjsg wm1->consumption_rate);
5107ccd5a2cSjsg b.full = dfixed_const(16 * 1000);
5117ccd5a2cSjsg priority_mark12.full = dfixed_div(a, b);
5127ccd5a2cSjsg }
5137ccd5a2cSjsg if (wm0->priority_mark.full > priority_mark02.full)
5147ccd5a2cSjsg priority_mark02.full = wm0->priority_mark.full;
5157ccd5a2cSjsg if (wm0->priority_mark_max.full > priority_mark02.full)
5167ccd5a2cSjsg priority_mark02.full = wm0->priority_mark_max.full;
5177ccd5a2cSjsg if (wm1->priority_mark.full > priority_mark12.full)
5187ccd5a2cSjsg priority_mark12.full = wm1->priority_mark.full;
5197ccd5a2cSjsg if (wm1->priority_mark_max.full > priority_mark12.full)
5207ccd5a2cSjsg priority_mark12.full = wm1->priority_mark_max.full;
5217ccd5a2cSjsg *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
5227ccd5a2cSjsg *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
5237ccd5a2cSjsg if (rdev->disp_priority == 2) {
5247ccd5a2cSjsg *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
5257ccd5a2cSjsg *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
5267ccd5a2cSjsg }
5277ccd5a2cSjsg } else if (mode0) {
5287ccd5a2cSjsg if (dfixed_trunc(wm0->dbpp) > 64)
5297ccd5a2cSjsg a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
5307ccd5a2cSjsg else
5317ccd5a2cSjsg a.full = wm0->num_line_pair.full;
5327ccd5a2cSjsg fill_rate.full = dfixed_div(wm0->sclk, a);
5337ccd5a2cSjsg if (wm0->consumption_rate.full > fill_rate.full) {
5347ccd5a2cSjsg b.full = wm0->consumption_rate.full - fill_rate.full;
5357ccd5a2cSjsg b.full = dfixed_mul(b, wm0->active_time);
5367ccd5a2cSjsg a.full = dfixed_mul(wm0->worst_case_latency,
5377ccd5a2cSjsg wm0->consumption_rate);
5387ccd5a2cSjsg a.full = a.full + b.full;
5397ccd5a2cSjsg b.full = dfixed_const(16 * 1000);
5407ccd5a2cSjsg priority_mark02.full = dfixed_div(a, b);
5417ccd5a2cSjsg } else {
5427ccd5a2cSjsg a.full = dfixed_mul(wm0->worst_case_latency,
5437ccd5a2cSjsg wm0->consumption_rate);
5447ccd5a2cSjsg b.full = dfixed_const(16 * 1000);
5457ccd5a2cSjsg priority_mark02.full = dfixed_div(a, b);
5467ccd5a2cSjsg }
5477ccd5a2cSjsg if (wm0->priority_mark.full > priority_mark02.full)
5487ccd5a2cSjsg priority_mark02.full = wm0->priority_mark.full;
5497ccd5a2cSjsg if (wm0->priority_mark_max.full > priority_mark02.full)
5507ccd5a2cSjsg priority_mark02.full = wm0->priority_mark_max.full;
5517ccd5a2cSjsg *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
5527ccd5a2cSjsg if (rdev->disp_priority == 2)
5537ccd5a2cSjsg *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
5547ccd5a2cSjsg } else if (mode1) {
5557ccd5a2cSjsg if (dfixed_trunc(wm1->dbpp) > 64)
5567ccd5a2cSjsg a.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
5577ccd5a2cSjsg else
5587ccd5a2cSjsg a.full = wm1->num_line_pair.full;
5597ccd5a2cSjsg fill_rate.full = dfixed_div(wm1->sclk, a);
5607ccd5a2cSjsg if (wm1->consumption_rate.full > fill_rate.full) {
5617ccd5a2cSjsg b.full = wm1->consumption_rate.full - fill_rate.full;
5627ccd5a2cSjsg b.full = dfixed_mul(b, wm1->active_time);
5637ccd5a2cSjsg a.full = dfixed_mul(wm1->worst_case_latency,
5647ccd5a2cSjsg wm1->consumption_rate);
5657ccd5a2cSjsg a.full = a.full + b.full;
5667ccd5a2cSjsg b.full = dfixed_const(16 * 1000);
5677ccd5a2cSjsg priority_mark12.full = dfixed_div(a, b);
5687ccd5a2cSjsg } else {
5697ccd5a2cSjsg a.full = dfixed_mul(wm1->worst_case_latency,
5707ccd5a2cSjsg wm1->consumption_rate);
5717ccd5a2cSjsg b.full = dfixed_const(16 * 1000);
5727ccd5a2cSjsg priority_mark12.full = dfixed_div(a, b);
5737ccd5a2cSjsg }
5747ccd5a2cSjsg if (wm1->priority_mark.full > priority_mark12.full)
5757ccd5a2cSjsg priority_mark12.full = wm1->priority_mark.full;
5767ccd5a2cSjsg if (wm1->priority_mark_max.full > priority_mark12.full)
5777ccd5a2cSjsg priority_mark12.full = wm1->priority_mark_max.full;
5787ccd5a2cSjsg *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
5797ccd5a2cSjsg if (rdev->disp_priority == 2)
5807ccd5a2cSjsg *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
5817ccd5a2cSjsg }
5827ccd5a2cSjsg }
5837ccd5a2cSjsg
rs690_bandwidth_update(struct radeon_device * rdev)5841099013bSjsg void rs690_bandwidth_update(struct radeon_device *rdev)
5851099013bSjsg {
5861099013bSjsg struct drm_display_mode *mode0 = NULL;
5871099013bSjsg struct drm_display_mode *mode1 = NULL;
5887ccd5a2cSjsg struct rs690_watermark wm0_high, wm0_low;
5897ccd5a2cSjsg struct rs690_watermark wm1_high, wm1_low;
5901099013bSjsg u32 tmp;
5917ccd5a2cSjsg u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
5927ccd5a2cSjsg u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
5937ccd5a2cSjsg
5947ccd5a2cSjsg if (!rdev->mode_info.mode_config_initialized)
5957ccd5a2cSjsg return;
5961099013bSjsg
5971099013bSjsg radeon_update_display_priority(rdev);
5981099013bSjsg
5991099013bSjsg if (rdev->mode_info.crtcs[0]->base.enabled)
6001099013bSjsg mode0 = &rdev->mode_info.crtcs[0]->base.mode;
6011099013bSjsg if (rdev->mode_info.crtcs[1]->base.enabled)
6021099013bSjsg mode1 = &rdev->mode_info.crtcs[1]->base.mode;
6031099013bSjsg /*
6041099013bSjsg * Set display0/1 priority up in the memory controller for
6051099013bSjsg * modes if the user specifies HIGH for displaypriority
6061099013bSjsg * option.
6071099013bSjsg */
6081099013bSjsg if ((rdev->disp_priority == 2) &&
6091099013bSjsg ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
6101099013bSjsg tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
6111099013bSjsg tmp &= C_000104_MC_DISP0R_INIT_LAT;
6121099013bSjsg tmp &= C_000104_MC_DISP1R_INIT_LAT;
6131099013bSjsg if (mode0)
6141099013bSjsg tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
6151099013bSjsg if (mode1)
6161099013bSjsg tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
6171099013bSjsg WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
6181099013bSjsg }
6191099013bSjsg rs690_line_buffer_adjust(rdev, mode0, mode1);
6201099013bSjsg
6211099013bSjsg if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
6221099013bSjsg WREG32(R_006C9C_DCP_CONTROL, 0);
6231099013bSjsg if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
6241099013bSjsg WREG32(R_006C9C_DCP_CONTROL, 2);
6251099013bSjsg
6267ccd5a2cSjsg rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
6277ccd5a2cSjsg rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
6281099013bSjsg
6297ccd5a2cSjsg rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true);
6307ccd5a2cSjsg rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true);
6317ccd5a2cSjsg
6327ccd5a2cSjsg tmp = (wm0_high.lb_request_fifo_depth - 1);
6337ccd5a2cSjsg tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16;
6341099013bSjsg WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
6351099013bSjsg
6367ccd5a2cSjsg rs690_compute_mode_priority(rdev,
6377ccd5a2cSjsg &wm0_high, &wm1_high,
6387ccd5a2cSjsg mode0, mode1,
6397ccd5a2cSjsg &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
6407ccd5a2cSjsg rs690_compute_mode_priority(rdev,
6417ccd5a2cSjsg &wm0_low, &wm1_low,
6427ccd5a2cSjsg mode0, mode1,
6437ccd5a2cSjsg &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
6441099013bSjsg
6451099013bSjsg WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
6467ccd5a2cSjsg WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
6471099013bSjsg WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
6487ccd5a2cSjsg WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
6491099013bSjsg }
6501099013bSjsg
rs690_mc_rreg(struct radeon_device * rdev,uint32_t reg)6511099013bSjsg uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
6521099013bSjsg {
6537ccd5a2cSjsg unsigned long flags;
6541099013bSjsg uint32_t r;
6551099013bSjsg
6567ccd5a2cSjsg spin_lock_irqsave(&rdev->mc_idx_lock, flags);
6571099013bSjsg WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
6581099013bSjsg r = RREG32(R_00007C_MC_DATA);
6591099013bSjsg WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
6607ccd5a2cSjsg spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
6611099013bSjsg return r;
6621099013bSjsg }
6631099013bSjsg
rs690_mc_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)6641099013bSjsg void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
6651099013bSjsg {
6667ccd5a2cSjsg unsigned long flags;
6677ccd5a2cSjsg
6687ccd5a2cSjsg spin_lock_irqsave(&rdev->mc_idx_lock, flags);
6691099013bSjsg WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
6701099013bSjsg S_000078_MC_IND_WR_EN(1));
6711099013bSjsg WREG32(R_00007C_MC_DATA, v);
6721099013bSjsg WREG32(R_000078_MC_INDEX, 0x7F);
6737ccd5a2cSjsg spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
6741099013bSjsg }
6751099013bSjsg
rs690_mc_program(struct radeon_device * rdev)6761099013bSjsg static void rs690_mc_program(struct radeon_device *rdev)
6771099013bSjsg {
6781099013bSjsg struct rv515_mc_save save;
6791099013bSjsg
6801099013bSjsg /* Stops all mc clients */
6811099013bSjsg rv515_mc_stop(rdev, &save);
6821099013bSjsg
6831099013bSjsg /* Wait for mc idle */
6841099013bSjsg if (rs690_mc_wait_for_idle(rdev))
6851099013bSjsg dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
6861099013bSjsg /* Program MC, should be a 32bits limited address space */
6871099013bSjsg WREG32_MC(R_000100_MCCFG_FB_LOCATION,
6881099013bSjsg S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
6891099013bSjsg S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
6901099013bSjsg WREG32(R_000134_HDP_FB_LOCATION,
6911099013bSjsg S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
6921099013bSjsg
6931099013bSjsg rv515_mc_resume(rdev, &save);
6941099013bSjsg }
6951099013bSjsg
rs690_startup(struct radeon_device * rdev)6961099013bSjsg static int rs690_startup(struct radeon_device *rdev)
6971099013bSjsg {
6981099013bSjsg int r;
6991099013bSjsg
7001099013bSjsg rs690_mc_program(rdev);
7011099013bSjsg /* Resume clock */
7021099013bSjsg rv515_clock_startup(rdev);
7031099013bSjsg /* Initialize GPU configuration (# pipes, ...) */
7041099013bSjsg rs690_gpu_init(rdev);
7051099013bSjsg /* Initialize GART (initialize after TTM so we can allocate
7061099013bSjsg * memory through TTM but finalize after TTM) */
7071099013bSjsg r = rs400_gart_enable(rdev);
7081099013bSjsg if (r)
7091099013bSjsg return r;
7101099013bSjsg
7111099013bSjsg /* allocate wb buffer */
7121099013bSjsg r = radeon_wb_init(rdev);
7131099013bSjsg if (r)
7141099013bSjsg return r;
7151099013bSjsg
7161099013bSjsg r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
7171099013bSjsg if (r) {
7181099013bSjsg dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
7191099013bSjsg return r;
7201099013bSjsg }
7211099013bSjsg
7221099013bSjsg /* Enable IRQ */
72355fe5614Sjsg if (!rdev->irq.installed) {
72455fe5614Sjsg r = radeon_irq_kms_init(rdev);
72555fe5614Sjsg if (r)
72655fe5614Sjsg return r;
72755fe5614Sjsg }
72855fe5614Sjsg
7291099013bSjsg rs600_irq_set(rdev);
7301099013bSjsg rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
7311099013bSjsg /* 1M ring buffer */
7321099013bSjsg r = r100_cp_init(rdev, 1024 * 1024);
7331099013bSjsg if (r) {
7341099013bSjsg dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
7351099013bSjsg return r;
7361099013bSjsg }
7371099013bSjsg
7381099013bSjsg r = radeon_ib_pool_init(rdev);
7391099013bSjsg if (r) {
7401099013bSjsg dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
7411099013bSjsg return r;
7421099013bSjsg }
7431099013bSjsg
7447ccd5a2cSjsg r = radeon_audio_init(rdev);
7451099013bSjsg if (r) {
7461099013bSjsg dev_err(rdev->dev, "failed initializing audio\n");
7471099013bSjsg return r;
7481099013bSjsg }
7491099013bSjsg
7501099013bSjsg return 0;
7511099013bSjsg }
7521099013bSjsg
rs690_resume(struct radeon_device * rdev)7531099013bSjsg int rs690_resume(struct radeon_device *rdev)
7541099013bSjsg {
7551099013bSjsg int r;
7561099013bSjsg
7571099013bSjsg /* Make sur GART are not working */
7581099013bSjsg rs400_gart_disable(rdev);
7591099013bSjsg /* Resume clock before doing reset */
7601099013bSjsg rv515_clock_startup(rdev);
7611099013bSjsg /* Reset gpu before posting otherwise ATOM will enter infinite loop */
7621099013bSjsg if (radeon_asic_reset(rdev)) {
7631099013bSjsg dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
7641099013bSjsg RREG32(R_000E40_RBBM_STATUS),
7651099013bSjsg RREG32(R_0007C0_CP_STAT));
7661099013bSjsg }
7671099013bSjsg /* post */
7681099013bSjsg atom_asic_init(rdev->mode_info.atom_context);
7691099013bSjsg /* Resume clock after posting */
7701099013bSjsg rv515_clock_startup(rdev);
7711099013bSjsg /* Initialize surface registers */
7721099013bSjsg radeon_surface_init(rdev);
7731099013bSjsg
7741099013bSjsg rdev->accel_working = true;
7751099013bSjsg r = rs690_startup(rdev);
7761099013bSjsg if (r) {
7771099013bSjsg rdev->accel_working = false;
7781099013bSjsg }
7791099013bSjsg return r;
7801099013bSjsg }
7811099013bSjsg
rs690_suspend(struct radeon_device * rdev)7821099013bSjsg int rs690_suspend(struct radeon_device *rdev)
7831099013bSjsg {
7847ccd5a2cSjsg radeon_pm_suspend(rdev);
7857ccd5a2cSjsg radeon_audio_fini(rdev);
7861099013bSjsg r100_cp_disable(rdev);
7871099013bSjsg radeon_wb_disable(rdev);
7881099013bSjsg rs600_irq_disable(rdev);
7891099013bSjsg rs400_gart_disable(rdev);
7901099013bSjsg return 0;
7911099013bSjsg }
7921099013bSjsg
rs690_fini(struct radeon_device * rdev)7931099013bSjsg void rs690_fini(struct radeon_device *rdev)
7941099013bSjsg {
7957ccd5a2cSjsg radeon_pm_fini(rdev);
7967ccd5a2cSjsg radeon_audio_fini(rdev);
7971099013bSjsg r100_cp_fini(rdev);
7981099013bSjsg radeon_wb_fini(rdev);
7991099013bSjsg radeon_ib_pool_fini(rdev);
8001099013bSjsg radeon_gem_fini(rdev);
8011099013bSjsg rs400_gart_fini(rdev);
8021099013bSjsg radeon_irq_kms_fini(rdev);
8031099013bSjsg radeon_fence_driver_fini(rdev);
8041099013bSjsg radeon_bo_fini(rdev);
8051099013bSjsg radeon_atombios_fini(rdev);
806de5631a0Sjsg kfree(rdev->bios);
8071099013bSjsg rdev->bios = NULL;
8081099013bSjsg }
8091099013bSjsg
rs690_init(struct radeon_device * rdev)8101099013bSjsg int rs690_init(struct radeon_device *rdev)
8111099013bSjsg {
8121099013bSjsg int r;
8131099013bSjsg
8141099013bSjsg /* Disable VGA */
8151099013bSjsg rv515_vga_render_disable(rdev);
8161099013bSjsg /* Initialize scratch registers */
8171099013bSjsg radeon_scratch_init(rdev);
8181099013bSjsg /* Initialize surface registers */
8191099013bSjsg radeon_surface_init(rdev);
8201099013bSjsg /* restore some register to sane defaults */
8211099013bSjsg r100_restore_sanity(rdev);
8221099013bSjsg /* TODO: disable VGA need to use VGA request */
8231099013bSjsg /* BIOS*/
8241099013bSjsg if (!radeon_get_bios(rdev)) {
8251099013bSjsg if (ASIC_IS_AVIVO(rdev))
8261099013bSjsg return -EINVAL;
8271099013bSjsg }
8281099013bSjsg if (rdev->is_atom_bios) {
8291099013bSjsg r = radeon_atombios_init(rdev);
8301099013bSjsg if (r)
8311099013bSjsg return r;
8321099013bSjsg } else {
8331099013bSjsg dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
8341099013bSjsg return -EINVAL;
8351099013bSjsg }
8361099013bSjsg /* Reset gpu before posting otherwise ATOM will enter infinite loop */
8371099013bSjsg if (radeon_asic_reset(rdev)) {
8381099013bSjsg dev_warn(rdev->dev,
8391099013bSjsg "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
8401099013bSjsg RREG32(R_000E40_RBBM_STATUS),
8411099013bSjsg RREG32(R_0007C0_CP_STAT));
8421099013bSjsg }
8431099013bSjsg /* check if cards are posted or not */
8441099013bSjsg if (radeon_boot_test_post_card(rdev) == false)
8451099013bSjsg return -EINVAL;
8461099013bSjsg
8471099013bSjsg /* Initialize clocks */
8481099013bSjsg radeon_get_clock_info(rdev->ddev);
8491099013bSjsg /* initialize memory controller */
8501099013bSjsg rs690_mc_init(rdev);
8511099013bSjsg rv515_debugfs(rdev);
8521099013bSjsg /* Fence driver */
853*5ca02815Sjsg radeon_fence_driver_init(rdev);
8541099013bSjsg /* Memory manager */
8551099013bSjsg r = radeon_bo_init(rdev);
8561099013bSjsg if (r)
8571099013bSjsg return r;
8581099013bSjsg r = rs400_gart_init(rdev);
8591099013bSjsg if (r)
8601099013bSjsg return r;
8611099013bSjsg rs600_set_safe_registers(rdev);
8621099013bSjsg
8637ccd5a2cSjsg /* Initialize power management */
8647ccd5a2cSjsg radeon_pm_init(rdev);
8657ccd5a2cSjsg
8661099013bSjsg rdev->accel_working = true;
8671099013bSjsg r = rs690_startup(rdev);
8681099013bSjsg if (r) {
8691099013bSjsg /* Somethings want wront with the accel init stop accel */
8701099013bSjsg dev_err(rdev->dev, "Disabling GPU acceleration\n");
8711099013bSjsg r100_cp_fini(rdev);
8721099013bSjsg radeon_wb_fini(rdev);
8731099013bSjsg radeon_ib_pool_fini(rdev);
8741099013bSjsg rs400_gart_fini(rdev);
8751099013bSjsg radeon_irq_kms_fini(rdev);
8761099013bSjsg rdev->accel_working = false;
8771099013bSjsg }
8781099013bSjsg return 0;
8791099013bSjsg }
880