1*55fe5614Sjsg /* $OpenBSD: rs690.c,v 1.4 2014/02/09 12:33:44 jsg Exp $ */ 21099013bSjsg /* 31099013bSjsg * Copyright 2008 Advanced Micro Devices, Inc. 41099013bSjsg * Copyright 2008 Red Hat Inc. 51099013bSjsg * Copyright 2009 Jerome Glisse. 61099013bSjsg * 71099013bSjsg * Permission is hereby granted, free of charge, to any person obtaining a 81099013bSjsg * copy of this software and associated documentation files (the "Software"), 91099013bSjsg * to deal in the Software without restriction, including without limitation 101099013bSjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 111099013bSjsg * and/or sell copies of the Software, and to permit persons to whom the 121099013bSjsg * Software is furnished to do so, subject to the following conditions: 131099013bSjsg * 141099013bSjsg * The above copyright notice and this permission notice shall be included in 151099013bSjsg * all copies or substantial portions of the Software. 161099013bSjsg * 171099013bSjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 181099013bSjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 191099013bSjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 201099013bSjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 211099013bSjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 221099013bSjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 231099013bSjsg * OTHER DEALINGS IN THE SOFTWARE. 241099013bSjsg * 251099013bSjsg * Authors: Dave Airlie 261099013bSjsg * Alex Deucher 271099013bSjsg * Jerome Glisse 281099013bSjsg */ 291099013bSjsg #include <dev/pci/drm/drmP.h> 301099013bSjsg #include "radeon.h" 311099013bSjsg #include "radeon_asic.h" 321099013bSjsg #include "atom.h" 331099013bSjsg #include "rs690d.h" 341099013bSjsg 351099013bSjsg int rs690_mc_wait_for_idle(struct radeon_device *rdev) 361099013bSjsg { 371099013bSjsg unsigned i; 381099013bSjsg uint32_t tmp; 391099013bSjsg 401099013bSjsg for (i = 0; i < rdev->usec_timeout; i++) { 411099013bSjsg /* read MC_STATUS */ 421099013bSjsg tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); 431099013bSjsg if (G_000090_MC_SYSTEM_IDLE(tmp)) 441099013bSjsg return 0; 451099013bSjsg udelay(1); 461099013bSjsg } 471099013bSjsg return -1; 481099013bSjsg } 491099013bSjsg 501099013bSjsg static void rs690_gpu_init(struct radeon_device *rdev) 511099013bSjsg { 521099013bSjsg /* FIXME: is this correct ? */ 531099013bSjsg r420_pipes_init(rdev); 541099013bSjsg if (rs690_mc_wait_for_idle(rdev)) { 551099013bSjsg DRM_ERROR("Failed to wait MC idle while " 561099013bSjsg "programming pipes. Bad things might happen.\n"); 571099013bSjsg } 581099013bSjsg } 591099013bSjsg 601099013bSjsg union igp_info { 611099013bSjsg struct _ATOM_INTEGRATED_SYSTEM_INFO info; 621099013bSjsg struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2; 631099013bSjsg }; 641099013bSjsg 651099013bSjsg void rs690_pm_info(struct radeon_device *rdev) 661099013bSjsg { 671099013bSjsg int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 681099013bSjsg union igp_info *info; 691099013bSjsg uint16_t data_offset; 701099013bSjsg uint8_t frev, crev; 711099013bSjsg fixed20_12 tmp; 721099013bSjsg 731099013bSjsg if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, 741099013bSjsg &frev, &crev, &data_offset)) { 751099013bSjsg info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); 761099013bSjsg 771099013bSjsg /* Get various system informations from bios */ 781099013bSjsg switch (crev) { 791099013bSjsg case 1: 801099013bSjsg tmp.full = dfixed_const(100); 811099013bSjsg rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); 821099013bSjsg rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 831099013bSjsg if (le16_to_cpu(info->info.usK8MemoryClock)) 841099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); 851099013bSjsg else if (rdev->clock.default_mclk) { 861099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 871099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 881099013bSjsg } else 891099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(400); 901099013bSjsg rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); 911099013bSjsg rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); 921099013bSjsg break; 931099013bSjsg case 2: 941099013bSjsg tmp.full = dfixed_const(100); 951099013bSjsg rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); 961099013bSjsg rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 971099013bSjsg if (le32_to_cpu(info->info_v2.ulBootUpUMAClock)) 981099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); 991099013bSjsg else if (rdev->clock.default_mclk) 1001099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 1011099013bSjsg else 1021099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(66700); 1031099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 1041099013bSjsg rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq)); 1051099013bSjsg rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); 1061099013bSjsg rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); 1071099013bSjsg break; 1081099013bSjsg default: 1091099013bSjsg /* We assume the slower possible clock ie worst case */ 1101099013bSjsg rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 1111099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(200); 1121099013bSjsg rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 1131099013bSjsg rdev->pm.igp_ht_link_width.full = dfixed_const(8); 1141099013bSjsg DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 1151099013bSjsg break; 1161099013bSjsg } 1171099013bSjsg } else { 1181099013bSjsg /* We assume the slower possible clock ie worst case */ 1191099013bSjsg rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 1201099013bSjsg rdev->pm.igp_system_mclk.full = dfixed_const(200); 1211099013bSjsg rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 1221099013bSjsg rdev->pm.igp_ht_link_width.full = dfixed_const(8); 1231099013bSjsg DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 1241099013bSjsg } 1251099013bSjsg /* Compute various bandwidth */ 1261099013bSjsg /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ 1271099013bSjsg tmp.full = dfixed_const(4); 1281099013bSjsg rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp); 1291099013bSjsg /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 1301099013bSjsg * = ht_clk * ht_width / 5 1311099013bSjsg */ 1321099013bSjsg tmp.full = dfixed_const(5); 1331099013bSjsg rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk, 1341099013bSjsg rdev->pm.igp_ht_link_width); 1351099013bSjsg rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp); 1361099013bSjsg if (tmp.full < rdev->pm.max_bandwidth.full) { 1371099013bSjsg /* HT link is a limiting factor */ 1381099013bSjsg rdev->pm.max_bandwidth.full = tmp.full; 1391099013bSjsg } 1401099013bSjsg /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 1411099013bSjsg * = (sideport_clk * 14) / 10 1421099013bSjsg */ 1431099013bSjsg tmp.full = dfixed_const(14); 1441099013bSjsg rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp); 1451099013bSjsg tmp.full = dfixed_const(10); 1461099013bSjsg rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp); 1471099013bSjsg } 1481099013bSjsg 1491099013bSjsg static void rs690_mc_init(struct radeon_device *rdev) 1501099013bSjsg { 1511099013bSjsg u64 base; 1521099013bSjsg 1531099013bSjsg rs400_gart_adjust_size(rdev); 1541099013bSjsg rdev->mc.vram_is_ddr = true; 1551099013bSjsg rdev->mc.vram_width = 128; 1561099013bSjsg rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 1571099013bSjsg rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 1581099013bSjsg rdev->mc.aper_base = rdev->fb_aper_offset; 1591099013bSjsg rdev->mc.aper_size = rdev->fb_aper_size; 1601099013bSjsg rdev->mc.visible_vram_size = rdev->mc.aper_size; 1611099013bSjsg base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 1621099013bSjsg base = G_000100_MC_FB_START(base) << 16; 1631099013bSjsg rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 164dc633288Sjsg /* Some boards seem to be configured for 128MB of sideport memory, 165dc633288Sjsg * but really only have 64MB. Just skip the sideport and use 166dc633288Sjsg * UMA memory. 167dc633288Sjsg */ 168dc633288Sjsg if (rdev->mc.igp_sideport_enabled && 169dc633288Sjsg (rdev->mc.real_vram_size == (384 * 1024 * 1024))) { 170dc633288Sjsg base += 128 * 1024 * 1024; 171dc633288Sjsg rdev->mc.real_vram_size -= 128 * 1024 * 1024; 172dc633288Sjsg rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 173dc633288Sjsg } 174dc633288Sjsg 1751099013bSjsg rs690_pm_info(rdev); 1761099013bSjsg radeon_vram_location(rdev, &rdev->mc, base); 1771099013bSjsg rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 1781099013bSjsg radeon_gtt_location(rdev, &rdev->mc); 1791099013bSjsg radeon_update_bandwidth_info(rdev); 1801099013bSjsg } 1811099013bSjsg 1821099013bSjsg void rs690_line_buffer_adjust(struct radeon_device *rdev, 1831099013bSjsg struct drm_display_mode *mode1, 1841099013bSjsg struct drm_display_mode *mode2) 1851099013bSjsg { 1861099013bSjsg u32 tmp; 1871099013bSjsg 1881099013bSjsg /* 1891099013bSjsg * Line Buffer Setup 1901099013bSjsg * There is a single line buffer shared by both display controllers. 1911099013bSjsg * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 1921099013bSjsg * the display controllers. The paritioning can either be done 1931099013bSjsg * manually or via one of four preset allocations specified in bits 1:0: 1941099013bSjsg * 0 - line buffer is divided in half and shared between crtc 1951099013bSjsg * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 1961099013bSjsg * 2 - D1 gets the whole buffer 1971099013bSjsg * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 1981099013bSjsg * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual 1991099013bSjsg * allocation mode. In manual allocation mode, D1 always starts at 0, 2001099013bSjsg * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. 2011099013bSjsg */ 2021099013bSjsg tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; 2031099013bSjsg tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE; 2041099013bSjsg /* auto */ 2051099013bSjsg if (mode1 && mode2) { 2061099013bSjsg if (mode1->hdisplay > mode2->hdisplay) { 2071099013bSjsg if (mode1->hdisplay > 2560) 2081099013bSjsg tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; 2091099013bSjsg else 2101099013bSjsg tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 2111099013bSjsg } else if (mode2->hdisplay > mode1->hdisplay) { 2121099013bSjsg if (mode2->hdisplay > 2560) 2131099013bSjsg tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 2141099013bSjsg else 2151099013bSjsg tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 2161099013bSjsg } else 2171099013bSjsg tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 2181099013bSjsg } else if (mode1) { 2191099013bSjsg tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY; 2201099013bSjsg } else if (mode2) { 2211099013bSjsg tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 2221099013bSjsg } 2231099013bSjsg WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); 2241099013bSjsg } 2251099013bSjsg 2261099013bSjsg struct rs690_watermark { 2271099013bSjsg u32 lb_request_fifo_depth; 2281099013bSjsg fixed20_12 num_line_pair; 2291099013bSjsg fixed20_12 estimated_width; 2301099013bSjsg fixed20_12 worst_case_latency; 2311099013bSjsg fixed20_12 consumption_rate; 2321099013bSjsg fixed20_12 active_time; 2331099013bSjsg fixed20_12 dbpp; 2341099013bSjsg fixed20_12 priority_mark_max; 2351099013bSjsg fixed20_12 priority_mark; 2361099013bSjsg fixed20_12 sclk; 2371099013bSjsg }; 2381099013bSjsg 2391099013bSjsg static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, 2401099013bSjsg struct radeon_crtc *crtc, 2411099013bSjsg struct rs690_watermark *wm) 2421099013bSjsg { 2431099013bSjsg struct drm_display_mode *mode = &crtc->base.mode; 2441099013bSjsg fixed20_12 a, b, c; 2451099013bSjsg fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 2461099013bSjsg fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 2471099013bSjsg 2481099013bSjsg if (!crtc->base.enabled) { 2491099013bSjsg /* FIXME: wouldn't it better to set priority mark to maximum */ 2501099013bSjsg wm->lb_request_fifo_depth = 4; 2511099013bSjsg return; 2521099013bSjsg } 2531099013bSjsg 2541099013bSjsg if (crtc->vsc.full > dfixed_const(2)) 2551099013bSjsg wm->num_line_pair.full = dfixed_const(2); 2561099013bSjsg else 2571099013bSjsg wm->num_line_pair.full = dfixed_const(1); 2581099013bSjsg 2591099013bSjsg b.full = dfixed_const(mode->crtc_hdisplay); 2601099013bSjsg c.full = dfixed_const(256); 2611099013bSjsg a.full = dfixed_div(b, c); 2621099013bSjsg request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 2631099013bSjsg request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 2641099013bSjsg if (a.full < dfixed_const(4)) { 2651099013bSjsg wm->lb_request_fifo_depth = 4; 2661099013bSjsg } else { 2671099013bSjsg wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 2681099013bSjsg } 2691099013bSjsg 2701099013bSjsg /* Determine consumption rate 2711099013bSjsg * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 2721099013bSjsg * vtaps = number of vertical taps, 2731099013bSjsg * vsc = vertical scaling ratio, defined as source/destination 2741099013bSjsg * hsc = horizontal scaling ration, defined as source/destination 2751099013bSjsg */ 2761099013bSjsg a.full = dfixed_const(mode->clock); 2771099013bSjsg b.full = dfixed_const(1000); 2781099013bSjsg a.full = dfixed_div(a, b); 2791099013bSjsg pclk.full = dfixed_div(b, a); 2801099013bSjsg if (crtc->rmx_type != RMX_OFF) { 2811099013bSjsg b.full = dfixed_const(2); 2821099013bSjsg if (crtc->vsc.full > b.full) 2831099013bSjsg b.full = crtc->vsc.full; 2841099013bSjsg b.full = dfixed_mul(b, crtc->hsc); 2851099013bSjsg c.full = dfixed_const(2); 2861099013bSjsg b.full = dfixed_div(b, c); 2871099013bSjsg consumption_time.full = dfixed_div(pclk, b); 2881099013bSjsg } else { 2891099013bSjsg consumption_time.full = pclk.full; 2901099013bSjsg } 2911099013bSjsg a.full = dfixed_const(1); 2921099013bSjsg wm->consumption_rate.full = dfixed_div(a, consumption_time); 2931099013bSjsg 2941099013bSjsg 2951099013bSjsg /* Determine line time 2961099013bSjsg * LineTime = total time for one line of displayhtotal 2971099013bSjsg * LineTime = total number of horizontal pixels 2981099013bSjsg * pclk = pixel clock period(ns) 2991099013bSjsg */ 3001099013bSjsg a.full = dfixed_const(crtc->base.mode.crtc_htotal); 3011099013bSjsg line_time.full = dfixed_mul(a, pclk); 3021099013bSjsg 3031099013bSjsg /* Determine active time 3041099013bSjsg * ActiveTime = time of active region of display within one line, 3051099013bSjsg * hactive = total number of horizontal active pixels 3061099013bSjsg * htotal = total number of horizontal pixels 3071099013bSjsg */ 3081099013bSjsg a.full = dfixed_const(crtc->base.mode.crtc_htotal); 3091099013bSjsg b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 3101099013bSjsg wm->active_time.full = dfixed_mul(line_time, b); 3111099013bSjsg wm->active_time.full = dfixed_div(wm->active_time, a); 3121099013bSjsg 3131099013bSjsg /* Maximun bandwidth is the minimun bandwidth of all component */ 3141099013bSjsg rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; 3151099013bSjsg if (rdev->mc.igp_sideport_enabled) { 3161099013bSjsg if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full && 3171099013bSjsg rdev->pm.sideport_bandwidth.full) 3181099013bSjsg rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; 3191099013bSjsg read_delay_latency.full = dfixed_const(370 * 800 * 1000); 3201099013bSjsg read_delay_latency.full = dfixed_div(read_delay_latency, 3211099013bSjsg rdev->pm.igp_sideport_mclk); 3221099013bSjsg } else { 3231099013bSjsg if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full && 3241099013bSjsg rdev->pm.k8_bandwidth.full) 3251099013bSjsg rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth; 3261099013bSjsg if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full && 3271099013bSjsg rdev->pm.ht_bandwidth.full) 3281099013bSjsg rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; 3291099013bSjsg read_delay_latency.full = dfixed_const(5000); 3301099013bSjsg } 3311099013bSjsg 3321099013bSjsg /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ 3331099013bSjsg a.full = dfixed_const(16); 3341099013bSjsg rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a); 3351099013bSjsg a.full = dfixed_const(1000); 3361099013bSjsg rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk); 3371099013bSjsg /* Determine chunk time 3381099013bSjsg * ChunkTime = the time it takes the DCP to send one chunk of data 3391099013bSjsg * to the LB which consists of pipeline delay and inter chunk gap 3401099013bSjsg * sclk = system clock(ns) 3411099013bSjsg */ 3421099013bSjsg a.full = dfixed_const(256 * 13); 3431099013bSjsg chunk_time.full = dfixed_mul(rdev->pm.sclk, a); 3441099013bSjsg a.full = dfixed_const(10); 3451099013bSjsg chunk_time.full = dfixed_div(chunk_time, a); 3461099013bSjsg 3471099013bSjsg /* Determine the worst case latency 3481099013bSjsg * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 3491099013bSjsg * WorstCaseLatency = worst case time from urgent to when the MC starts 3501099013bSjsg * to return data 3511099013bSjsg * READ_DELAY_IDLE_MAX = constant of 1us 3521099013bSjsg * ChunkTime = time it takes the DCP to send one chunk of data to the LB 3531099013bSjsg * which consists of pipeline delay and inter chunk gap 3541099013bSjsg */ 3551099013bSjsg if (dfixed_trunc(wm->num_line_pair) > 1) { 3561099013bSjsg a.full = dfixed_const(3); 3571099013bSjsg wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 3581099013bSjsg wm->worst_case_latency.full += read_delay_latency.full; 3591099013bSjsg } else { 3601099013bSjsg a.full = dfixed_const(2); 3611099013bSjsg wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 3621099013bSjsg wm->worst_case_latency.full += read_delay_latency.full; 3631099013bSjsg } 3641099013bSjsg 3651099013bSjsg /* Determine the tolerable latency 3661099013bSjsg * TolerableLatency = Any given request has only 1 line time 3671099013bSjsg * for the data to be returned 3681099013bSjsg * LBRequestFifoDepth = Number of chunk requests the LB can 3691099013bSjsg * put into the request FIFO for a display 3701099013bSjsg * LineTime = total time for one line of display 3711099013bSjsg * ChunkTime = the time it takes the DCP to send one chunk 3721099013bSjsg * of data to the LB which consists of 3731099013bSjsg * pipeline delay and inter chunk gap 3741099013bSjsg */ 3751099013bSjsg if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 3761099013bSjsg tolerable_latency.full = line_time.full; 3771099013bSjsg } else { 3781099013bSjsg tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 3791099013bSjsg tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 3801099013bSjsg tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 3811099013bSjsg tolerable_latency.full = line_time.full - tolerable_latency.full; 3821099013bSjsg } 3831099013bSjsg /* We assume worst case 32bits (4 bytes) */ 3841099013bSjsg wm->dbpp.full = dfixed_const(4 * 8); 3851099013bSjsg 3861099013bSjsg /* Determine the maximum priority mark 3871099013bSjsg * width = viewport width in pixels 3881099013bSjsg */ 3891099013bSjsg a.full = dfixed_const(16); 3901099013bSjsg wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 3911099013bSjsg wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 3921099013bSjsg wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 3931099013bSjsg 3941099013bSjsg /* Determine estimated width */ 3951099013bSjsg estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 3961099013bSjsg estimated_width.full = dfixed_div(estimated_width, consumption_time); 3971099013bSjsg if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 3981099013bSjsg wm->priority_mark.full = dfixed_const(10); 3991099013bSjsg } else { 4001099013bSjsg a.full = dfixed_const(16); 4011099013bSjsg wm->priority_mark.full = dfixed_div(estimated_width, a); 4021099013bSjsg wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 4031099013bSjsg wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 4041099013bSjsg } 4051099013bSjsg } 4061099013bSjsg 4071099013bSjsg void rs690_bandwidth_update(struct radeon_device *rdev) 4081099013bSjsg { 4091099013bSjsg struct drm_display_mode *mode0 = NULL; 4101099013bSjsg struct drm_display_mode *mode1 = NULL; 4111099013bSjsg struct rs690_watermark wm0; 4121099013bSjsg struct rs690_watermark wm1; 4131099013bSjsg u32 tmp; 4141099013bSjsg u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 4151099013bSjsg u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 4161099013bSjsg fixed20_12 priority_mark02, priority_mark12, fill_rate; 4171099013bSjsg fixed20_12 a, b; 4181099013bSjsg 4191099013bSjsg radeon_update_display_priority(rdev); 4201099013bSjsg 4211099013bSjsg if (rdev->mode_info.crtcs[0]->base.enabled) 4221099013bSjsg mode0 = &rdev->mode_info.crtcs[0]->base.mode; 4231099013bSjsg if (rdev->mode_info.crtcs[1]->base.enabled) 4241099013bSjsg mode1 = &rdev->mode_info.crtcs[1]->base.mode; 4251099013bSjsg /* 4261099013bSjsg * Set display0/1 priority up in the memory controller for 4271099013bSjsg * modes if the user specifies HIGH for displaypriority 4281099013bSjsg * option. 4291099013bSjsg */ 4301099013bSjsg if ((rdev->disp_priority == 2) && 4311099013bSjsg ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) { 4321099013bSjsg tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); 4331099013bSjsg tmp &= C_000104_MC_DISP0R_INIT_LAT; 4341099013bSjsg tmp &= C_000104_MC_DISP1R_INIT_LAT; 4351099013bSjsg if (mode0) 4361099013bSjsg tmp |= S_000104_MC_DISP0R_INIT_LAT(1); 4371099013bSjsg if (mode1) 4381099013bSjsg tmp |= S_000104_MC_DISP1R_INIT_LAT(1); 4391099013bSjsg WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); 4401099013bSjsg } 4411099013bSjsg rs690_line_buffer_adjust(rdev, mode0, mode1); 4421099013bSjsg 4431099013bSjsg if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) 4441099013bSjsg WREG32(R_006C9C_DCP_CONTROL, 0); 4451099013bSjsg if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 4461099013bSjsg WREG32(R_006C9C_DCP_CONTROL, 2); 4471099013bSjsg 4481099013bSjsg rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); 4491099013bSjsg rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); 4501099013bSjsg 4511099013bSjsg tmp = (wm0.lb_request_fifo_depth - 1); 4521099013bSjsg tmp |= (wm1.lb_request_fifo_depth - 1) << 16; 4531099013bSjsg WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); 4541099013bSjsg 4551099013bSjsg if (mode0 && mode1) { 4561099013bSjsg if (dfixed_trunc(wm0.dbpp) > 64) 4571099013bSjsg a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); 4581099013bSjsg else 4591099013bSjsg a.full = wm0.num_line_pair.full; 4601099013bSjsg if (dfixed_trunc(wm1.dbpp) > 64) 4611099013bSjsg b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); 4621099013bSjsg else 4631099013bSjsg b.full = wm1.num_line_pair.full; 4641099013bSjsg a.full += b.full; 4651099013bSjsg fill_rate.full = dfixed_div(wm0.sclk, a); 4661099013bSjsg if (wm0.consumption_rate.full > fill_rate.full) { 4671099013bSjsg b.full = wm0.consumption_rate.full - fill_rate.full; 4681099013bSjsg b.full = dfixed_mul(b, wm0.active_time); 4691099013bSjsg a.full = dfixed_mul(wm0.worst_case_latency, 4701099013bSjsg wm0.consumption_rate); 4711099013bSjsg a.full = a.full + b.full; 4721099013bSjsg b.full = dfixed_const(16 * 1000); 4731099013bSjsg priority_mark02.full = dfixed_div(a, b); 4741099013bSjsg } else { 4751099013bSjsg a.full = dfixed_mul(wm0.worst_case_latency, 4761099013bSjsg wm0.consumption_rate); 4771099013bSjsg b.full = dfixed_const(16 * 1000); 4781099013bSjsg priority_mark02.full = dfixed_div(a, b); 4791099013bSjsg } 4801099013bSjsg if (wm1.consumption_rate.full > fill_rate.full) { 4811099013bSjsg b.full = wm1.consumption_rate.full - fill_rate.full; 4821099013bSjsg b.full = dfixed_mul(b, wm1.active_time); 4831099013bSjsg a.full = dfixed_mul(wm1.worst_case_latency, 4841099013bSjsg wm1.consumption_rate); 4851099013bSjsg a.full = a.full + b.full; 4861099013bSjsg b.full = dfixed_const(16 * 1000); 4871099013bSjsg priority_mark12.full = dfixed_div(a, b); 4881099013bSjsg } else { 4891099013bSjsg a.full = dfixed_mul(wm1.worst_case_latency, 4901099013bSjsg wm1.consumption_rate); 4911099013bSjsg b.full = dfixed_const(16 * 1000); 4921099013bSjsg priority_mark12.full = dfixed_div(a, b); 4931099013bSjsg } 4941099013bSjsg if (wm0.priority_mark.full > priority_mark02.full) 4951099013bSjsg priority_mark02.full = wm0.priority_mark.full; 4961099013bSjsg if (dfixed_trunc(priority_mark02) < 0) 4971099013bSjsg priority_mark02.full = 0; 4981099013bSjsg if (wm0.priority_mark_max.full > priority_mark02.full) 4991099013bSjsg priority_mark02.full = wm0.priority_mark_max.full; 5001099013bSjsg if (wm1.priority_mark.full > priority_mark12.full) 5011099013bSjsg priority_mark12.full = wm1.priority_mark.full; 5021099013bSjsg if (dfixed_trunc(priority_mark12) < 0) 5031099013bSjsg priority_mark12.full = 0; 5041099013bSjsg if (wm1.priority_mark_max.full > priority_mark12.full) 5051099013bSjsg priority_mark12.full = wm1.priority_mark_max.full; 5061099013bSjsg d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 5071099013bSjsg d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 5081099013bSjsg if (rdev->disp_priority == 2) { 5091099013bSjsg d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 5101099013bSjsg d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 5111099013bSjsg } 5121099013bSjsg } else if (mode0) { 5131099013bSjsg if (dfixed_trunc(wm0.dbpp) > 64) 5141099013bSjsg a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); 5151099013bSjsg else 5161099013bSjsg a.full = wm0.num_line_pair.full; 5171099013bSjsg fill_rate.full = dfixed_div(wm0.sclk, a); 5181099013bSjsg if (wm0.consumption_rate.full > fill_rate.full) { 5191099013bSjsg b.full = wm0.consumption_rate.full - fill_rate.full; 5201099013bSjsg b.full = dfixed_mul(b, wm0.active_time); 5211099013bSjsg a.full = dfixed_mul(wm0.worst_case_latency, 5221099013bSjsg wm0.consumption_rate); 5231099013bSjsg a.full = a.full + b.full; 5241099013bSjsg b.full = dfixed_const(16 * 1000); 5251099013bSjsg priority_mark02.full = dfixed_div(a, b); 5261099013bSjsg } else { 5271099013bSjsg a.full = dfixed_mul(wm0.worst_case_latency, 5281099013bSjsg wm0.consumption_rate); 5291099013bSjsg b.full = dfixed_const(16 * 1000); 5301099013bSjsg priority_mark02.full = dfixed_div(a, b); 5311099013bSjsg } 5321099013bSjsg if (wm0.priority_mark.full > priority_mark02.full) 5331099013bSjsg priority_mark02.full = wm0.priority_mark.full; 5341099013bSjsg if (dfixed_trunc(priority_mark02) < 0) 5351099013bSjsg priority_mark02.full = 0; 5361099013bSjsg if (wm0.priority_mark_max.full > priority_mark02.full) 5371099013bSjsg priority_mark02.full = wm0.priority_mark_max.full; 5381099013bSjsg d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 5391099013bSjsg if (rdev->disp_priority == 2) 5401099013bSjsg d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 5411099013bSjsg } else if (mode1) { 5421099013bSjsg if (dfixed_trunc(wm1.dbpp) > 64) 5431099013bSjsg a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); 5441099013bSjsg else 5451099013bSjsg a.full = wm1.num_line_pair.full; 5461099013bSjsg fill_rate.full = dfixed_div(wm1.sclk, a); 5471099013bSjsg if (wm1.consumption_rate.full > fill_rate.full) { 5481099013bSjsg b.full = wm1.consumption_rate.full - fill_rate.full; 5491099013bSjsg b.full = dfixed_mul(b, wm1.active_time); 5501099013bSjsg a.full = dfixed_mul(wm1.worst_case_latency, 5511099013bSjsg wm1.consumption_rate); 5521099013bSjsg a.full = a.full + b.full; 5531099013bSjsg b.full = dfixed_const(16 * 1000); 5541099013bSjsg priority_mark12.full = dfixed_div(a, b); 5551099013bSjsg } else { 5561099013bSjsg a.full = dfixed_mul(wm1.worst_case_latency, 5571099013bSjsg wm1.consumption_rate); 5581099013bSjsg b.full = dfixed_const(16 * 1000); 5591099013bSjsg priority_mark12.full = dfixed_div(a, b); 5601099013bSjsg } 5611099013bSjsg if (wm1.priority_mark.full > priority_mark12.full) 5621099013bSjsg priority_mark12.full = wm1.priority_mark.full; 5631099013bSjsg if (dfixed_trunc(priority_mark12) < 0) 5641099013bSjsg priority_mark12.full = 0; 5651099013bSjsg if (wm1.priority_mark_max.full > priority_mark12.full) 5661099013bSjsg priority_mark12.full = wm1.priority_mark_max.full; 5671099013bSjsg d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 5681099013bSjsg if (rdev->disp_priority == 2) 5691099013bSjsg d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 5701099013bSjsg } 5711099013bSjsg 5721099013bSjsg WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 5731099013bSjsg WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 5741099013bSjsg WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 5751099013bSjsg WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 5761099013bSjsg } 5771099013bSjsg 5781099013bSjsg uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) 5791099013bSjsg { 5801099013bSjsg uint32_t r; 5811099013bSjsg 5821099013bSjsg WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); 5831099013bSjsg r = RREG32(R_00007C_MC_DATA); 5841099013bSjsg WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); 5851099013bSjsg return r; 5861099013bSjsg } 5871099013bSjsg 5881099013bSjsg void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 5891099013bSjsg { 5901099013bSjsg WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | 5911099013bSjsg S_000078_MC_IND_WR_EN(1)); 5921099013bSjsg WREG32(R_00007C_MC_DATA, v); 5931099013bSjsg WREG32(R_000078_MC_INDEX, 0x7F); 5941099013bSjsg } 5951099013bSjsg 5961099013bSjsg static void rs690_mc_program(struct radeon_device *rdev) 5971099013bSjsg { 5981099013bSjsg struct rv515_mc_save save; 5991099013bSjsg 6001099013bSjsg /* Stops all mc clients */ 6011099013bSjsg rv515_mc_stop(rdev, &save); 6021099013bSjsg 6031099013bSjsg /* Wait for mc idle */ 6041099013bSjsg if (rs690_mc_wait_for_idle(rdev)) 6051099013bSjsg dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 6061099013bSjsg /* Program MC, should be a 32bits limited address space */ 6071099013bSjsg WREG32_MC(R_000100_MCCFG_FB_LOCATION, 6081099013bSjsg S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | 6091099013bSjsg S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16)); 6101099013bSjsg WREG32(R_000134_HDP_FB_LOCATION, 6111099013bSjsg S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 6121099013bSjsg 6131099013bSjsg rv515_mc_resume(rdev, &save); 6141099013bSjsg } 6151099013bSjsg 6161099013bSjsg static int rs690_startup(struct radeon_device *rdev) 6171099013bSjsg { 6181099013bSjsg int r; 6191099013bSjsg 6201099013bSjsg rs690_mc_program(rdev); 6211099013bSjsg /* Resume clock */ 6221099013bSjsg rv515_clock_startup(rdev); 6231099013bSjsg /* Initialize GPU configuration (# pipes, ...) */ 6241099013bSjsg rs690_gpu_init(rdev); 6251099013bSjsg /* Initialize GART (initialize after TTM so we can allocate 6261099013bSjsg * memory through TTM but finalize after TTM) */ 6271099013bSjsg r = rs400_gart_enable(rdev); 6281099013bSjsg if (r) 6291099013bSjsg return r; 6301099013bSjsg 6311099013bSjsg /* allocate wb buffer */ 6321099013bSjsg r = radeon_wb_init(rdev); 6331099013bSjsg if (r) 6341099013bSjsg return r; 6351099013bSjsg 6361099013bSjsg r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 6371099013bSjsg if (r) { 6381099013bSjsg dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 6391099013bSjsg return r; 6401099013bSjsg } 6411099013bSjsg 6421099013bSjsg /* Enable IRQ */ 643*55fe5614Sjsg if (!rdev->irq.installed) { 644*55fe5614Sjsg r = radeon_irq_kms_init(rdev); 645*55fe5614Sjsg if (r) 646*55fe5614Sjsg return r; 647*55fe5614Sjsg } 648*55fe5614Sjsg 6491099013bSjsg rs600_irq_set(rdev); 6501099013bSjsg rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 6511099013bSjsg /* 1M ring buffer */ 6521099013bSjsg r = r100_cp_init(rdev, 1024 * 1024); 6531099013bSjsg if (r) { 6541099013bSjsg dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 6551099013bSjsg return r; 6561099013bSjsg } 6571099013bSjsg 6581099013bSjsg r = radeon_ib_pool_init(rdev); 6591099013bSjsg if (r) { 6601099013bSjsg dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 6611099013bSjsg return r; 6621099013bSjsg } 6631099013bSjsg 6641099013bSjsg r = r600_audio_init(rdev); 6651099013bSjsg if (r) { 6661099013bSjsg dev_err(rdev->dev, "failed initializing audio\n"); 6671099013bSjsg return r; 6681099013bSjsg } 6691099013bSjsg 6701099013bSjsg return 0; 6711099013bSjsg } 6721099013bSjsg 6731099013bSjsg int rs690_resume(struct radeon_device *rdev) 6741099013bSjsg { 6751099013bSjsg int r; 6761099013bSjsg 6771099013bSjsg /* Make sur GART are not working */ 6781099013bSjsg rs400_gart_disable(rdev); 6791099013bSjsg /* Resume clock before doing reset */ 6801099013bSjsg rv515_clock_startup(rdev); 6811099013bSjsg /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 6821099013bSjsg if (radeon_asic_reset(rdev)) { 6831099013bSjsg dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 6841099013bSjsg RREG32(R_000E40_RBBM_STATUS), 6851099013bSjsg RREG32(R_0007C0_CP_STAT)); 6861099013bSjsg } 6871099013bSjsg /* post */ 6881099013bSjsg atom_asic_init(rdev->mode_info.atom_context); 6891099013bSjsg /* Resume clock after posting */ 6901099013bSjsg rv515_clock_startup(rdev); 6911099013bSjsg /* Initialize surface registers */ 6921099013bSjsg radeon_surface_init(rdev); 6931099013bSjsg 6941099013bSjsg rdev->accel_working = true; 6951099013bSjsg r = rs690_startup(rdev); 6961099013bSjsg if (r) { 6971099013bSjsg rdev->accel_working = false; 6981099013bSjsg } 6991099013bSjsg return r; 7001099013bSjsg } 7011099013bSjsg 7021099013bSjsg int rs690_suspend(struct radeon_device *rdev) 7031099013bSjsg { 7041099013bSjsg r600_audio_fini(rdev); 7051099013bSjsg r100_cp_disable(rdev); 7061099013bSjsg radeon_wb_disable(rdev); 7071099013bSjsg rs600_irq_disable(rdev); 7081099013bSjsg rs400_gart_disable(rdev); 7091099013bSjsg return 0; 7101099013bSjsg } 7111099013bSjsg 7121099013bSjsg void rs690_fini(struct radeon_device *rdev) 7131099013bSjsg { 7141099013bSjsg r600_audio_fini(rdev); 7151099013bSjsg r100_cp_fini(rdev); 7161099013bSjsg radeon_wb_fini(rdev); 7171099013bSjsg radeon_ib_pool_fini(rdev); 7181099013bSjsg radeon_gem_fini(rdev); 7191099013bSjsg rs400_gart_fini(rdev); 7201099013bSjsg radeon_irq_kms_fini(rdev); 7211099013bSjsg radeon_fence_driver_fini(rdev); 7221099013bSjsg radeon_bo_fini(rdev); 7231099013bSjsg radeon_atombios_fini(rdev); 724de5631a0Sjsg kfree(rdev->bios); 7251099013bSjsg rdev->bios = NULL; 7261099013bSjsg } 7271099013bSjsg 7281099013bSjsg int rs690_init(struct radeon_device *rdev) 7291099013bSjsg { 7301099013bSjsg int r; 7311099013bSjsg 7321099013bSjsg /* Disable VGA */ 7331099013bSjsg rv515_vga_render_disable(rdev); 7341099013bSjsg /* Initialize scratch registers */ 7351099013bSjsg radeon_scratch_init(rdev); 7361099013bSjsg /* Initialize surface registers */ 7371099013bSjsg radeon_surface_init(rdev); 7381099013bSjsg /* restore some register to sane defaults */ 7391099013bSjsg r100_restore_sanity(rdev); 7401099013bSjsg /* TODO: disable VGA need to use VGA request */ 7411099013bSjsg /* BIOS*/ 7421099013bSjsg if (!radeon_get_bios(rdev)) { 7431099013bSjsg if (ASIC_IS_AVIVO(rdev)) 7441099013bSjsg return -EINVAL; 7451099013bSjsg } 7461099013bSjsg if (rdev->is_atom_bios) { 7471099013bSjsg r = radeon_atombios_init(rdev); 7481099013bSjsg if (r) 7491099013bSjsg return r; 7501099013bSjsg } else { 7511099013bSjsg dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 7521099013bSjsg return -EINVAL; 7531099013bSjsg } 7541099013bSjsg /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 7551099013bSjsg if (radeon_asic_reset(rdev)) { 7561099013bSjsg dev_warn(rdev->dev, 7571099013bSjsg "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 7581099013bSjsg RREG32(R_000E40_RBBM_STATUS), 7591099013bSjsg RREG32(R_0007C0_CP_STAT)); 7601099013bSjsg } 7611099013bSjsg /* check if cards are posted or not */ 7621099013bSjsg if (radeon_boot_test_post_card(rdev) == false) 7631099013bSjsg return -EINVAL; 7641099013bSjsg 7651099013bSjsg /* Initialize clocks */ 7661099013bSjsg radeon_get_clock_info(rdev->ddev); 7671099013bSjsg /* initialize memory controller */ 7681099013bSjsg rs690_mc_init(rdev); 7691099013bSjsg rv515_debugfs(rdev); 7701099013bSjsg /* Fence driver */ 7711099013bSjsg r = radeon_fence_driver_init(rdev); 7721099013bSjsg if (r) 7731099013bSjsg return r; 7741099013bSjsg /* Memory manager */ 7751099013bSjsg r = radeon_bo_init(rdev); 7761099013bSjsg if (r) 7771099013bSjsg return r; 7781099013bSjsg r = rs400_gart_init(rdev); 7791099013bSjsg if (r) 7801099013bSjsg return r; 7811099013bSjsg rs600_set_safe_registers(rdev); 7821099013bSjsg 7831099013bSjsg rdev->accel_working = true; 7841099013bSjsg r = rs690_startup(rdev); 7851099013bSjsg if (r) { 7861099013bSjsg /* Somethings want wront with the accel init stop accel */ 7871099013bSjsg dev_err(rdev->dev, "Disabling GPU acceleration\n"); 7881099013bSjsg r100_cp_fini(rdev); 7891099013bSjsg radeon_wb_fini(rdev); 7901099013bSjsg radeon_ib_pool_fini(rdev); 7911099013bSjsg rs400_gart_fini(rdev); 7921099013bSjsg radeon_irq_kms_fini(rdev); 7931099013bSjsg rdev->accel_working = false; 7941099013bSjsg } 7951099013bSjsg return 0; 7961099013bSjsg } 797