1*7ccd5a2cSjsg /* 2*7ccd5a2cSjsg * Copyright 2011 Advanced Micro Devices, Inc. 3*7ccd5a2cSjsg * 4*7ccd5a2cSjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*7ccd5a2cSjsg * copy of this software and associated documentation files (the "Software"), 6*7ccd5a2cSjsg * to deal in the Software without restriction, including without limitation 7*7ccd5a2cSjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*7ccd5a2cSjsg * and/or sell copies of the Software, and to permit persons to whom the 9*7ccd5a2cSjsg * Software is furnished to do so, subject to the following conditions: 10*7ccd5a2cSjsg * 11*7ccd5a2cSjsg * The above copyright notice and this permission notice shall be included in 12*7ccd5a2cSjsg * all copies or substantial portions of the Software. 13*7ccd5a2cSjsg * 14*7ccd5a2cSjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*7ccd5a2cSjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*7ccd5a2cSjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*7ccd5a2cSjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*7ccd5a2cSjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*7ccd5a2cSjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*7ccd5a2cSjsg * OTHER DEALINGS IN THE SOFTWARE. 21*7ccd5a2cSjsg * 22*7ccd5a2cSjsg * Authors: Alex Deucher 23*7ccd5a2cSjsg */ 24*7ccd5a2cSjsg 25*7ccd5a2cSjsg #ifndef __RV6XX_DPM_H__ 26*7ccd5a2cSjsg #define __RV6XX_DPM_H__ 27*7ccd5a2cSjsg 28*7ccd5a2cSjsg #include "r600_dpm.h" 29*7ccd5a2cSjsg 30*7ccd5a2cSjsg /* Represents a single SCLK step. */ 31*7ccd5a2cSjsg struct rv6xx_sclk_stepping 32*7ccd5a2cSjsg { 33*7ccd5a2cSjsg u32 vco_frequency; 34*7ccd5a2cSjsg u32 post_divider; 35*7ccd5a2cSjsg }; 36*7ccd5a2cSjsg 37*7ccd5a2cSjsg struct rv6xx_pm_hw_state { 38*7ccd5a2cSjsg u32 sclks[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; 39*7ccd5a2cSjsg u32 mclks[R600_PM_NUMBER_OF_MCLKS]; 40*7ccd5a2cSjsg u16 vddc[R600_PM_NUMBER_OF_VOLTAGE_LEVELS]; 41*7ccd5a2cSjsg bool backbias[R600_PM_NUMBER_OF_VOLTAGE_LEVELS]; 42*7ccd5a2cSjsg bool pcie_gen2[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; 43*7ccd5a2cSjsg u8 high_sclk_index; 44*7ccd5a2cSjsg u8 medium_sclk_index; 45*7ccd5a2cSjsg u8 low_sclk_index; 46*7ccd5a2cSjsg u8 high_mclk_index; 47*7ccd5a2cSjsg u8 medium_mclk_index; 48*7ccd5a2cSjsg u8 low_mclk_index; 49*7ccd5a2cSjsg u8 high_vddc_index; 50*7ccd5a2cSjsg u8 medium_vddc_index; 51*7ccd5a2cSjsg u8 low_vddc_index; 52*7ccd5a2cSjsg u8 rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; 53*7ccd5a2cSjsg u8 lp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; 54*7ccd5a2cSjsg }; 55*7ccd5a2cSjsg 56*7ccd5a2cSjsg struct rv6xx_power_info { 57*7ccd5a2cSjsg /* flags */ 58*7ccd5a2cSjsg bool voltage_control; 59*7ccd5a2cSjsg bool sclk_ss; 60*7ccd5a2cSjsg bool mclk_ss; 61*7ccd5a2cSjsg bool dynamic_ss; 62*7ccd5a2cSjsg bool dynamic_pcie_gen2; 63*7ccd5a2cSjsg bool thermal_protection; 64*7ccd5a2cSjsg bool display_gap; 65*7ccd5a2cSjsg bool gfx_clock_gating; 66*7ccd5a2cSjsg /* clk values */ 67*7ccd5a2cSjsg u32 fb_div_scale; 68*7ccd5a2cSjsg u32 spll_ref_div; 69*7ccd5a2cSjsg u32 mpll_ref_div; 70*7ccd5a2cSjsg u32 bsu; 71*7ccd5a2cSjsg u32 bsp; 72*7ccd5a2cSjsg /* */ 73*7ccd5a2cSjsg u32 active_auto_throttle_sources; 74*7ccd5a2cSjsg /* current power state */ 75*7ccd5a2cSjsg u32 restricted_levels; 76*7ccd5a2cSjsg struct rv6xx_pm_hw_state hw; 77*7ccd5a2cSjsg }; 78*7ccd5a2cSjsg 79*7ccd5a2cSjsg struct rv6xx_pl { 80*7ccd5a2cSjsg u32 sclk; 81*7ccd5a2cSjsg u32 mclk; 82*7ccd5a2cSjsg u16 vddc; 83*7ccd5a2cSjsg u32 flags; 84*7ccd5a2cSjsg }; 85*7ccd5a2cSjsg 86*7ccd5a2cSjsg struct rv6xx_ps { 87*7ccd5a2cSjsg struct rv6xx_pl high; 88*7ccd5a2cSjsg struct rv6xx_pl medium; 89*7ccd5a2cSjsg struct rv6xx_pl low; 90*7ccd5a2cSjsg }; 91*7ccd5a2cSjsg 92*7ccd5a2cSjsg #define RV6XX_DEFAULT_VCLK_FREQ 40000 /* 10 khz */ 93*7ccd5a2cSjsg #define RV6XX_DEFAULT_DCLK_FREQ 30000 /* 10 khz */ 94*7ccd5a2cSjsg 95*7ccd5a2cSjsg #endif 96