1 /* $OpenBSD: gdt_pci.c,v 1.22 2009/03/29 21:53:52 sthen Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * This driver would not have written if it was not for the hardware donations 29 * from both ICP-Vortex and �ko.neT. I want to thank them for their support. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/queue.h> 38 39 #include <machine/bus.h> 40 #include <machine/endian.h> 41 #include <machine/intr.h> 42 43 #include <scsi/scsi_all.h> 44 #include <scsi/scsiconf.h> 45 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 50 #include <dev/ic/gdtreg.h> 51 #include <dev/ic/gdtvar.h> 52 53 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 54 #define GDT_PCI_PRODUCT_FC 0x200 55 56 #define GDT_DEVICE_ID_MIN 0x100 57 #define GDT_DEVICE_ID_MAX 0x2ff 58 #define GDT_DEVICE_ID_NEWRX 0x300 59 #define GDT_DEVICE_ID_NEWRX2 0x301 60 61 /* Mapping registers for various areas */ 62 #define GDT_PCI_DPMEM 0x10 63 #define GDT_PCINEW_IOMEM 0x10 64 #define GDT_PCINEW_IO 0x14 65 #define GDT_PCINEW_DPMEM 0x18 66 67 /* PCI SRAM structure */ 68 #define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 69 #define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 70 #define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */ 71 #define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 72 #define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 73 #define GDT_SRAM_SZ 0x40 74 75 /* DPRAM PCI controllers */ 76 #define GDT_DPR_IF 0x00 /* interface area */ 77 #define GDT_6SR (0xff0 - GDT_SRAM_SZ) 78 #define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 79 #define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 80 #define GDT_EVENT 0xff8 /* u_int8_t, release event */ 81 #define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 82 #define GDT_DPRAM_SZ 0x1000 83 84 /* PLX register structure (new PCI controllers) */ 85 #define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 86 #define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 87 #define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 88 #define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 89 #define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */ 90 #define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 91 #define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 92 #define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 93 #define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 94 #define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 95 #define GDT_PLX_SZ 0x80 96 97 /* DPRAM new PCI controllers */ 98 #define GDT_IC 0x00 /* interface */ 99 #define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ) 100 /* SRAM structure */ 101 #define GDT_PCINEW_SZ 0x4000 102 103 /* i960 register structure (PCI MPR controllers) */ 104 #define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 105 #define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 106 #define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 107 #define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */ 108 #define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 109 #define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 110 #define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 111 #define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 112 #define GDT_I960_SZ 0x1000 113 114 /* DPRAM PCI MPR controllers */ 115 #define GDT_I960R 0x00 /* 4KB i960 registers */ 116 #define GDT_MPR_IC GDT_I960_SZ 117 /* interface area */ 118 #define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ) 119 /* SRAM structure */ 120 #define GDT_MPR_SZ 0x4000 121 122 int gdt_pci_probe(struct device *, void *, void *); 123 void gdt_pci_attach(struct device *, struct device *, void *); 124 void gdt_pci_enable_intr(struct gdt_softc *); 125 126 void gdt_pci_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 127 u_int8_t gdt_pci_get_status(struct gdt_softc *); 128 void gdt_pci_intr(struct gdt_softc *, struct gdt_intr_ctx *); 129 void gdt_pci_release_event(struct gdt_softc *, struct gdt_ccb *); 130 void gdt_pci_set_sema0(struct gdt_softc *); 131 int gdt_pci_test_busy(struct gdt_softc *); 132 133 void gdt_pcinew_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 134 u_int8_t gdt_pcinew_get_status(struct gdt_softc *); 135 void gdt_pcinew_intr(struct gdt_softc *, struct gdt_intr_ctx *); 136 void gdt_pcinew_release_event(struct gdt_softc *, struct gdt_ccb *); 137 void gdt_pcinew_set_sema0(struct gdt_softc *); 138 int gdt_pcinew_test_busy(struct gdt_softc *); 139 140 void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 141 u_int8_t gdt_mpr_get_status(struct gdt_softc *); 142 void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *); 143 void gdt_mpr_release_event(struct gdt_softc *, struct gdt_ccb *); 144 void gdt_mpr_set_sema0(struct gdt_softc *); 145 int gdt_mpr_test_busy(struct gdt_softc *); 146 147 struct cfattach gdt_pci_ca = { 148 sizeof (struct gdt_softc), gdt_pci_probe, gdt_pci_attach 149 }; 150 151 int 152 gdt_pci_probe(struct device *parent, void *match, void *aux) 153 { 154 struct pci_attach_args *pa = aux; 155 156 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX && 157 ((PCI_PRODUCT(pa->pa_id) >= GDT_DEVICE_ID_MIN && 158 PCI_PRODUCT(pa->pa_id) <= GDT_DEVICE_ID_MAX) || 159 PCI_PRODUCT(pa->pa_id) == GDT_DEVICE_ID_NEWRX || 160 PCI_PRODUCT(pa->pa_id) == GDT_DEVICE_ID_NEWRX2)) 161 return (1); 162 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 163 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GDT_RAID1 || 164 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GDT_RAID2)) 165 return (1); 166 return (0); 167 } 168 169 void 170 gdt_pci_attach(struct device *parent, struct device *self, void *aux) 171 { 172 struct pci_attach_args *pa = aux; 173 struct gdt_softc *sc = (void *)self; 174 bus_space_tag_t dpmemt, iomemt, iot; 175 bus_space_handle_t dpmemh, iomemh, ioh; 176 bus_addr_t dpmembase, iomembase, iobase; 177 bus_size_t dpmemsize, iomemsize, iosize; 178 u_int16_t prod; 179 u_int32_t status = 0; 180 #define DPMEM_MAPPED 1 181 #define IOMEM_MAPPED 2 182 #define IO_MAPPED 4 183 #define INTR_ESTABLISHED 8 184 int retries; 185 u_int8_t protocol; 186 pci_intr_handle_t ih; 187 const char *intrstr; 188 189 printf(": "); 190 191 sc->sc_class = 0; 192 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX) { 193 prod = PCI_PRODUCT(pa->pa_id); 194 switch (prod) { 195 case PCI_PRODUCT_VORTEX_GDT_60x0: 196 case PCI_PRODUCT_VORTEX_GDT_6000B: 197 sc->sc_class = GDT_PCI; 198 break; 199 200 case PCI_PRODUCT_VORTEX_GDT_6x10: 201 case PCI_PRODUCT_VORTEX_GDT_6x20: 202 case PCI_PRODUCT_VORTEX_GDT_6530: 203 case PCI_PRODUCT_VORTEX_GDT_6550: 204 case PCI_PRODUCT_VORTEX_GDT_6x17: 205 case PCI_PRODUCT_VORTEX_GDT_6x27: 206 case PCI_PRODUCT_VORTEX_GDT_6537: 207 case PCI_PRODUCT_VORTEX_GDT_6557: 208 case PCI_PRODUCT_VORTEX_GDT_6x15: 209 case PCI_PRODUCT_VORTEX_GDT_6x25: 210 case PCI_PRODUCT_VORTEX_GDT_6535: 211 case PCI_PRODUCT_VORTEX_GDT_6555: 212 sc->sc_class = GDT_PCINEW; 213 break; 214 215 case PCI_PRODUCT_VORTEX_GDT_6x17RP: 216 case PCI_PRODUCT_VORTEX_GDT_6x27RP: 217 case PCI_PRODUCT_VORTEX_GDT_6537RP: 218 case PCI_PRODUCT_VORTEX_GDT_6557RP: 219 case PCI_PRODUCT_VORTEX_GDT_6x11RP: 220 case PCI_PRODUCT_VORTEX_GDT_6x21RP: 221 case PCI_PRODUCT_VORTEX_GDT_6x17RD: 222 case PCI_PRODUCT_VORTEX_GDT_6x27RD: 223 case PCI_PRODUCT_VORTEX_GDT_6537RD: 224 case PCI_PRODUCT_VORTEX_GDT_6557RD: 225 case PCI_PRODUCT_VORTEX_GDT_6x11RD: 226 case PCI_PRODUCT_VORTEX_GDT_6x21RD: 227 case PCI_PRODUCT_VORTEX_GDT_6x18RD: 228 case PCI_PRODUCT_VORTEX_GDT_6x28RD: 229 case PCI_PRODUCT_VORTEX_GDT_6x38RD: 230 case PCI_PRODUCT_VORTEX_GDT_6x58RD: 231 case PCI_PRODUCT_VORTEX_GDT_6518RS: 232 case PCI_PRODUCT_VORTEX_GDT_7x18RN: 233 case PCI_PRODUCT_VORTEX_GDT_7x28RN: 234 case PCI_PRODUCT_VORTEX_GDT_7x38RN: 235 case PCI_PRODUCT_VORTEX_GDT_7x58RN: 236 case PCI_PRODUCT_VORTEX_GDT_6x19RD: 237 case PCI_PRODUCT_VORTEX_GDT_6x29RD: 238 case PCI_PRODUCT_VORTEX_GDT_7x19RN: 239 case PCI_PRODUCT_VORTEX_GDT_7x29RN: 240 case PCI_PRODUCT_VORTEX_GDT_7x43RN: 241 sc->sc_class = GDT_MPR; 242 } 243 244 /* If we don't recognize it, determine class heuristically. */ 245 if (sc->sc_class == 0) 246 sc->sc_class = prod < 0x100 ? GDT_PCINEW : GDT_MPR; 247 248 if (prod >= GDT_PCI_PRODUCT_FC) 249 sc->sc_class |= GDT_FC; 250 251 } else if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 252 sc->sc_class = GDT_MPR; 253 } 254 255 if (pci_mapreg_map(pa, 256 GDT_CLASS(sc) == GDT_PCINEW ? GDT_PCINEW_DPMEM : GDT_PCI_DPMEM, 257 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &dpmemt, 258 &dpmemh, &dpmembase, &dpmemsize, 0)) { 259 if (pci_mapreg_map(pa, 260 GDT_CLASS(sc) == GDT_PCINEW ? GDT_PCINEW_DPMEM : 261 GDT_PCI_DPMEM, 262 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M, 0, 263 &dpmemt,&dpmemh, &dpmembase, &dpmemsize, 0)) { 264 printf("cannot map DPMEM\n"); 265 goto bail_out; 266 } 267 } 268 status |= DPMEM_MAPPED; 269 sc->sc_dpmemt = dpmemt; 270 sc->sc_dpmemh = dpmemh; 271 sc->sc_dpmembase = dpmembase; 272 sc->sc_dmat = pa->pa_dmat; 273 274 /* 275 * The GDT_PCINEW series also has two other regions to map. 276 */ 277 if (GDT_CLASS(sc) == GDT_PCINEW) { 278 if (pci_mapreg_map(pa, GDT_PCINEW_IOMEM, PCI_MAPREG_TYPE_MEM, 279 0, &iomemt, &iomemh, &iomembase, &iomemsize, 0)) { 280 printf("can't map memory mapped i/o ports\n"); 281 goto bail_out; 282 } 283 status |= IOMEM_MAPPED; 284 285 if (pci_mapreg_map(pa, GDT_PCINEW_IO, PCI_MAPREG_TYPE_IO, 0, 286 &iot, &ioh, &iobase, &iosize, 0)) { 287 printf("can't map i/o space\n"); 288 goto bail_out; 289 } 290 status |= IO_MAPPED; 291 sc->sc_iot = iot; 292 sc->sc_ioh = ioh; 293 sc->sc_iobase = iobase; 294 } 295 296 switch (GDT_CLASS(sc)) { 297 case GDT_PCI: 298 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 299 GDT_DPR_IF_SZ >> 2); 300 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 301 printf("can't write to DPMEM\n"); 302 goto bail_out; 303 } 304 305 #if 0 306 /* disable board interrupts, deinit services */ 307 gdth_writeb(0xff, &dp6_ptr->io.irqdel); 308 gdth_writeb(0x00, &dp6_ptr->io.irqen); 309 gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status); 310 gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index); 311 312 gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]); 313 gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx); 314 gdth_writeb(0, &dp6_ptr->io.event); 315 retries = INIT_RETRIES; 316 gdth_delay(20); 317 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) { 318 if (--retries == 0) { 319 printk("initialization error (DEINIT failed)\n"); 320 gdth_munmap(ha->brd); 321 return 0; 322 } 323 gdth_delay(1); 324 } 325 prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]); 326 gdth_writeb(0, &dp6_ptr->u.ic.S_Status); 327 gdth_writeb(0xff, &dp6_ptr->io.irqdel); 328 if (prot_ver != PROTOCOL_VERSION) { 329 printk("illegal protocol version\n"); 330 gdth_munmap(ha->brd); 331 return 0; 332 } 333 334 ha->type = GDT_PCI; 335 ha->ic_all_size = sizeof(dp6_ptr->u); 336 337 /* special command to controller BIOS */ 338 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]); 339 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]); 340 gdth_writel(0x01, &dp6_ptr->u.ic.S_Info[2]); 341 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]); 342 gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx); 343 gdth_writeb(0, &dp6_ptr->io.event); 344 retries = INIT_RETRIES; 345 gdth_delay(20); 346 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) { 347 if (--retries == 0) { 348 printk("initialization error\n"); 349 gdth_munmap(ha->brd); 350 return 0; 351 } 352 gdth_delay(1); 353 } 354 gdth_writeb(0, &dp6_ptr->u.ic.S_Status); 355 gdth_writeb(0xff, &dp6_ptr->io.irqdel); 356 #endif 357 358 sc->sc_ic_all_size = GDT_DPRAM_SZ; 359 360 sc->sc_copy_cmd = gdt_pci_copy_cmd; 361 sc->sc_get_status = gdt_pci_get_status; 362 sc->sc_intr = gdt_pci_intr; 363 sc->sc_release_event = gdt_pci_release_event; 364 sc->sc_set_sema0 = gdt_pci_set_sema0; 365 sc->sc_test_busy = gdt_pci_test_busy; 366 367 break; 368 369 case GDT_PCINEW: 370 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 371 GDT_DPR_IF_SZ >> 2); 372 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 373 printf("cannot write to DPMEM\n"); 374 goto bail_out; 375 } 376 377 #if 0 378 /* disable board interrupts, deinit services */ 379 outb(0x00,PTR2USHORT(&ha->plx->control1)); 380 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg)); 381 382 gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status); 383 gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index); 384 385 gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]); 386 gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx); 387 388 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 389 390 retries = INIT_RETRIES; 391 gdth_delay(20); 392 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) { 393 if (--retries == 0) { 394 printk("initialization error (DEINIT failed)\n"); 395 gdth_munmap(ha->brd); 396 return 0; 397 } 398 gdth_delay(1); 399 } 400 prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]); 401 gdth_writeb(0, &dp6c_ptr->u.ic.Status); 402 if (prot_ver != PROTOCOL_VERSION) { 403 printk("illegal protocol version\n"); 404 gdth_munmap(ha->brd); 405 return 0; 406 } 407 408 ha->type = GDT_PCINEW; 409 ha->ic_all_size = sizeof(dp6c_ptr->u); 410 411 /* special command to controller BIOS */ 412 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]); 413 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]); 414 gdth_writel(0x01, &dp6c_ptr->u.ic.S_Info[2]); 415 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]); 416 gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx); 417 418 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 419 420 retries = INIT_RETRIES; 421 gdth_delay(20); 422 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) { 423 if (--retries == 0) { 424 printk("initialization error\n"); 425 gdth_munmap(ha->brd); 426 return 0; 427 } 428 gdth_delay(1); 429 } 430 gdth_writeb(0, &dp6c_ptr->u.ic.S_Status); 431 #endif 432 433 sc->sc_ic_all_size = GDT_PCINEW_SZ; 434 435 sc->sc_copy_cmd = gdt_pcinew_copy_cmd; 436 sc->sc_get_status = gdt_pcinew_get_status; 437 sc->sc_intr = gdt_pcinew_intr; 438 sc->sc_release_event = gdt_pcinew_release_event; 439 sc->sc_set_sema0 = gdt_pcinew_set_sema0; 440 sc->sc_test_busy = gdt_pcinew_test_busy; 441 442 break; 443 444 case GDT_MPR: 445 bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC, GDT_MPR_MAGIC); 446 if (bus_space_read_4(dpmemt, dpmemh, GDT_MPR_IC) != 447 GDT_MPR_MAGIC) { 448 printf("cannot access DPMEM at 0x%x (shadowed?)\n", 449 dpmembase); 450 goto bail_out; 451 } 452 453 /* 454 * XXX Here the Linux driver has a weird remapping logic I 455 * don't understand. My controller does not need it, and I 456 * cannot see what purpose it serves, therefore I did not 457 * do anything similar. 458 */ 459 460 bus_space_set_region_4(dpmemt, dpmemh, GDT_I960_SZ, 0, 461 GDT_DPR_IF_SZ >> 2); 462 463 /* Disable everything */ 464 bus_space_write_1(dpmemt, dpmemh, GDT_EDOOR_EN, 465 bus_space_read_1(dpmemt, dpmemh, GDT_EDOOR_EN) | 4); 466 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_EDOOR, 0xff); 467 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS, 468 0); 469 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_CMD_INDEX, 470 0); 471 472 bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_INFO, 473 dpmembase); 474 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 475 0xff); 476 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_LDOOR, 1); 477 478 DELAY(20); 479 retries = GDT_RETRIES; 480 while (bus_space_read_1(dpmemt, dpmemh, 481 GDT_MPR_IC + GDT_S_STATUS) != 0xff) { 482 if (--retries == 0) { 483 printf("DEINIT failed (status 0x%x)\n", 484 bus_space_read_1(dpmemt, dpmemh, 485 GDT_MPR_IC + GDT_S_STATUS)); 486 goto bail_out; 487 } 488 DELAY(1); 489 } 490 491 protocol = (u_int8_t)bus_space_read_4(dpmemt, dpmemh, 492 GDT_MPR_IC + GDT_S_INFO); 493 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS, 494 0); 495 if (protocol != GDT_PROTOCOL_VERSION) { 496 printf("unsupported protocol %d\n", protocol); 497 goto bail_out; 498 } 499 500 /* special commnd to controller BIOS */ 501 bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_INFO, 0); 502 bus_space_write_4(dpmemt, dpmemh, 503 GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), 0); 504 bus_space_write_4(dpmemt, dpmemh, 505 GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t), 1); 506 bus_space_write_4(dpmemt, dpmemh, 507 GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t), 0); 508 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 509 0xfe); 510 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_LDOOR, 1); 511 512 DELAY(20); 513 retries = GDT_RETRIES; 514 while (bus_space_read_1(dpmemt, dpmemh, 515 GDT_MPR_IC + GDT_S_STATUS) != 0xfe) { 516 if (--retries == 0) { 517 printf("initialization error\n"); 518 goto bail_out; 519 } 520 DELAY(1); 521 } 522 523 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS, 524 0); 525 526 sc->sc_ic_all_size = GDT_MPR_SZ; 527 528 sc->sc_copy_cmd = gdt_mpr_copy_cmd; 529 sc->sc_get_status = gdt_mpr_get_status; 530 sc->sc_intr = gdt_mpr_intr; 531 sc->sc_release_event = gdt_mpr_release_event; 532 sc->sc_set_sema0 = gdt_mpr_set_sema0; 533 sc->sc_test_busy = gdt_mpr_test_busy; 534 } 535 536 if (pci_intr_map(pa, &ih)) { 537 printf("couldn't map interrupt\n"); 538 goto bail_out; 539 } 540 intrstr = pci_intr_string(pa->pa_pc, ih); 541 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, gdt_intr, sc, 542 sc->sc_dev.dv_xname); 543 if (sc->sc_ih == NULL) { 544 printf("couldn't establish interrupt"); 545 if (intrstr != NULL) 546 printf(" at %s", intrstr); 547 printf("\n"); 548 goto bail_out; 549 } 550 status |= INTR_ESTABLISHED; 551 if (intrstr != NULL) 552 printf("%s ", intrstr); 553 554 if (gdt_attach(sc)) 555 goto bail_out; 556 557 gdt_pci_enable_intr(sc); 558 559 return; 560 561 bail_out: 562 if (status & DPMEM_MAPPED) 563 bus_space_unmap(dpmemt, dpmemh, dpmemsize); 564 if (status & IOMEM_MAPPED) 565 bus_space_unmap(iomemt, iomemh, iomembase); 566 if (status & IO_MAPPED) 567 bus_space_unmap(iot, ioh, iosize); 568 if (status & INTR_ESTABLISHED) 569 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 570 return; 571 } 572 573 /* Enable interrupts */ 574 void 575 gdt_pci_enable_intr(struct gdt_softc *sc) 576 { 577 GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", sc)); 578 579 switch(GDT_CLASS(sc)) { 580 case GDT_PCI: 581 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_IRQDEL, 582 1); 583 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, 584 GDT_CMD_INDEX, 0); 585 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_IRQEN, 586 1); 587 break; 588 589 case GDT_PCINEW: 590 bus_space_write_1(sc->sc_iot, sc->sc_ioh, GDT_EDOOR_REG, 591 0xff); 592 bus_space_write_1(sc->sc_iot, sc->sc_ioh, GDT_CONTROL1, 3); 593 break; 594 595 case GDT_MPR: 596 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, 597 GDT_MPR_EDOOR, 0xff); 598 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_EDOOR_EN, 599 bus_space_read_1(sc->sc_dpmemt, sc->sc_dpmemh, 600 GDT_EDOOR_EN) & ~4); 601 break; 602 } 603 } 604 605 /* 606 * "old" PCI controller-specific functions 607 */ 608 609 void 610 gdt_pci_copy_cmd(struct gdt_softc *sc, struct gdt_ccb *ccb) 611 { 612 /* XXX Not yet implemented */ 613 } 614 615 u_int8_t 616 gdt_pci_get_status(struct gdt_softc *sc) 617 { 618 /* XXX Not yet implemented */ 619 return (0); 620 } 621 622 void 623 gdt_pci_intr(struct gdt_softc *sc, struct gdt_intr_ctx *ctx) 624 { 625 /* XXX Not yet implemented */ 626 } 627 628 void 629 gdt_pci_release_event(struct gdt_softc *sc, struct gdt_ccb *ccb) 630 { 631 /* XXX Not yet implemented */ 632 } 633 634 void 635 gdt_pci_set_sema0(struct gdt_softc *sc) 636 { 637 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_SEMA0, 1); 638 } 639 640 int 641 gdt_pci_test_busy(struct gdt_softc *sc) 642 { 643 /* XXX Not yet implemented */ 644 return (0); 645 } 646 647 /* 648 * "new" PCI controller-specific functions 649 */ 650 651 void 652 gdt_pcinew_copy_cmd(struct gdt_softc *sc, struct gdt_ccb *ccb) 653 { 654 /* XXX Not yet implemented */ 655 } 656 657 u_int8_t 658 gdt_pcinew_get_status(struct gdt_softc *sc) 659 { 660 /* XXX Not yet implemented */ 661 return (0); 662 } 663 664 void 665 gdt_pcinew_intr(struct gdt_softc *sc, struct gdt_intr_ctx *ctx) 666 { 667 /* XXX Not yet implemented */ 668 } 669 670 void 671 gdt_pcinew_release_event(struct gdt_softc *sc, struct gdt_ccb *ccb) 672 { 673 /* XXX Not yet implemented */ 674 } 675 676 void 677 gdt_pcinew_set_sema0(struct gdt_softc *sc) 678 { 679 bus_space_write_1(sc->sc_iot, sc->sc_ioh, GDT_SEMA0_REG, 1); 680 } 681 682 int 683 gdt_pcinew_test_busy(struct gdt_softc *sc) 684 { 685 /* XXX Not yet implemented */ 686 return (0); 687 } 688 689 /* 690 * MPR PCI controller-specific functions 691 */ 692 693 void 694 gdt_mpr_copy_cmd(struct gdt_softc *sc, struct gdt_ccb *ccb) 695 { 696 u_int16_t cp_count = roundup(sc->sc_cmd_len, sizeof (u_int32_t)); 697 u_int16_t dp_offset = sc->sc_cmd_off; 698 u_int16_t cmd_no = sc->sc_cmd_cnt++; 699 700 GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", sc)); 701 702 sc->sc_cmd_off += cp_count; 703 704 bus_space_write_2(sc->sc_dpmemt, sc->sc_dpmemh, 705 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET, 706 GDT_DPMEM_COMMAND_OFFSET + dp_offset); 707 bus_space_write_2(sc->sc_dpmemt, sc->sc_dpmemh, 708 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID, 709 ccb->gc_service); 710 bus_space_write_raw_region_4(sc->sc_dpmemt, sc->sc_dpmemh, 711 GDT_MPR_IC + GDT_DPR_CMD + dp_offset, sc->sc_cmd, cp_count); 712 } 713 714 u_int8_t 715 gdt_mpr_get_status(struct gdt_softc *sc) 716 { 717 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", sc)); 718 719 return bus_space_read_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_EDOOR); 720 } 721 722 void 723 gdt_mpr_intr(struct gdt_softc *sc, struct gdt_intr_ctx *ctx) 724 { 725 GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", sc)); 726 727 if (ctx->istatus & 0x80) { /* error flag */ 728 ctx->istatus &= ~0x80; 729 ctx->cmd_status = bus_space_read_2(sc->sc_dpmemt, 730 sc->sc_dpmemh, GDT_MPR_STATUS); 731 if (ctx->istatus == GDT_ASYNCINDEX) { 732 ctx->service = bus_space_read_2(sc->sc_dpmemt, 733 sc->sc_dpmemh, GDT_MPR_SERVICE); 734 ctx->info2 = bus_space_read_4(sc->sc_dpmemt, 735 sc->sc_dpmemh, GDT_MPR_INFO + sizeof (u_int32_t)); 736 } 737 } else /* no error */ 738 ctx->cmd_status = GDT_S_OK; 739 740 ctx->info = 741 bus_space_read_4(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_INFO); 742 743 if (gdt_polling) /* init. -> more info */ 744 ctx->info2 = bus_space_read_4(sc->sc_dpmemt, sc->sc_dpmemh, 745 GDT_MPR_INFO + sizeof (u_int32_t)); 746 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 747 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_SEMA1, 0); 748 } 749 750 void 751 gdt_mpr_release_event(struct gdt_softc *sc, struct gdt_ccb *ccb) 752 { 753 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", sc)); 754 755 if (gdt_dec16(sc->sc_cmd + GDT_CMD_OPCODE) == GDT_INIT) 756 ccb->gc_service |= 0x80; 757 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_LDOOR, 1); 758 } 759 760 void 761 gdt_mpr_set_sema0(struct gdt_softc *sc) 762 { 763 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", sc)); 764 765 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_SEMA0, 1); 766 } 767 768 int 769 gdt_mpr_test_busy(struct gdt_softc *sc) 770 { 771 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", sc)); 772 773 return (bus_space_read_1(sc->sc_dpmemt, sc->sc_dpmemh, 774 GDT_MPR_SEMA0) & 1); 775 } 776