1 /* $OpenBSD: gdt_pci.c,v 1.27 2022/03/11 18:00:45 mpi Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * This driver would not have written if it was not for the hardware donations 29 * from both ICP-Vortex and �ko.neT. I want to thank them for their support. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/queue.h> 38 #include <sys/endian.h> 39 40 #include <machine/bus.h> 41 42 #include <scsi/scsi_all.h> 43 #include <scsi/scsiconf.h> 44 45 #include <dev/pci/pcidevs.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 49 #include <dev/ic/gdtreg.h> 50 #include <dev/ic/gdtvar.h> 51 52 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 53 #define GDT_PCI_PRODUCT_FC 0x200 54 55 #define GDT_DEVICE_ID_MIN 0x100 56 #define GDT_DEVICE_ID_MAX 0x2ff 57 #define GDT_DEVICE_ID_NEWRX 0x300 58 #define GDT_DEVICE_ID_NEWRX2 0x301 59 60 /* Mapping registers for various areas */ 61 #define GDT_PCI_DPMEM 0x10 62 #define GDT_PCINEW_IOMEM 0x10 63 #define GDT_PCINEW_IO 0x14 64 #define GDT_PCINEW_DPMEM 0x18 65 66 /* PCI SRAM structure */ 67 #define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 68 #define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 69 #define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */ 70 #define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 71 #define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 72 #define GDT_SRAM_SZ 0x40 73 74 /* DPRAM PCI controllers */ 75 #define GDT_DPR_IF 0x00 /* interface area */ 76 #define GDT_6SR (0xff0 - GDT_SRAM_SZ) 77 #define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 78 #define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 79 #define GDT_EVENT 0xff8 /* u_int8_t, release event */ 80 #define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 81 #define GDT_DPRAM_SZ 0x1000 82 83 /* PLX register structure (new PCI controllers) */ 84 #define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 85 #define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 86 #define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 87 #define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 88 #define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */ 89 #define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 90 #define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 91 #define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 92 #define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 93 #define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 94 #define GDT_PLX_SZ 0x80 95 96 /* DPRAM new PCI controllers */ 97 #define GDT_IC 0x00 /* interface */ 98 #define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ) 99 /* SRAM structure */ 100 #define GDT_PCINEW_SZ 0x4000 101 102 /* i960 register structure (PCI MPR controllers) */ 103 #define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 104 #define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 105 #define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 106 #define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */ 107 #define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 108 #define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 109 #define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 110 #define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 111 #define GDT_I960_SZ 0x1000 112 113 /* DPRAM PCI MPR controllers */ 114 #define GDT_I960R 0x00 /* 4KB i960 registers */ 115 #define GDT_MPR_IC GDT_I960_SZ 116 /* interface area */ 117 #define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ) 118 /* SRAM structure */ 119 #define GDT_MPR_SZ 0x4000 120 121 int gdt_pci_probe(struct device *, void *, void *); 122 void gdt_pci_attach(struct device *, struct device *, void *); 123 void gdt_pci_enable_intr(struct gdt_softc *); 124 125 void gdt_pci_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 126 u_int8_t gdt_pci_get_status(struct gdt_softc *); 127 void gdt_pci_intr(struct gdt_softc *, struct gdt_intr_ctx *); 128 void gdt_pci_release_event(struct gdt_softc *, struct gdt_ccb *); 129 void gdt_pci_set_sema0(struct gdt_softc *); 130 int gdt_pci_test_busy(struct gdt_softc *); 131 132 void gdt_pcinew_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 133 u_int8_t gdt_pcinew_get_status(struct gdt_softc *); 134 void gdt_pcinew_intr(struct gdt_softc *, struct gdt_intr_ctx *); 135 void gdt_pcinew_release_event(struct gdt_softc *, struct gdt_ccb *); 136 void gdt_pcinew_set_sema0(struct gdt_softc *); 137 int gdt_pcinew_test_busy(struct gdt_softc *); 138 139 void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 140 u_int8_t gdt_mpr_get_status(struct gdt_softc *); 141 void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *); 142 void gdt_mpr_release_event(struct gdt_softc *, struct gdt_ccb *); 143 void gdt_mpr_set_sema0(struct gdt_softc *); 144 int gdt_mpr_test_busy(struct gdt_softc *); 145 146 const struct cfattach gdt_pci_ca = { 147 sizeof (struct gdt_softc), gdt_pci_probe, gdt_pci_attach 148 }; 149 150 int 151 gdt_pci_probe(struct device *parent, void *match, void *aux) 152 { 153 struct pci_attach_args *pa = aux; 154 155 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX && 156 ((PCI_PRODUCT(pa->pa_id) >= GDT_DEVICE_ID_MIN && 157 PCI_PRODUCT(pa->pa_id) <= GDT_DEVICE_ID_MAX) || 158 PCI_PRODUCT(pa->pa_id) == GDT_DEVICE_ID_NEWRX || 159 PCI_PRODUCT(pa->pa_id) == GDT_DEVICE_ID_NEWRX2)) 160 return (1); 161 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 162 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GDT_RAID1 || 163 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GDT_RAID2)) 164 return (1); 165 return (0); 166 } 167 168 void 169 gdt_pci_attach(struct device *parent, struct device *self, void *aux) 170 { 171 struct pci_attach_args *pa = aux; 172 struct gdt_softc *sc = (void *)self; 173 bus_space_tag_t dpmemt, iomemt, iot; 174 bus_space_handle_t dpmemh, iomemh, ioh; 175 bus_addr_t dpmembase, iomembase, iobase; 176 bus_size_t dpmemsize, iomemsize, iosize; 177 u_int16_t prod; 178 u_int32_t status = 0; 179 #define DPMEM_MAPPED 1 180 #define IOMEM_MAPPED 2 181 #define IO_MAPPED 4 182 #define INTR_ESTABLISHED 8 183 int retries; 184 u_int8_t protocol; 185 pci_intr_handle_t ih; 186 const char *intrstr; 187 188 printf(": "); 189 190 sc->sc_class = 0; 191 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX) { 192 prod = PCI_PRODUCT(pa->pa_id); 193 switch (prod) { 194 case PCI_PRODUCT_VORTEX_GDT_60X0: 195 case PCI_PRODUCT_VORTEX_GDT_6000B: 196 sc->sc_class = GDT_PCI; 197 break; 198 199 case PCI_PRODUCT_VORTEX_GDT_6X10: 200 case PCI_PRODUCT_VORTEX_GDT_6X20: 201 case PCI_PRODUCT_VORTEX_GDT_6530: 202 case PCI_PRODUCT_VORTEX_GDT_6550: 203 case PCI_PRODUCT_VORTEX_GDT_6X17: 204 case PCI_PRODUCT_VORTEX_GDT_6X27: 205 case PCI_PRODUCT_VORTEX_GDT_6537: 206 case PCI_PRODUCT_VORTEX_GDT_6557: 207 case PCI_PRODUCT_VORTEX_GDT_6X15: 208 case PCI_PRODUCT_VORTEX_GDT_6X25: 209 case PCI_PRODUCT_VORTEX_GDT_6535: 210 case PCI_PRODUCT_VORTEX_GDT_6555: 211 sc->sc_class = GDT_PCINEW; 212 break; 213 214 case PCI_PRODUCT_VORTEX_GDT_6X17RP: 215 case PCI_PRODUCT_VORTEX_GDT_6X27RP: 216 case PCI_PRODUCT_VORTEX_GDT_6537RP: 217 case PCI_PRODUCT_VORTEX_GDT_6557RP: 218 case PCI_PRODUCT_VORTEX_GDT_6X11RP: 219 case PCI_PRODUCT_VORTEX_GDT_6X21RP: 220 case PCI_PRODUCT_VORTEX_GDT_6X17RD: 221 case PCI_PRODUCT_VORTEX_GDT_6X27RD: 222 case PCI_PRODUCT_VORTEX_GDT_6537RD: 223 case PCI_PRODUCT_VORTEX_GDT_6557RD: 224 case PCI_PRODUCT_VORTEX_GDT_6X11RD: 225 case PCI_PRODUCT_VORTEX_GDT_6X21RD: 226 case PCI_PRODUCT_VORTEX_GDT_6X18RD: 227 case PCI_PRODUCT_VORTEX_GDT_6X28RD: 228 case PCI_PRODUCT_VORTEX_GDT_6X38RD: 229 case PCI_PRODUCT_VORTEX_GDT_6X58RD: 230 case PCI_PRODUCT_VORTEX_GDT_6518RS: 231 case PCI_PRODUCT_VORTEX_GDT_7X18RN: 232 case PCI_PRODUCT_VORTEX_GDT_7X28RN: 233 case PCI_PRODUCT_VORTEX_GDT_7X38RN: 234 case PCI_PRODUCT_VORTEX_GDT_7X58RN: 235 case PCI_PRODUCT_VORTEX_GDT_6X19RD: 236 case PCI_PRODUCT_VORTEX_GDT_6X29RD: 237 case PCI_PRODUCT_VORTEX_GDT_7X19RN: 238 case PCI_PRODUCT_VORTEX_GDT_7X29RN: 239 case PCI_PRODUCT_VORTEX_GDT_7X43RN: 240 sc->sc_class = GDT_MPR; 241 } 242 243 /* If we don't recognize it, determine class heuristically. */ 244 if (sc->sc_class == 0) 245 sc->sc_class = prod < 0x100 ? GDT_PCINEW : GDT_MPR; 246 247 if (prod >= GDT_PCI_PRODUCT_FC) 248 sc->sc_class |= GDT_FC; 249 250 } else if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 251 sc->sc_class = GDT_MPR; 252 } 253 254 if (pci_mapreg_map(pa, 255 GDT_CLASS(sc) == GDT_PCINEW ? GDT_PCINEW_DPMEM : GDT_PCI_DPMEM, 256 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &dpmemt, 257 &dpmemh, &dpmembase, &dpmemsize, 0)) { 258 if (pci_mapreg_map(pa, 259 GDT_CLASS(sc) == GDT_PCINEW ? GDT_PCINEW_DPMEM : 260 GDT_PCI_DPMEM, 261 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M, 0, 262 &dpmemt,&dpmemh, &dpmembase, &dpmemsize, 0)) { 263 printf("cannot map DPMEM\n"); 264 goto bail_out; 265 } 266 } 267 status |= DPMEM_MAPPED; 268 sc->sc_dpmemt = dpmemt; 269 sc->sc_dpmemh = dpmemh; 270 sc->sc_dpmembase = dpmembase; 271 sc->sc_dmat = pa->pa_dmat; 272 273 /* 274 * The GDT_PCINEW series also has two other regions to map. 275 */ 276 if (GDT_CLASS(sc) == GDT_PCINEW) { 277 if (pci_mapreg_map(pa, GDT_PCINEW_IOMEM, PCI_MAPREG_TYPE_MEM, 278 0, &iomemt, &iomemh, &iomembase, &iomemsize, 0)) { 279 printf("can't map memory mapped i/o ports\n"); 280 goto bail_out; 281 } 282 status |= IOMEM_MAPPED; 283 284 if (pci_mapreg_map(pa, GDT_PCINEW_IO, PCI_MAPREG_TYPE_IO, 0, 285 &iot, &ioh, &iobase, &iosize, 0)) { 286 printf("can't map i/o space\n"); 287 goto bail_out; 288 } 289 status |= IO_MAPPED; 290 sc->sc_iot = iot; 291 sc->sc_ioh = ioh; 292 sc->sc_iobase = iobase; 293 } 294 295 switch (GDT_CLASS(sc)) { 296 case GDT_PCI: 297 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 298 GDT_DPR_IF_SZ >> 2); 299 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 300 printf("can't write to DPMEM\n"); 301 goto bail_out; 302 } 303 304 #if 0 305 /* disable board interrupts, deinit services */ 306 gdth_writeb(0xff, &dp6_ptr->io.irqdel); 307 gdth_writeb(0x00, &dp6_ptr->io.irqen); 308 gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status); 309 gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index); 310 311 gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]); 312 gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx); 313 gdth_writeb(0, &dp6_ptr->io.event); 314 retries = INIT_RETRIES; 315 gdth_delay(20); 316 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) { 317 if (--retries == 0) { 318 printk("initialization error (DEINIT failed)\n"); 319 gdth_munmap(ha->brd); 320 return 0; 321 } 322 gdth_delay(1); 323 } 324 prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]); 325 gdth_writeb(0, &dp6_ptr->u.ic.S_Status); 326 gdth_writeb(0xff, &dp6_ptr->io.irqdel); 327 if (prot_ver != PROTOCOL_VERSION) { 328 printk("illegal protocol version\n"); 329 gdth_munmap(ha->brd); 330 return 0; 331 } 332 333 ha->type = GDT_PCI; 334 ha->ic_all_size = sizeof(dp6_ptr->u); 335 336 /* special command to controller BIOS */ 337 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]); 338 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]); 339 gdth_writel(0x01, &dp6_ptr->u.ic.S_Info[2]); 340 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]); 341 gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx); 342 gdth_writeb(0, &dp6_ptr->io.event); 343 retries = INIT_RETRIES; 344 gdth_delay(20); 345 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) { 346 if (--retries == 0) { 347 printk("initialization error\n"); 348 gdth_munmap(ha->brd); 349 return 0; 350 } 351 gdth_delay(1); 352 } 353 gdth_writeb(0, &dp6_ptr->u.ic.S_Status); 354 gdth_writeb(0xff, &dp6_ptr->io.irqdel); 355 #endif 356 357 sc->sc_ic_all_size = GDT_DPRAM_SZ; 358 359 sc->sc_copy_cmd = gdt_pci_copy_cmd; 360 sc->sc_get_status = gdt_pci_get_status; 361 sc->sc_intr = gdt_pci_intr; 362 sc->sc_release_event = gdt_pci_release_event; 363 sc->sc_set_sema0 = gdt_pci_set_sema0; 364 sc->sc_test_busy = gdt_pci_test_busy; 365 366 break; 367 368 case GDT_PCINEW: 369 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 370 GDT_DPR_IF_SZ >> 2); 371 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 372 printf("cannot write to DPMEM\n"); 373 goto bail_out; 374 } 375 376 #if 0 377 /* disable board interrupts, deinit services */ 378 outb(0x00,PTR2USHORT(&ha->plx->control1)); 379 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg)); 380 381 gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status); 382 gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index); 383 384 gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]); 385 gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx); 386 387 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 388 389 retries = INIT_RETRIES; 390 gdth_delay(20); 391 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) { 392 if (--retries == 0) { 393 printk("initialization error (DEINIT failed)\n"); 394 gdth_munmap(ha->brd); 395 return 0; 396 } 397 gdth_delay(1); 398 } 399 prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]); 400 gdth_writeb(0, &dp6c_ptr->u.ic.Status); 401 if (prot_ver != PROTOCOL_VERSION) { 402 printk("illegal protocol version\n"); 403 gdth_munmap(ha->brd); 404 return 0; 405 } 406 407 ha->type = GDT_PCINEW; 408 ha->ic_all_size = sizeof(dp6c_ptr->u); 409 410 /* special command to controller BIOS */ 411 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]); 412 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]); 413 gdth_writel(0x01, &dp6c_ptr->u.ic.S_Info[2]); 414 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]); 415 gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx); 416 417 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 418 419 retries = INIT_RETRIES; 420 gdth_delay(20); 421 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) { 422 if (--retries == 0) { 423 printk("initialization error\n"); 424 gdth_munmap(ha->brd); 425 return 0; 426 } 427 gdth_delay(1); 428 } 429 gdth_writeb(0, &dp6c_ptr->u.ic.S_Status); 430 #endif 431 432 sc->sc_ic_all_size = GDT_PCINEW_SZ; 433 434 sc->sc_copy_cmd = gdt_pcinew_copy_cmd; 435 sc->sc_get_status = gdt_pcinew_get_status; 436 sc->sc_intr = gdt_pcinew_intr; 437 sc->sc_release_event = gdt_pcinew_release_event; 438 sc->sc_set_sema0 = gdt_pcinew_set_sema0; 439 sc->sc_test_busy = gdt_pcinew_test_busy; 440 441 break; 442 443 case GDT_MPR: 444 bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC, GDT_MPR_MAGIC); 445 if (bus_space_read_4(dpmemt, dpmemh, GDT_MPR_IC) != 446 GDT_MPR_MAGIC) { 447 printf("cannot access DPMEM at 0x%lx (shadowed?)\n", 448 dpmembase); 449 goto bail_out; 450 } 451 452 /* 453 * XXX Here the Linux driver has a weird remapping logic I 454 * don't understand. My controller does not need it, and I 455 * cannot see what purpose it serves, therefore I did not 456 * do anything similar. 457 */ 458 459 bus_space_set_region_4(dpmemt, dpmemh, GDT_I960_SZ, 0, 460 GDT_DPR_IF_SZ >> 2); 461 462 /* Disable everything */ 463 bus_space_write_1(dpmemt, dpmemh, GDT_EDOOR_EN, 464 bus_space_read_1(dpmemt, dpmemh, GDT_EDOOR_EN) | 4); 465 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_EDOOR, 0xff); 466 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS, 467 0); 468 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_CMD_INDEX, 469 0); 470 471 bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_INFO, 472 dpmembase); 473 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 474 0xff); 475 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_LDOOR, 1); 476 477 DELAY(20); 478 retries = GDT_RETRIES; 479 while (bus_space_read_1(dpmemt, dpmemh, 480 GDT_MPR_IC + GDT_S_STATUS) != 0xff) { 481 if (--retries == 0) { 482 printf("DEINIT failed (status 0x%x)\n", 483 bus_space_read_1(dpmemt, dpmemh, 484 GDT_MPR_IC + GDT_S_STATUS)); 485 goto bail_out; 486 } 487 DELAY(1); 488 } 489 490 protocol = (u_int8_t)bus_space_read_4(dpmemt, dpmemh, 491 GDT_MPR_IC + GDT_S_INFO); 492 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS, 493 0); 494 if (protocol != GDT_PROTOCOL_VERSION) { 495 printf("unsupported protocol %d\n", protocol); 496 goto bail_out; 497 } 498 499 /* special commnd to controller BIOS */ 500 bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_INFO, 0); 501 bus_space_write_4(dpmemt, dpmemh, 502 GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), 0); 503 bus_space_write_4(dpmemt, dpmemh, 504 GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t), 1); 505 bus_space_write_4(dpmemt, dpmemh, 506 GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t), 0); 507 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 508 0xfe); 509 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_LDOOR, 1); 510 511 DELAY(20); 512 retries = GDT_RETRIES; 513 while (bus_space_read_1(dpmemt, dpmemh, 514 GDT_MPR_IC + GDT_S_STATUS) != 0xfe) { 515 if (--retries == 0) { 516 printf("initialization error\n"); 517 goto bail_out; 518 } 519 DELAY(1); 520 } 521 522 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS, 523 0); 524 525 sc->sc_ic_all_size = GDT_MPR_SZ; 526 527 sc->sc_copy_cmd = gdt_mpr_copy_cmd; 528 sc->sc_get_status = gdt_mpr_get_status; 529 sc->sc_intr = gdt_mpr_intr; 530 sc->sc_release_event = gdt_mpr_release_event; 531 sc->sc_set_sema0 = gdt_mpr_set_sema0; 532 sc->sc_test_busy = gdt_mpr_test_busy; 533 } 534 535 if (pci_intr_map(pa, &ih)) { 536 printf("couldn't map interrupt\n"); 537 goto bail_out; 538 } 539 intrstr = pci_intr_string(pa->pa_pc, ih); 540 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, gdt_intr, sc, 541 sc->sc_dev.dv_xname); 542 if (sc->sc_ih == NULL) { 543 printf("couldn't establish interrupt"); 544 if (intrstr != NULL) 545 printf(" at %s", intrstr); 546 printf("\n"); 547 goto bail_out; 548 } 549 status |= INTR_ESTABLISHED; 550 if (intrstr != NULL) 551 printf("%s ", intrstr); 552 553 if (gdt_attach(sc)) 554 goto bail_out; 555 556 gdt_pci_enable_intr(sc); 557 558 return; 559 560 bail_out: 561 if (status & DPMEM_MAPPED) 562 bus_space_unmap(dpmemt, dpmemh, dpmemsize); 563 if (status & IOMEM_MAPPED) 564 bus_space_unmap(iomemt, iomemh, iomembase); 565 if (status & IO_MAPPED) 566 bus_space_unmap(iot, ioh, iosize); 567 if (status & INTR_ESTABLISHED) 568 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 569 return; 570 } 571 572 /* Enable interrupts */ 573 void 574 gdt_pci_enable_intr(struct gdt_softc *sc) 575 { 576 GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", sc)); 577 578 switch(GDT_CLASS(sc)) { 579 case GDT_PCI: 580 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_IRQDEL, 581 1); 582 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, 583 GDT_CMD_INDEX, 0); 584 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_IRQEN, 585 1); 586 break; 587 588 case GDT_PCINEW: 589 bus_space_write_1(sc->sc_iot, sc->sc_ioh, GDT_EDOOR_REG, 590 0xff); 591 bus_space_write_1(sc->sc_iot, sc->sc_ioh, GDT_CONTROL1, 3); 592 break; 593 594 case GDT_MPR: 595 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, 596 GDT_MPR_EDOOR, 0xff); 597 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_EDOOR_EN, 598 bus_space_read_1(sc->sc_dpmemt, sc->sc_dpmemh, 599 GDT_EDOOR_EN) & ~4); 600 break; 601 } 602 } 603 604 /* 605 * "old" PCI controller-specific functions 606 */ 607 608 void 609 gdt_pci_copy_cmd(struct gdt_softc *sc, struct gdt_ccb *ccb) 610 { 611 /* XXX Not yet implemented */ 612 } 613 614 u_int8_t 615 gdt_pci_get_status(struct gdt_softc *sc) 616 { 617 /* XXX Not yet implemented */ 618 return (0); 619 } 620 621 void 622 gdt_pci_intr(struct gdt_softc *sc, struct gdt_intr_ctx *ctx) 623 { 624 /* XXX Not yet implemented */ 625 } 626 627 void 628 gdt_pci_release_event(struct gdt_softc *sc, struct gdt_ccb *ccb) 629 { 630 /* XXX Not yet implemented */ 631 } 632 633 void 634 gdt_pci_set_sema0(struct gdt_softc *sc) 635 { 636 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_SEMA0, 1); 637 } 638 639 int 640 gdt_pci_test_busy(struct gdt_softc *sc) 641 { 642 /* XXX Not yet implemented */ 643 return (0); 644 } 645 646 /* 647 * "new" PCI controller-specific functions 648 */ 649 650 void 651 gdt_pcinew_copy_cmd(struct gdt_softc *sc, struct gdt_ccb *ccb) 652 { 653 /* XXX Not yet implemented */ 654 } 655 656 u_int8_t 657 gdt_pcinew_get_status(struct gdt_softc *sc) 658 { 659 /* XXX Not yet implemented */ 660 return (0); 661 } 662 663 void 664 gdt_pcinew_intr(struct gdt_softc *sc, struct gdt_intr_ctx *ctx) 665 { 666 /* XXX Not yet implemented */ 667 } 668 669 void 670 gdt_pcinew_release_event(struct gdt_softc *sc, struct gdt_ccb *ccb) 671 { 672 /* XXX Not yet implemented */ 673 } 674 675 void 676 gdt_pcinew_set_sema0(struct gdt_softc *sc) 677 { 678 bus_space_write_1(sc->sc_iot, sc->sc_ioh, GDT_SEMA0_REG, 1); 679 } 680 681 int 682 gdt_pcinew_test_busy(struct gdt_softc *sc) 683 { 684 /* XXX Not yet implemented */ 685 return (0); 686 } 687 688 /* 689 * MPR PCI controller-specific functions 690 */ 691 692 void 693 gdt_mpr_copy_cmd(struct gdt_softc *sc, struct gdt_ccb *ccb) 694 { 695 u_int16_t cp_count = roundup(sc->sc_cmd_len, sizeof (u_int32_t)); 696 u_int16_t dp_offset = sc->sc_cmd_off; 697 u_int16_t cmd_no = sc->sc_cmd_cnt++; 698 699 GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", sc)); 700 701 sc->sc_cmd_off += cp_count; 702 703 bus_space_write_2(sc->sc_dpmemt, sc->sc_dpmemh, 704 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET, 705 GDT_DPMEM_COMMAND_OFFSET + dp_offset); 706 bus_space_write_2(sc->sc_dpmemt, sc->sc_dpmemh, 707 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID, 708 ccb->gc_service); 709 bus_space_write_raw_region_4(sc->sc_dpmemt, sc->sc_dpmemh, 710 GDT_MPR_IC + GDT_DPR_CMD + dp_offset, sc->sc_cmd, cp_count); 711 } 712 713 u_int8_t 714 gdt_mpr_get_status(struct gdt_softc *sc) 715 { 716 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", sc)); 717 718 return bus_space_read_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_EDOOR); 719 } 720 721 void 722 gdt_mpr_intr(struct gdt_softc *sc, struct gdt_intr_ctx *ctx) 723 { 724 GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", sc)); 725 726 if (ctx->istatus & 0x80) { /* error flag */ 727 ctx->istatus &= ~0x80; 728 ctx->cmd_status = bus_space_read_2(sc->sc_dpmemt, 729 sc->sc_dpmemh, GDT_MPR_STATUS); 730 if (ctx->istatus == GDT_ASYNCINDEX) { 731 ctx->service = bus_space_read_2(sc->sc_dpmemt, 732 sc->sc_dpmemh, GDT_MPR_SERVICE); 733 ctx->info2 = bus_space_read_4(sc->sc_dpmemt, 734 sc->sc_dpmemh, GDT_MPR_INFO + sizeof (u_int32_t)); 735 } 736 } else /* no error */ 737 ctx->cmd_status = GDT_S_OK; 738 739 ctx->info = 740 bus_space_read_4(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_INFO); 741 742 if (gdt_polling) /* init. -> more info */ 743 ctx->info2 = bus_space_read_4(sc->sc_dpmemt, sc->sc_dpmemh, 744 GDT_MPR_INFO + sizeof (u_int32_t)); 745 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 746 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_SEMA1, 0); 747 } 748 749 void 750 gdt_mpr_release_event(struct gdt_softc *sc, struct gdt_ccb *ccb) 751 { 752 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", sc)); 753 754 if (gdt_dec16(sc->sc_cmd + GDT_CMD_OPCODE) == GDT_INIT) 755 ccb->gc_service |= 0x80; 756 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_LDOOR, 1); 757 } 758 759 void 760 gdt_mpr_set_sema0(struct gdt_softc *sc) 761 { 762 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", sc)); 763 764 bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_SEMA0, 1); 765 } 766 767 int 768 gdt_mpr_test_busy(struct gdt_softc *sc) 769 { 770 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", sc)); 771 772 return (bus_space_read_1(sc->sc_dpmemt, sc->sc_dpmemh, 773 GDT_MPR_SEMA0) & 1); 774 } 775