1 /* $OpenBSD: glxreg.h,v 1.1 2010/10/14 21:23:05 pirofti Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Miodrag Vallat. 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * AMD 5536 Geode companion chip MSR registers 21 */ 22 23 /* 24 * Base addresses of the MSR groups. 25 */ 26 27 #ifdef __loongson__ 28 #define SB_MSR_BASE 0x00000000 29 #define GLIU_MSR_BASE 0x10000000 30 #define USB_MSR_BASE 0x40000000 31 #define IDE_MSR_BASE 0x60000000 32 #define DIVIL_MSR_BASE 0x80000000 33 #define ACC_MSR_BASE 0xa0000000 34 #define GLCP_MSR_BASE 0xe0000000 35 #else 36 #define SB_MSR_BASE 0x51000000 37 #define GLIU_MSR_BASE 0x51010000 38 #define USB_MSR_BASE 0x51200000 39 #define IDE_MSR_BASE 0x51300000 40 #define DIVIL_MSR_BASE 0x51400000 41 #define ACC_MSR_BASE 0x51500000 42 #define GLCP_MSR_BASE 0x51700000 43 #endif 44 45 /* 46 * GeodeLink Interface Unit (GLIU) 47 */ 48 49 #define GLIU_GLD_MSR_CAP (GLIU_MSR_BASE + 0x00) 50 #define GLIU_GLD_MSR_CONFIG (GLIU_MSR_BASE + 0x01) 51 #define GLIU_GLD_MSR_SMI (GLIU_MSR_BASE + 0x02) 52 #define GLIU_GLD_MSR_ERROR (GLIU_MSR_BASE + 0x03) 53 #define GLIU_GLD_MSR_PM (GLIU_MSR_BASE + 0x04) 54 #define GLIU_GLD_MSR_DIAG (GLIU_MSR_BASE + 0x05) 55 56 #define GLIU_P2D_BM0 (GLIU_MSR_BASE + 0x20) 57 #define GLIU_P2D_BM1 (GLIU_MSR_BASE + 0x21) 58 #define GLIU_P2D_BM2 (GLIU_MSR_BASE + 0x22) 59 #define GLIU_P2D_BMK0 (GLIU_MSR_BASE + 0x23) 60 #define GLIU_P2D_BMK1 (GLIU_MSR_BASE + 0x24) 61 #define GLIU_P2D_BM3 (GLIU_MSR_BASE + 0x25) 62 #define GLIU_P2D_BM4 (GLIU_MSR_BASE + 0x26) 63 64 #define GLIU_COH (GLIU_MSR_BASE + 0x80) 65 #define GLIU_PAE (GLIU_MSR_BASE + 0x81) 66 #define GLIU_ARB (GLIU_MSR_BASE + 0x82) 67 #define GLIU_ASMI (GLIU_MSR_BASE + 0x83) 68 #define GLIU_AERR (GLIU_MSR_BASE + 0x84) 69 #define GLIU_DEBUG (GLIU_MSR_BASE + 0x85) 70 #define GLIU_PHY_CAP (GLIU_MSR_BASE + 0x86) 71 #define GLIU_NOUT_RESP (GLIU_MSR_BASE + 0x87) 72 #define GLIU_NOUT_WDATA (GLIU_MSR_BASE + 0x88) 73 #define GLIU_WHOAMI (GLIU_MSR_BASE + 0x8b) 74 #define GLIU_SLV_DIS (GLIU_MSR_BASE + 0x8c) 75 #define GLIU_STATISTIC_CNT0 (GLIU_MSR_BASE + 0xa0) 76 #define GLIU_STATISTIC_MASK0 (GLIU_MSR_BASE + 0xa1) 77 #define GLIU_STATISTIC_ACTION0 (GLIU_MSR_BASE + 0xa2) 78 #define GLIU_STATISTIC_CNT1 (GLIU_MSR_BASE + 0xa4) 79 #define GLIU_STATISTIC_MASK1 (GLIU_MSR_BASE + 0xa5) 80 #define GLIU_STATISTIC_ACTION1 (GLIU_MSR_BASE + 0xa6) 81 #define GLIU_STATISTIC_CNT2 (GLIU_MSR_BASE + 0xa8) 82 #define GLIU_STATISTIC_MASK2 (GLIU_MSR_BASE + 0xa9) 83 #define GLIU_STATISTIC_ACTION2 (GLIU_MSR_BASE + 0xaa) 84 #define GLIU_RQ_COMP_VAL (GLIU_MSR_BASE + 0xc0) 85 #define GLIU_RQ_COMP_MASK (GLIU_MSR_BASE + 0xc1) 86 #define GLIU_DA_COMP_VAL_LO (GLIU_MSR_BASE + 0xd0) 87 #define GLIU_DA_COMP_VAL_HI (GLIU_MSR_BASE + 0xd1) 88 #define GLIU_DA_COMP_MASK_LO (GLIU_MSR_BASE + 0xd2) 89 #define GLIU_DA_COMP_MASK_HI (GLIU_MSR_BASE + 0xd3) 90 91 #define GLIU_IOD_BM0 (GLIU_MSR_BASE + 0xe0) 92 #define GLIU_IOD_BM1 (GLIU_MSR_BASE + 0xe1) 93 #define GLIU_IOD_BM2 (GLIU_MSR_BASE + 0xe2) 94 #define GLIU_IOD_BM3 (GLIU_MSR_BASE + 0xe3) 95 #define GLIU_IOD_BM4 (GLIU_MSR_BASE + 0xe4) 96 #define GLIU_IOD_BM5 (GLIU_MSR_BASE + 0xe5) 97 #define GLIU_IOD_BM6 (GLIU_MSR_BASE + 0xe6) 98 #define GLIU_IOD_BM7 (GLIU_MSR_BASE + 0xe7) 99 #define GLIU_IOD_BM8 (GLIU_MSR_BASE + 0xe8) 100 #define GLIU_IOD_BM9 (GLIU_MSR_BASE + 0xe9) 101 #define GLIU_IOD_SC0 (GLIU_MSR_BASE + 0xea) 102 #define GLIU_IOD_SC1 (GLIU_MSR_BASE + 0xeb) 103 #define GLIU_IOD_SC2 (GLIU_MSR_BASE + 0xec) 104 #define GLIU_IOD_SC3 (GLIU_MSR_BASE + 0xed) 105 #define GLIU_IOD_SC4 (GLIU_MSR_BASE + 0xee) 106 #define GLIU_IOD_SC5 (GLIU_MSR_BASE + 0xef) 107 #define GLIU_IOD_SC6 (GLIU_MSR_BASE + 0xf0) 108 #define GLIU_IOD_SC7 (GLIU_MSR_BASE + 0xf1) 109 110 /* 111 * GeodeLink PCI South Bridge (SB) 112 */ 113 114 #define GLPCI_GLD_MSR_CAP (SB_MSR_BASE + 0x00) 115 #define GLPCI_GLD_MSR_CONFIG (SB_MSR_BASE + 0x01) 116 #define GLPCI_GLD_MSR_SMI (SB_MSR_BASE + 0x02) 117 #define GLPCI_GLD_MSR_ERROR (SB_MSR_BASE + 0x03) 118 #define GLPCI_GLD_MSR_PM (SB_MSR_BASE + 0x04) 119 #define GLPCI_GLD_MSR_DIAG (SB_MSR_BASE + 0x05) 120 121 #define GLPCI_CTRL (SB_MSR_BASE + 0x10) 122 #define GLPCI_R0 (SB_MSR_BASE + 0x20) 123 #define GLPCI_R1 (SB_MSR_BASE + 0x21) 124 #define GLPCI_R2 (SB_MSR_BASE + 0x22) 125 #define GLPCI_R3 (SB_MSR_BASE + 0x23) 126 #define GLPCI_R4 (SB_MSR_BASE + 0x24) 127 #define GLPCI_R5 (SB_MSR_BASE + 0x25) 128 #define GLPCI_R6 (SB_MSR_BASE + 0x26) 129 #define GLPCI_R7 (SB_MSR_BASE + 0x27) 130 #define GLPCI_R8 (SB_MSR_BASE + 0x28) 131 #define GLPCI_R9 (SB_MSR_BASE + 0x29) 132 #define GLPCI_R10 (SB_MSR_BASE + 0x2a) 133 #define GLPCI_R11 (SB_MSR_BASE + 0x2b) 134 #define GLPCI_R12 (SB_MSR_BASE + 0x2c) 135 #define GLPCI_R13 (SB_MSR_BASE + 0x2d) 136 #define GLPCI_R14 (SB_MSR_BASE + 0x2e) 137 #define GLPCI_R15 (SB_MSR_BASE + 0x2f) 138 #define GLPCI_PCIHEAD_BYTE0_3 (SB_MSR_BASE + 0x30) 139 #define GLPCI_PCIHEAD_BYTE4_7 (SB_MSR_BASE + 0x31) 140 #define GLPCI_PCIHEAD_BYTE8_B (SB_MSR_BASE + 0x32) 141 #define GLPCI_PCIHEAD_BYTEC_F (SB_MSR_BASE + 0x33) 142 143 /* 144 * AC97 Audio Codec Controller (ACC) 145 */ 146 147 #define ACC_GLD_MSR_CAP (ACC_MSR_BASE + 0x00) 148 #define ACC_GLD_MSR_CONFIG (ACC_MSR_BASE + 0x01) 149 #define ACC_GLD_MSR_SMI (ACC_MSR_BASE + 0x02) 150 #define ACC_GLD_MSR_ERROR (ACC_MSR_BASE + 0x03) 151 #define ACC_GLD_MSR_PM (ACC_MSR_BASE + 0x04) 152 #define ACC_GLD_MSR_DIAG (ACC_MSR_BASE + 0x05) 153 154 /* 155 * USB Controller Registers (USB) 156 */ 157 158 #define USB_GLD_MSR_CAP (USB_MSR_BASE + 0x00) 159 #define USB_GLD_MSR_CONFIG (USB_MSR_BASE + 0x01) 160 #define USB_GLD_MSR_SMI (USB_MSR_BASE + 0x02) 161 #define USB_GLD_MSR_ERROR (USB_MSR_BASE + 0x03) 162 #define USB_GLD_MSR_PM (USB_MSR_BASE + 0x04) 163 #define USB_GLD_MSR_DIAG (USB_MSR_BASE + 0x05) 164 165 #define USB_MSR_OHCB (USB_MSR_BASE + 0x08) 166 #define USB_MSR_EHCB (USB_MSR_BASE + 0x09) 167 #define USB_MSR_UDCB (USB_MSR_BASE + 0x0a) 168 #define USB_MSR_UOCB (USB_MSR_BASE + 0x0b) 169 170 /* 171 * IDE Controller Registers (IDE) 172 */ 173 174 #define IDE_GLD_MSR_CAP (IDE_MSR_BASE + 0x00) 175 #define IDE_GLD_MSR_CONFIG (IDE_MSR_BASE + 0x01) 176 #define IDE_GLD_MSR_SMI (IDE_MSR_BASE + 0x02) 177 #define IDE_GLD_MSR_ERROR (IDE_MSR_BASE + 0x03) 178 #define IDE_GLD_MSR_PM (IDE_MSR_BASE + 0x04) 179 #define IDE_GLD_MSR_DIAG (IDE_MSR_BASE + 0x05) 180 181 #define IDE_IO_BAR (IDE_MSR_BASE + 0x08) 182 #define IDE_CFG (IDE_MSR_BASE + 0x10) 183 #define IDE_DTC (IDE_MSR_BASE + 0x12) 184 #define IDE_CAST (IDE_MSR_BASE + 0x13) 185 #define IDE_ETC (IDE_MSR_BASE + 0x14) 186 #define IDE_PM (IDE_MSR_BASE + 0x15) 187 188 /* 189 * Diverse Integration Logic (DIVIL) 190 */ 191 192 #define DIVIL_GLD_MSR_CAP (DIVIL_MSR_BASE + 0x00) 193 #define DIVIL_GLD_MSR_CONFIG (DIVIL_MSR_BASE + 0x01) 194 #define DIVIL_GLD_MSR_SMI (DIVIL_MSR_BASE + 0x02) 195 #define DIVIL_GLD_MSR_ERROR (DIVIL_MSR_BASE + 0x03) 196 #define DIVIL_GLD_MSR_PM (DIVIL_MSR_BASE + 0x04) 197 #define DIVIL_GLD_MSR_DIAG (DIVIL_MSR_BASE + 0x05) 198 199 #define DIVIL_LBAR_IRQ (DIVIL_MSR_BASE + 0x08) 200 #define DIVIL_LBAR_KEL (DIVIL_MSR_BASE + 0x09) 201 #define DIVIL_LBAR_SMB (DIVIL_MSR_BASE + 0x0b) 202 #define DIVIL_LBAR_GPIO (DIVIL_MSR_BASE + 0x0c) 203 #define DIVIL_LBAR_MFGPT (DIVIL_MSR_BASE + 0x0d) 204 #define DIVIL_LBAR_ACPI (DIVIL_MSR_BASE + 0x0e) 205 #define DIVIL_LBAR_PMS (DIVIL_MSR_BASE + 0x0f) 206 #define DIVIL_LBAR_FLSH0 (DIVIL_MSR_BASE + 0x10) 207 #define DIVIL_LBAR_FLSH1 (DIVIL_MSR_BASE + 0x11) 208 #define DIVIL_LBAR_FLSH2 (DIVIL_MSR_BASE + 0x12) 209 #define DIVIL_LBAR_FLSH3 (DIVIL_MSR_BASE + 0x13) 210 #define DIVIL_LEG_IO (DIVIL_MSR_BASE + 0x14) 211 #define DIVIL_BALL_OPTS (DIVIL_MSR_BASE + 0x15) 212 #define DIVIL_SOFT_IRQ (DIVIL_MSR_BASE + 0x16) 213 #define DIVIL_SOFT_RESET (DIVIL_MSR_BASE + 0x17) 214 #define NORF_CTL (DIVIL_MSR_BASE + 0x18) 215 #define NORF_T01 (DIVIL_MSR_BASE + 0x19) 216 #define NORF_T23 (DIVIL_MSR_BASE + 0x1a) 217 #define NANDF_DATA (DIVIL_MSR_BASE + 0x1b) 218 #define NANDF_CTL (DIVIL_MSR_BASE + 0x1c) 219 #define NANDF_RSVD (DIVIL_MSR_BASE + 0x1d) 220 #define DIVIL_AC_DMA (DIVIL_MSR_BASE + 0x1e) 221 #define KELX_CTL (DIVIL_MSR_BASE + 0x1f) 222 #define PIC_YSEL_LOW (DIVIL_MSR_BASE + 0x20) 223 #define PIC_YSEL_HIGH (DIVIL_MSR_BASE + 0x21) 224 #define PIC_ZSEL_LOW (DIVIL_MSR_BASE + 0x22) 225 #define PIC_ZSEL_HIGH (DIVIL_MSR_BASE + 0x23) 226 #define PIC_IRQM_PRIM (DIVIL_MSR_BASE + 0x24) 227 #define PIC_IRQM_LPC (DIVIL_MSR_BASE + 0x25) 228 #define PIC_XIRR_STS_LOW (DIVIL_MSR_BASE + 0x26) 229 #define PIC_XIRR_STS_HIGH (DIVIL_MSR_BASE + 0x27) 230 #define MFGPT_IRQ (DIVIL_MSR_BASE + 0x28) 231 #define MFGPT_NR (DIVIL_MSR_BASE + 0x29) 232 #define MFGPT_RSVD (DIVIL_MSR_BASE + 0x2a) 233 #define MFGPT_SETUP (DIVIL_MSR_BASE + 0x2b) 234 #define FLPY_3F2_SHDW (DIVIL_MSR_BASE + 0x30) 235 #define FLPY_3F7_SHDW (DIVIL_MSR_BASE + 0x31) 236 #define FLPY_372_SHDW (DIVIL_MSR_BASE + 0x32) 237 #define FLPY_377_SHDW (DIVIL_MSR_BASE + 0x33) 238 #define PIC_SHDW (DIVIL_MSR_BASE + 0x34) 239 #define PIT_SHDW (DIVIL_MSR_BASE + 0x36) 240 #define PIT_CNTRL (DIVIL_MSR_BASE + 0x37) 241 #define UART1_MOD (DIVIL_MSR_BASE + 0x38) 242 #define UART1_DONG (DIVIL_MSR_BASE + 0x39) 243 #define UART1_CONF (DIVIL_MSR_BASE + 0x3a) 244 #define UART1_RSVD_MSR (DIVIL_MSR_BASE + 0x3b) 245 #define UART2_MOD (DIVIL_MSR_BASE + 0x3c) 246 #define UART2_DONG (DIVIL_MSR_BASE + 0x3d) 247 #define UART2_CONF (DIVIL_MSR_BASE + 0x3e) 248 #define UART2_RSVD_MSR (DIVIL_MSR_BASE + 0x3f) 249 #define DMA_MAP (DIVIL_MSR_BASE + 0x40) 250 #define DMA_SHDW_CH0 (DIVIL_MSR_BASE + 0x41) 251 #define DMA_SHDW_CH1 (DIVIL_MSR_BASE + 0x42) 252 #define DMA_SHDW_CH2 (DIVIL_MSR_BASE + 0x43) 253 #define DMA_SHDW_CH3 (DIVIL_MSR_BASE + 0x44) 254 #define DMA_SHDW_CH4 (DIVIL_MSR_BASE + 0x45) 255 #define DMA_SHDW_CH5 (DIVIL_MSR_BASE + 0x46) 256 #define DMA_SHDW_CH6 (DIVIL_MSR_BASE + 0x47) 257 #define DMA_SHDW_CH7 (DIVIL_MSR_BASE + 0x48) 258 #define DMA_MSK_SHDW (DIVIL_MSR_BASE + 0x49) 259 #define LPC_EADDR (DIVIL_MSR_BASE + 0x4c) 260 #define LPC_ESTAT (DIVIL_MSR_BASE + 0x4d) 261 #define LPC_SIRQ (DIVIL_MSR_BASE + 0x4e) 262 #define LPC_RSVD (DIVIL_MSR_BASE + 0x4f) 263 #define PMC_LTMR (DIVIL_MSR_BASE + 0x50) 264 #define PMC_RSVD (DIVIL_MSR_BASE + 0x51) 265 #define RTC_RAM_LOCK (DIVIL_MSR_BASE + 0x54) 266 #define RTC_DOMA_OFFSET (DIVIL_MSR_BASE + 0x55) 267 #define RTC_MONA_OFFSET (DIVIL_MSR_BASE + 0x56) 268 #define RTC_CEN_OFFSET (DIVIL_MSR_BASE + 0x57) 269 270 /* 271 * GeodeLink Control Processor (GLCP) 272 */ 273 274 #define GLCP_GLD_MSR_CAP (GLCP_MSR_BASE + 0x00) 275 #define GLCP_GLD_MSR_CONFIG (GLCP_MSR_BASE + 0x01) 276 #define GLCP_GLD_MSR_SMI (GLCP_MSR_BASE + 0x02) 277 #define GLCP_GLD_MSR_ERROR (GLCP_MSR_BASE + 0x03) 278 #define GLCP_GLD_MSR_PM (GLCP_MSR_BASE + 0x04) 279 #define GLCP_GLD_MSR_DIAG (GLCP_MSR_BASE + 0x05) 280 281 #define GLCP_CLK_DIS_DELAY (GLCP_MSR_BASE + 0x08) 282 #define GLCP_PMCLKDISABLE (GLCP_MSR_BASE + 0x09) 283 #define GLCP_GLB_PM (GLCP_MSR_BASE + 0x0b) 284 #define GLCP_DBGOUT (GLCP_MSR_BASE + 0x0c) 285 #define GLCP_DOWSER (GLCP_MSR_BASE + 0x0e) 286 #define GLCP_CLKOFF (GLCP_MSR_BASE + 0x10) 287 #define GLCP_CLKACTIVE (GLCP_MSR_BASE + 0x11) 288 #define GLCP_CLKDISABLE (GLCP_MSR_BASE + 0x12) 289 #define GLCP_CLK4ACK (GLCP_MSR_BASE + 0x13) 290 #define GLCP_SYS_RST (GLCP_MSR_BASE + 0x14) 291 #define GLCP_DBGCLKCTRL (GLCP_MSR_BASE + 0x16) 292 #define GLCP_CHIP_REV_ID (GLCP_MSR_BASE + 0x17) 293 294 /* 295 * GPIO registers 296 */ 297 298 #define GPIOL_OUT_VAL 0x0000 299 #define GPIOL_OUT_EN 0x0004 300 #define GPIOL_OUT_OD_EN 0x0008 301 #define GPIOL_OUT_INVRT_EN 0x000c 302 #define GPIOL_OUT_AUX1_SEL 0x0010 303 #define GPIOL_OUT_AUX2_SEL 0x0014 304 #define GPIOL_PU_EN 0x0018 305 #define GPIOL_PD_EN 0x001c 306 #define GPIOL_IN_EN 0x0020 307 #define GPIOL_IN_INV_EN 0x0024 308 #define GPIOL_IN_FLTR_EN 0x0028 309 #define GPIOL_IN_EVNTCNT_EN 0x002c 310 #define GPIOL_READ_BACK 0x0030 311 #define GPIOL_IN_AUX1_SEL 0x0034 312 #define GPIOL_EVNT_EN 0x0038 313 #define GPIOL_LOCK_EN 0x003c 314 #define GPIOL_POSEDGE_EN 0x0040 315 #define GPIOL_NEGEDGE_EN 0x0044 316 #define GPIOL_POSEDGE_STS 0x0048 317 #define GPIOL_NEGEDGE_STS 0x004c 318 #define GPIO_FLTR0_AMNT 0x0050 319 #define GPIO_FLTR0_CNT 0x0052 320 #define GPIO_EVNTCNT0 0x0054 321 #define GPIO_EVNTCNT0_COMP 0x0056 322 #define GPIO_FLTR1_AMNT 0x0058 323 #define GPIO_FLTR1_CNT 0x005a 324 #define GPIO_EVNTCNT1 0x005c 325 #define GPIO_EVNTCNT1_COMP 0x005e 326 #define GPIO_FLTR2_AMNT 0x0060 327 #define GPIO_FLTR2_CNT 0x0062 328 #define GPIO_EVNTCNT2 0x0064 329 #define GPIO_EVNTCNT2_COMP 0x0066 330 #define GPIO_FLTR3_AMNT 0x0068 331 #define GPIO_FLTR3_CNT 0x006a 332 #define GPIO_EVNTCNT3 0x006c 333 #define GPIO_EVNTCNT3_COMP 0x006e 334 #define GPIO_FLTR4_AMNT 0x0070 335 #define GPIO_FLTR4_CNT 0x0072 336 #define GPIO_EVNTCNT4 0x0074 337 #define GPIO_EVNTCNT4_COMP 0x0076 338 #define GPIO_FLTR5_AMNT 0x0078 339 #define GPIO_FLTR5_CNT 0x007a 340 #define GPIO_EVNTCNT5 0x007c 341 #define GPIO_EVNTCNT5_COMP 0x007e 342 #define GPIOH_OUT_VAL 0x0080 343 #define GPIOH_OUT_EN 0x0084 344 #define GPIOH_OUT_OD_EN 0x0088 345 #define GPIOH_OUT_INVRT_EN 0x008c 346 #define GPIOH_OUT_AUX1_SEL 0x0090 347 #define GPIOH_OUT_AUX2_SEL 0x0094 348 #define GPIOH_PU_EN 0x0098 349 #define GPIOH_PD_EN 0x009c 350 #define GPIOH_IN_EN 0x00a0 351 #define GPIOH_IN_INV_EN 0x00a4 352 #define GPIOH_IN_FLTR_EN 0x00a8 353 #define GPIOH_IN_EVNTCNT_EN 0x00ac 354 #define GPIOH_READ_BACK 0x00b0 355 #define GPIOH_IN_AUX1_SEL 0x00b4 356 #define GPIOH_EVNT_EN 0x00b8 357 #define GPIOH_LOCK_EN 0x00bc 358 #define GPIOH_POSEDGE_EN 0x00c0 359 #define GPIOH_NEGEDGE_EN 0x00c4 360 #define GPIOH_POSEDGE_STS 0x00c8 361 #define GPIOH_NEGEDGE_STS 0x00cc 362 #define GPIO_FLTR6_AMNT 0x00d0 363 #define GPIO_FLTR6_CNT 0x00d2 364 #define GPIO_EVNTCNT6 0x00d4 365 #define GPIO_EVNTCNT6_COMP 0x00d6 366 #define GPIO_FLTR7_AMNT 0x00d8 367 #define GPIO_FLTR7_CNT 0x00da 368 #define GPIO_EVNTCNT7 0x00dc 369 #define GPIO_EVNTCNT7_COMP 0x00de 370 #define GPIO_MAP_X 0x00e0 371 #define GPIO_MAP_Y 0x00e4 372 #define GPIO_MAP_Z 0x00e8 373 #define GPIO_MAP_W 0x00ec 374 #define GPIO_FE0_SEL 0x00f0 375 #define GPIO_FE1_SEL 0x00f1 376 #define GPIO_FE2_SEL 0x00f2 377 #define GPIO_FE3_SEL 0x00f3 378 #define GPIO_FE4_SEL 0x00f4 379 #define GPIO_FE5_SEL 0x00f5 380 #define GPIO_FE6_SEL 0x00f6 381 #define GPIO_FE7_SEL 0x00f7 382 #define GPIOL_EVNTCNT_DEC 0x00f8 383 #define GPIOH_EVNTCNT_DEC 0x00fc 384 385 #define GPIO_ATOMIC_VALUE(pin,feature) \ 386 ((feature) ? \ 387 ((0 << (16 + (pin))) | (1 << (pin))) : \ 388 ((1 << (16 + (pin))) | (0 << (pin)))) 389