1 /* $OpenBSD: if_agereg.h,v 1.3 2009/07/28 13:53:56 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/age/if_agereg.h,v 1.1 2008/05/19 01:39:59 yongari Exp $ 30 */ 31 32 #ifndef _IF_AGEREG_H 33 #define _IF_AGEREG_H 34 35 #define AGE_PCIR_BAR 0x10 36 37 /* 38 * Attansic Technology Corp. PCI vendor ID 39 */ 40 #define VENDORID_ATTANSIC 0x1969 41 42 /* 43 * Attansic L1 device ID 44 */ 45 #define DEVICEID_ATTANSIC_L1 0x1048 46 47 #define AGE_VPD_REG_CONF_START 0x0100 48 #define AGE_VPD_REG_CONF_END 0x01FF 49 #define AGE_VPD_REG_CONF_SIG 0x5A 50 51 #define AGE_SPI_CTRL 0x200 52 #define SPI_STAT_NOT_READY 0x00000001 53 #define SPI_STAT_WR_ENB 0x00000002 54 #define SPI_STAT_WRP_ENB 0x00000080 55 #define SPI_INST_MASK 0x000000FF 56 #define SPI_START 0x00000100 57 #define SPI_INST_START 0x00000800 58 #define SPI_VPD_ENB 0x00002000 59 #define SPI_LOADER_START 0x00008000 60 #define SPI_CS_HI_MASK 0x00030000 61 #define SPI_CS_HOLD_MASK 0x000C0000 62 #define SPI_CLK_LO_MASK 0x00300000 63 #define SPI_CLK_HI_MASK 0x00C00000 64 #define SPI_CS_SETUP_MASK 0x03000000 65 #define SPI_EPROM_PG_MASK 0x0C000000 66 #define SPI_INST_SHIFT 8 67 #define SPI_CS_HI_SHIFT 16 68 #define SPI_CS_HOLD_SHIFT 18 69 #define SPI_CLK_LO_SHIFT 20 70 #define SPI_CLK_HI_SHIFT 22 71 #define SPI_CS_SETUP_SHIFT 24 72 #define SPI_EPROM_PG_SHIFT 26 73 #define SPI_WAIT_READY 0x10000000 74 75 #define AGE_SPI_ADDR 0x204 /* 16bits */ 76 77 #define AGE_SPI_DATA 0x208 78 79 #define AGE_SPI_CONFIG 0x20C 80 81 #define AGE_SPI_OP_PROGRAM 0x210 /* 8bits */ 82 83 #define AGE_SPI_OP_SC_ERASE 0x211 /* 8bits */ 84 85 #define AGE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */ 86 87 #define AGE_SPI_OP_RDID 0x213 /* 8bits */ 88 89 #define AGE_SPI_OP_WREN 0x214 /* 8bits */ 90 91 #define AGE_SPI_OP_RDSR 0x215 /* 8bits */ 92 93 #define AGE_SPI_OP_WRSR 0x216 /* 8bits */ 94 95 #define AGE_SPI_OP_READ 0x217 /* 8bits */ 96 97 #define AGE_TWSI_CTRL 0x218 98 #define TWSI_CTRL_SW_LD_START 0x00000800 99 #define TWSI_CTRL_HW_LD_START 0x00001000 100 #define TWSI_CTRL_LD_EXIST 0x00400000 101 102 #define AGE_DEV_MISC_CTRL 0x21C 103 104 #define AGE_MASTER_CFG 0x1400 105 #define MASTER_RESET 0x00000001 106 #define MASTER_MTIMER_ENB 0x00000002 107 #define MASTER_ITIMER_ENB 0x00000004 108 #define MASTER_MANUAL_INT_ENB 0x00000008 109 #define MASTER_CHIP_REV_MASK 0x00FF0000 110 #define MASTER_CHIP_ID_MASK 0xFF000000 111 #define MASTER_CHIP_REV_SHIFT 16 112 #define MASTER_CHIP_ID_SHIFT 24 113 114 /* Number of ticks per usec for L1. */ 115 #define AGE_TICK_USECS 2 116 #define AGE_USECS(x) ((x) / AGE_TICK_USECS) 117 118 #define AGE_MANUAL_TIMER 0x1404 119 120 #define AGE_IM_TIMER 0x1408 /* 16bits */ 121 #define AGE_IM_TIMER_MIN 0 122 #define AGE_IM_TIMER_MAX 130000 /* 130ms */ 123 #define AGE_IM_TIMER_DEFAULT 100 124 125 #define AGE_GPHY_CTRL 0x140C /* 16bits */ 126 #define GPHY_CTRL_RST 0x0000 127 #define GPHY_CTRL_CLR 0x0001 128 129 #define AGE_INTR_CLR_TIMER 0x140E /* 16bits */ 130 131 #define AGE_IDLE_STATUS 0x1410 132 #define IDLE_STATUS_RXMAC 0x00000001 133 #define IDLE_STATUS_TXMAC 0x00000002 134 #define IDLE_STATUS_RXQ 0x00000004 135 #define IDLE_STATUS_TXQ 0x00000008 136 #define IDLE_STATUS_DMARD 0x00000010 137 #define IDLE_STATUS_DMAWR 0x00000020 138 #define IDLE_STATUS_SMB 0x00000040 139 #define IDLE_STATUS_CMB 0x00000080 140 141 #define AGE_MDIO 0x1414 142 #define MDIO_DATA_MASK 0x0000FFFF 143 #define MDIO_REG_ADDR_MASK 0x001F0000 144 #define MDIO_OP_READ 0x00200000 145 #define MDIO_OP_WRITE 0x00000000 146 #define MDIO_SUP_PREAMBLE 0x00400000 147 #define MDIO_OP_EXECUTE 0x00800000 148 #define MDIO_CLK_25_4 0x00000000 149 #define MDIO_CLK_25_6 0x02000000 150 #define MDIO_CLK_25_8 0x03000000 151 #define MDIO_CLK_25_10 0x04000000 152 #define MDIO_CLK_25_14 0x05000000 153 #define MDIO_CLK_25_20 0x06000000 154 #define MDIO_CLK_25_28 0x07000000 155 #define MDIO_OP_BUSY 0x08000000 156 #define MDIO_DATA_SHIFT 0 157 #define MDIO_REG_ADDR_SHIFT 16 158 159 #define MDIO_REG_ADDR(x) \ 160 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 161 /* Default PHY address. */ 162 #define AGE_PHY_ADDR 0 163 164 #define AGE_PHY_STATUS 0x1418 165 166 #define AGE_BIST0 0x141C 167 #define BIST0_ENB 0x00000001 168 #define BIST0_SRAM_FAIL 0x00000002 169 #define BIST0_FUSE_FLAG 0x00000004 170 171 #define AGE_BIST1 0x1420 172 #define BIST1_ENB 0x00000001 173 #define BIST1_SRAM_FAIL 0x00000002 174 #define BIST1_FUSE_FLAG 0x00000004 175 176 #define AGE_MAC_CFG 0x1480 177 #define MAC_CFG_TX_ENB 0x00000001 178 #define MAC_CFG_RX_ENB 0x00000002 179 #define MAC_CFG_TX_FC 0x00000004 180 #define MAC_CFG_RX_FC 0x00000008 181 #define MAC_CFG_LOOP 0x00000010 182 #define MAC_CFG_FULL_DUPLEX 0x00000020 183 #define MAC_CFG_TX_CRC_ENB 0x00000040 184 #define MAC_CFG_TX_AUTO_PAD 0x00000080 185 #define MAC_CFG_TX_LENCHK 0x00000100 186 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 187 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 188 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 189 #define MAC_CFG_PROMISC 0x00008000 190 #define MAC_CFG_TX_PAUSE 0x00010000 191 #define MAC_CFG_SCNT 0x00020000 192 #define MAC_CFG_SYNC_RST_TX 0x00040000 193 #define MAC_CFG_SPEED_MASK 0x00300000 194 #define MAC_CFG_SPEED_10_100 0x00100000 195 #define MAC_CFG_SPEED_1000 0x00200000 196 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 197 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 198 #define MAC_CFG_RXCSUM_ENB 0x01000000 199 #define MAC_CFG_ALLMULTI 0x02000000 200 #define MAC_CFG_BCAST 0x04000000 201 #define MAC_CFG_DBG 0x08000000 202 #define MAC_CFG_PREAMBLE_SHIFT 10 203 #define MAC_CFG_PREAMBLE_DEFAULT 7 204 205 #define AGE_IPG_IFG_CFG 0x1484 206 #define IPG_IFG_IPGT_MASK 0x0000007F 207 #define IPG_IFG_MIFG_MASK 0x0000FF00 208 #define IPG_IFG_IPG1_MASK 0x007F0000 209 #define IPG_IFG_IPG2_MASK 0x7F000000 210 #define IPG_IFG_IPGT_SHIFT 0 211 #define IPG_IFG_IPGT_DEFAULT 0x60 212 #define IPG_IFG_MIFG_SHIFT 8 213 #define IPG_IFG_MIFG_DEFAULT 0x50 214 #define IPG_IFG_IPG1_SHIFT 16 215 #define IPG_IFG_IPG1_DEFAULT 0x40 216 #define IPG_IFG_IPG2_SHIFT 24 217 #define IPG_IFG_IPG2_DEFAULT 0x60 218 219 /* station address */ 220 #define AGE_PAR0 0x1488 221 #define AGE_PAR1 0x148C 222 223 /* 64bit multicast hash register. */ 224 #define AGE_MAR0 0x1490 225 #define AGE_MAR1 0x1494 226 227 /* half-duplex parameter configuration. */ 228 #define AGE_HDPX_CFG 0x1498 229 #define HDPX_CFG_LCOL_MASK 0x000003FF 230 #define HDPX_CFG_RETRY_MASK 0x0000F000 231 #define HDPX_CFG_EXC_DEF_EN 0x00010000 232 #define HDPX_CFG_NO_BACK_C 0x00020000 233 #define HDPX_CFG_NO_BACK_P 0x00040000 234 #define HDPX_CFG_ABEBE 0x00080000 235 #define HDPX_CFG_ABEBT_MASK 0x00F00000 236 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 237 #define HDPX_CFG_LCOL_SHIFT 0 238 #define HDPX_CFG_LCOL_DEFAULT 0x37 239 #define HDPX_CFG_RETRY_SHIFT 12 240 #define HDPX_CFG_RETRY_DEFAULT 0x0F 241 #define HDPX_CFG_ABEBT_SHIFT 20 242 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 243 #define HDPX_CFG_JAMIPG_SHIFT 24 244 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 245 246 #define AGE_FRAME_SIZE 0x149C 247 248 #define AGE_WOL_CFG 0x14A0 249 #define WOL_CFG_PATTERN 0x00000001 250 #define WOL_CFG_PATTERN_ENB 0x00000002 251 #define WOL_CFG_MAGIC 0x00000004 252 #define WOL_CFG_MAGIC_ENB 0x00000008 253 #define WOL_CFG_LINK_CHG 0x00000010 254 #define WOL_CFG_LINK_CHG_ENB 0x00000020 255 #define WOL_CFG_PATTERN_DET 0x00000100 256 #define WOL_CFG_MAGIC_DET 0x00000200 257 #define WOL_CFG_LINK_CHG_DET 0x00000400 258 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 259 #define WOL_CFG_PATTERN0 0x00010000 260 #define WOL_CFG_PATTERN1 0x00020000 261 #define WOL_CFG_PATTERN2 0x00040000 262 #define WOL_CFG_PATTERN3 0x00080000 263 #define WOL_CFG_PATTERN4 0x00100000 264 #define WOL_CFG_PATTERN5 0x00200000 265 #define WOL_CFG_PATTERN6 0x00400000 266 267 /* WOL pattern length. */ 268 #define AGE_PATTERN_CFG0 0x14A4 269 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 270 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 271 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 272 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 273 274 #define AGE_PATTERN_CFG1 0x14A8 275 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 276 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 277 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 278 279 #define AGE_SRAM_RD_ADDR 0x1500 280 281 #define AGE_SRAM_RD_LEN 0x1504 282 283 #define AGE_SRAM_RRD_ADDR 0x1508 284 285 #define AGE_SRAM_RRD_LEN 0x150C 286 287 #define AGE_SRAM_TPD_ADDR 0x1510 288 289 #define AGE_SRAM_TPD_LEN 0x1514 290 291 #define AGE_SRAM_TRD_ADDR 0x1518 292 293 #define AGE_SRAM_TRD_LEN 0x151C 294 295 #define AGE_SRAM_RX_FIFO_ADDR 0x1520 296 297 #define AGE_SRAM_RX_FIFO_LEN 0x1524 298 299 #define AGE_SRAM_TX_FIFO_ADDR 0x1528 300 301 #define AGE_SRAM_TX_FIFO_LEN 0x152C 302 303 #define AGE_SRAM_TCPH_ADDR 0x1530 304 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 305 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 306 #define SRAM_TCPH_ADDR_SHIFT 0 307 #define SRAM_PATH_ADDR_SHIFT 16 308 309 #define AGE_DMA_BLOCK 0x1534 310 #define DMA_BLOCK_LOAD 0x00000001 311 312 /* 313 * All descriptors and CMB/SMB share the same high address. 314 */ 315 #define AGE_DESC_ADDR_HI 0x1540 316 317 #define AGE_DESC_RD_ADDR_LO 0x1544 318 319 #define AGE_DESC_RRD_ADDR_LO 0x1548 320 321 #define AGE_DESC_TPD_ADDR_LO 0x154C 322 323 #define AGE_DESC_CMB_ADDR_LO 0x1550 324 325 #define AGE_DESC_SMB_ADDR_LO 0x1554 326 327 #define AGE_DESC_RRD_RD_CNT 0x1558 328 #define DESC_RD_CNT_MASK 0x000007FF 329 #define DESC_RRD_CNT_MASK 0x07FF0000 330 #define DESC_RD_CNT_SHIFT 0 331 #define DESC_RRD_CNT_SHIFT 16 332 333 #define AGE_DESC_TPD_CNT 0x155C 334 #define DESC_TPD_CNT_MASK 0x00003FF 335 #define DESC_TPD_CNT_SHIFT 0 336 337 #define AGE_TXQ_CFG 0x1580 338 #define TXQ_CFG_TPD_BURST_MASK 0x0000001F 339 #define TXQ_CFG_ENB 0x00000020 340 #define TXQ_CFG_ENHANCED_MODE 0x00000040 341 #define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00 342 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 343 #define TXQ_CFG_TPD_BURST_SHIFT 0 344 #define TXQ_CFG_TPD_BURST_DEFAULT 4 345 #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8 346 #define TXQ_CFG_TPD_FETCH_DEFAULT 16 347 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 348 #define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256 349 350 #define AGE_TX_JUMBO_TPD_TH_IPG 0x1584 351 #define TX_JUMBO_TPD_TH_MASK 0x000007FF 352 #define TX_JUMBO_TPD_IPG_MASK 0x001F0000 353 #define TX_JUMBO_TPD_TH_SHIFT 0 354 #define TX_JUMBO_TPD_IPG_SHIFT 16 355 #define TX_JUMBO_TPD_IPG_DEFAULT 1 356 357 #define AGE_RXQ_CFG 0x15A0 358 #define RXQ_CFG_RD_BURST_MASK 0x000000FF 359 #define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00 360 #define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000 361 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 362 #define RXQ_CFG_ENB 0x80000000 363 #define RXQ_CFG_RD_BURST_SHIFT 0 364 #define RXQ_CFG_RD_BURST_DEFAULT 8 365 #define RXQ_CFG_RRD_BURST_THRESH_SHIFT 8 366 #define RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8 367 #define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT 16 368 #define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1 369 370 #define AGE_RXQ_JUMBO_CFG 0x15A4 371 #define RXQ_JUMBO_CFG_SZ_THRESH_MASK 0x000007FF 372 #define RXQ_JUMBO_CFG_LKAH_MASK 0x00007800 373 #define RXQ_JUMBO_CFG_RRD_TIMER_MASK 0xFFFF0000 374 #define RXQ_JUMBO_CFG_SZ_THRESH_SHIFT 0 375 #define RXQ_JUMBO_CFG_LKAH_SHIFT 11 376 #define RXQ_JUMBO_CFG_LKAH_DEFAULT 0x01 377 #define RXQ_JUMBO_CFG_RRD_TIMER_SHIFT 16 378 379 #define AGE_RXQ_FIFO_PAUSE_THRESH 0x15A8 380 #define RXQ_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 381 #define RXQ_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF000 382 #define RXQ_FIFO_PAUSE_THRESH_LO_SHIFT 0 383 #define RXQ_FIFO_PAUSE_THRESH_HI_SHIFT 16 384 385 #define AGE_RXQ_RRD_PAUSE_THRESH 0x15AC 386 #define RXQ_RRD_PAUSE_THRESH_HI_MASK 0x00000FFF 387 #define RXQ_RRD_PAUSE_THRESH_LO_MASK 0x0FFF0000 388 #define RXQ_RRD_PAUSE_THRESH_HI_SHIFT 0 389 #define RXQ_RRD_PAUSE_THRESH_LO_SHIFT 16 390 391 #define AGE_DMA_CFG 0x15C0 392 #define DMA_CFG_IN_ORDER 0x00000001 393 #define DMA_CFG_ENH_ORDER 0x00000002 394 #define DMA_CFG_OUT_ORDER 0x00000004 395 #define DMA_CFG_RCB_64 0x00000000 396 #define DMA_CFG_RCB_128 0x00000008 397 #define DMA_CFG_RD_BURST_128 0x00000000 398 #define DMA_CFG_RD_BURST_256 0x00000010 399 #define DMA_CFG_RD_BURST_512 0x00000020 400 #define DMA_CFG_RD_BURST_1024 0x00000030 401 #define DMA_CFG_RD_BURST_2048 0x00000040 402 #define DMA_CFG_RD_BURST_4096 0x00000050 403 #define DMA_CFG_WR_BURST_128 0x00000000 404 #define DMA_CFG_WR_BURST_256 0x00000080 405 #define DMA_CFG_WR_BURST_512 0x00000100 406 #define DMA_CFG_WR_BURST_1024 0x00000180 407 #define DMA_CFG_WR_BURST_2048 0x00000200 408 #define DMA_CFG_WR_BURST_4096 0x00000280 409 #define DMA_CFG_RD_ENB 0x00000400 410 #define DMA_CFG_WR_ENB 0x00000800 411 #define DMA_CFG_RD_BURST_MASK 0x07 412 #define DMA_CFG_RD_BURST_SHIFT 4 413 #define DMA_CFG_WR_BURST_MASK 0x07 414 #define DMA_CFG_WR_BURST_SHIFT 7 415 416 #define AGE_CSMB_CTRL 0x15D0 417 #define CSMB_CTRL_CMB_KICK 0x00000001 418 #define CSMB_CTRL_SMB_KICK 0x00000002 419 #define CSMB_CTRL_CMB_ENB 0x00000004 420 #define CSMB_CTRL_SMB_ENB 0x00000008 421 422 /* CMB DMA Write Threshold Register */ 423 #define AGE_CMB_WR_THRESH 0x15D4 424 #define CMB_WR_THRESH_RRD_MASK 0x000007FF 425 #define CMB_WR_THRESH_TPD_MASK 0x07FF0000 426 #define CMB_WR_THRESH_RRD_SHIFT 0 427 #define CMB_WR_THRESH_RRD_DEFAULT 4 428 #define CMB_WR_THRESH_TPD_SHIFT 16 429 #define CMB_WR_THRESH_TPD_DEFAULT 4 430 431 /* RX/TX count-down timer to trigger CMB-write. */ 432 #define AGE_CMB_WR_TIMER 0x15D8 433 #define CMB_WR_TIMER_RX_MASK 0x0000FFFF 434 #define CMB_WR_TIMER_TX_MASK 0xFFFF0000 435 #define CMB_WR_TIMER_RX_SHIFT 0 436 #define CMB_WR_TIMER_TX_SHIFT 16 437 438 /* Number of packet received since last CMB write */ 439 #define AGE_CMB_RX_PKT_CNT 0x15DC 440 441 /* Number of packet transmitted since last CMB write */ 442 #define AGE_CMB_TX_PKT_CNT 0x15E0 443 444 /* SMB auto DMA timer register */ 445 #define AGE_SMB_TIMER 0x15E4 446 447 #define AGE_MBOX 0x15F0 448 #define MBOX_RD_PROD_IDX_MASK 0x000007FF 449 #define MBOX_RRD_CONS_IDX_MASK 0x003FF800 450 #define MBOX_TD_PROD_IDX_MASK 0xFFC00000 451 #define MBOX_RD_PROD_IDX_SHIFT 0 452 #define MBOX_RRD_CONS_IDX_SHIFT 11 453 #define MBOX_TD_PROD_IDX_SHIFT 22 454 455 #define AGE_INTR_STATUS 0x1600 456 #define INTR_SMB 0x00000001 457 #define INTR_MOD_TIMER 0x00000002 458 #define INTR_MANUAL_TIMER 0x00000004 459 #define INTR_RX_FIFO_OFLOW 0x00000008 460 #define INTR_RD_UNDERRUN 0x00000010 461 #define INTR_RRD_OFLOW 0x00000020 462 #define INTR_TX_FIFO_UNDERRUN 0x00000040 463 #define INTR_LINK_CHG 0x00000080 464 #define INTR_HOST_RD_UNDERRUN 0x00000100 465 #define INTR_HOST_RRD_OFLOW 0x00000200 466 #define INTR_DMA_RD_TO_RST 0x00000400 467 #define INTR_DMA_WR_TO_RST 0x00000800 468 #define INTR_GPHY 0x00001000 469 #define INTR_RX_PKT 0x00010000 470 #define INTR_TX_PKT 0x00020000 471 #define INTR_TX_DMA 0x00040000 472 #define INTR_RX_DMA 0x00080000 473 #define INTR_CMB_RX 0x00100000 474 #define INTR_CMB_TX 0x00200000 475 #define INTR_MAC_RX 0x00400000 476 #define INTR_MAC_TX 0x00800000 477 #define INTR_UNDERRUN 0x01000000 478 #define INTR_FRAME_ERROR 0x02000000 479 #define INTR_FRAME_OK 0x04000000 480 #define INTR_CSUM_ERROR 0x08000000 481 #define INTR_PHY_LINK_DOWN 0x10000000 482 #define INTR_DIS_SMB 0x20000000 483 #define INTR_DIS_DMA 0x40000000 484 #define INTR_DIS_INT 0x80000000 485 486 /* Interrupt Mask Register */ 487 #define AGE_INTR_MASK 0x1604 488 489 #define AGE_INTRS \ 490 (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 491 INTR_CMB_TX | INTR_CMB_RX) 492 493 /* Statistics counters collected by the MAC. */ 494 struct smb { 495 /* Rx stats. */ 496 uint32_t rx_frames; 497 uint32_t rx_bcast_frames; 498 uint32_t rx_mcast_frames; 499 uint32_t rx_pause_frames; 500 uint32_t rx_control_frames; 501 uint32_t rx_crcerrs; 502 uint32_t rx_lenerrs; 503 uint32_t rx_bytes; 504 uint32_t rx_runts; 505 uint32_t rx_fragments; 506 uint32_t rx_pkts_64; 507 uint32_t rx_pkts_65_127; 508 uint32_t rx_pkts_128_255; 509 uint32_t rx_pkts_256_511; 510 uint32_t rx_pkts_512_1023; 511 uint32_t rx_pkts_1024_1518; 512 uint32_t rx_pkts_1519_max; 513 uint32_t rx_pkts_truncated; 514 uint32_t rx_fifo_oflows; 515 uint32_t rx_desc_oflows; 516 uint32_t rx_alignerrs; 517 uint32_t rx_bcast_bytes; 518 uint32_t rx_mcast_bytes; 519 uint32_t rx_pkts_filtered; 520 /* Tx stats. */ 521 uint32_t tx_frames; 522 uint32_t tx_bcast_frames; 523 uint32_t tx_mcast_frames; 524 uint32_t tx_pause_frames; 525 uint32_t tx_excess_defer; 526 uint32_t tx_control_frames; 527 uint32_t tx_deferred; 528 uint32_t tx_bytes; 529 uint32_t tx_pkts_64; 530 uint32_t tx_pkts_65_127; 531 uint32_t tx_pkts_128_255; 532 uint32_t tx_pkts_256_511; 533 uint32_t tx_pkts_512_1023; 534 uint32_t tx_pkts_1024_1518; 535 uint32_t tx_pkts_1519_max; 536 uint32_t tx_single_colls; 537 uint32_t tx_multi_colls; 538 uint32_t tx_late_colls; 539 uint32_t tx_excess_colls; 540 uint32_t tx_underrun; 541 uint32_t tx_desc_underrun; 542 uint32_t tx_lenerrs; 543 uint32_t tx_pkts_truncated; 544 uint32_t tx_bcast_bytes; 545 uint32_t tx_mcast_bytes; 546 uint32_t updated; 547 } __packed; 548 549 /* Coalescing message block */ 550 struct cmb { 551 uint32_t intr_status; 552 uint32_t rprod_cons; 553 #define RRD_PROD_MASK 0x0000FFFF 554 #define RD_CONS_MASK 0xFFFF0000 555 #define RRD_PROD_SHIFT 0 556 #define RD_CONS_SHIFT 16 557 uint32_t tpd_cons; 558 #define CMB_UPDATED 0x00000001 559 #define TPD_CONS_MASK 0xFFFF0000 560 #define TPD_CONS_SHIFT 16 561 } __packed; 562 563 /* Rx return descriptor */ 564 struct rx_rdesc { 565 uint32_t index; 566 #define AGE_RRD_NSEGS_MASK 0x000000FF 567 #define AGE_RRD_CONS_MASK 0xFFFF0000 568 #define AGE_RRD_NSEGS_SHIFT 0 569 #define AGE_RRD_CONS_SHIFT 16 570 uint32_t len; 571 #define AGE_RRD_CSUM_MASK 0x0000FFFF 572 #define AGE_RRD_LEN_MASK 0xFFFF0000 573 #define AGE_RRD_CSUM_SHIFT 0 574 #define AGE_RRD_LEN_SHIFT 16 575 uint32_t flags; 576 #define AGE_RRD_ETHERNET 0x00000080 577 #define AGE_RRD_VLAN 0x00000100 578 #define AGE_RRD_ERROR 0x00000200 579 #define AGE_RRD_IPV4 0x00000400 580 #define AGE_RRD_UDP 0x00000800 581 #define AGE_RRD_TCP 0x00001000 582 #define AGE_RRD_BCAST 0x00002000 583 #define AGE_RRD_MCAST 0x00004000 584 #define AGE_RRD_PAUSE 0x00008000 585 #define AGE_RRD_CRC 0x00010000 586 #define AGE_RRD_CODE 0x00020000 587 #define AGE_RRD_DRIBBLE 0x00040000 588 #define AGE_RRD_RUNT 0x00080000 589 #define AGE_RRD_OFLOW 0x00100000 590 #define AGE_RRD_TRUNC 0x00200000 591 #define AGE_RRD_IPCSUM_NOK 0x00400000 592 #define AGE_RRD_TCP_UDPCSUM_NOK 0x00800000 593 #define AGE_RRD_LENGTH_NOK 0x01000000 594 #define AGE_RRD_DES_ADDR_FILTERED 0x02000000 595 uint32_t vtags; 596 #define AGE_RRD_VLAN_MASK 0xFFFF0000 597 #define AGE_RRD_VLAN_SHIFT 16 598 } __packed; 599 600 #define AGE_RX_NSEGS(x) \ 601 (((x) & AGE_RRD_NSEGS_MASK) >> AGE_RRD_NSEGS_SHIFT) 602 #define AGE_RX_CONS(x) \ 603 (((x) & AGE_RRD_CONS_MASK) >> AGE_RRD_CONS_SHIFT) 604 #define AGE_RX_CSUM(x) \ 605 (((x) & AGE_RRD_CSUM_MASK) >> AGE_RRD_CSUM_SHIFT) 606 #define AGE_RX_BYTES(x) \ 607 (((x) & AGE_RRD_LEN_MASK) >> AGE_RRD_LEN_SHIFT) 608 #define AGE_RX_VLAN(x) \ 609 (((x) & AGE_RRD_VLAN_MASK) >> AGE_RRD_VLAN_SHIFT) 610 #define AGE_RX_VLAN_TAG(x) \ 611 (((x) >> 4) | (((x) & 7) << 13) | (((x) & 8) << 9)) 612 613 /* Rx descriptor. */ 614 struct rx_desc { 615 uint64_t addr; 616 uint32_t len; 617 #define AGE_RD_LEN_MASK 0x0000FFFF 618 #define AGE_CONS_UPD_REQ_MASK 0xFFFF0000 619 #define AGE_RD_LEN_SHIFT 0 620 #define AGE_CONS_UPD_REQ_SHIFT 16 621 } __packed; 622 623 /* Tx descriptor. */ 624 struct tx_desc { 625 uint64_t addr; 626 uint32_t len; 627 #define AGE_TD_VLAN_MASK 0xFFFF0000 628 #define AGE_TD_PKT_INT 0x00008000 629 #define AGE_TD_DMA_INT 0x00004000 630 #define AGE_TD_BUFLEN_MASK 0x00003FFF 631 #define AGE_TD_VLAN_SHIFT 16 632 #define AGE_TX_VLAN_TAG(x) \ 633 (((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8)) 634 #define AGE_TD_BUFLEN_SHIFT 0 635 #define AGE_TX_BYTES(x) \ 636 (((x) << AGE_TD_BUFLEN_SHIFT) & AGE_TD_BUFLEN_MASK) 637 uint32_t flags; 638 #define AGE_TD_TSO_MSS 0xFFF80000 639 #define AGE_TD_TSO_HDR 0x00040000 640 #define AGE_TD_TSO_TCPHDR_LEN 0x0003C000 641 #define AGE_TD_IPHDR_LEN 0x00003C00 642 #define AGE_TD_LLC_SNAP 0x00000200 643 #define AGE_TD_VLAN_TAGGED 0x00000100 644 #define AGE_TD_UDPCSUM 0x00000080 645 #define AGE_TD_TCPCSUM 0x00000040 646 #define AGE_TD_IPCSUM 0x00000020 647 #define AGE_TD_TSO_IPV4 0x00000010 648 #define AGE_TD_TSO_IPV6 0x00000012 649 #define AGE_TD_CSUM 0x00000008 650 #define AGE_TD_INSERT_VLAN_TAG 0x00000004 651 #define AGE_TD_COALESCE 0x00000002 652 #define AGE_TD_EOP 0x00000001 653 654 #define AGE_TD_CSUM_PLOADOFFSET 0x00FF0000 655 #define AGE_TD_CSUM_XSUMOFFSET 0xFF000000 656 #define AGE_TD_CSUM_XSUMOFFSET_SHIFT 24 657 #define AGE_TD_CSUM_PLOADOFFSET_SHIFT 16 658 #define AGE_TD_TSO_MSS_SHIFT 19 659 #define AGE_TD_TSO_TCPHDR_LEN_SHIFT 14 660 #define AGE_TD_IPHDR_LEN_SHIFT 10 661 } __packed; 662 663 #define AGE_TX_RING_CNT 256 664 #define AGE_RX_RING_CNT 256 665 #define AGE_RR_RING_CNT (AGE_TX_RING_CNT + AGE_RX_RING_CNT) 666 /* The following ring alignments are just guessing. */ 667 #define AGE_TX_RING_ALIGN 16 668 #define AGE_RX_RING_ALIGN 16 669 #define AGE_RR_RING_ALIGN 16 670 #define AGE_CMB_ALIGN 16 671 #define AGE_SMB_ALIGN 16 672 673 #define AGE_TSO_MAXSEGSIZE 4096 674 #define AGE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 675 #define AGE_MAXTXSEGS 32 676 677 #define AGE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 678 #define AGE_ADDR_HI(x) ((uint64_t) (x) >> 32) 679 680 #define AGE_MSI_MESSAGES 1 681 #define AGE_MSIX_MESSAGES 1 682 683 #define AGE_JUMBO_FRAMELEN 10240 684 #define AGE_JUMBO_MTU \ 685 (AGE_JUMBO_FRAMELEN - EVL_ENCAPLEN - \ 686 ETHER_HDR_LEN - ETHER_CRC_LEN) 687 688 #define AGE_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 689 690 #define AGE_PROC_MIN 30 691 #define AGE_PROC_MAX (AGE_RX_RING_CNT - 1) 692 #define AGE_PROC_DEFAULT (AGE_RX_RING_CNT / 2) 693 694 struct age_txdesc { 695 struct mbuf *tx_m; 696 bus_dmamap_t tx_dmamap; 697 struct tx_desc *tx_desc; 698 }; 699 700 struct age_rxdesc { 701 struct mbuf *rx_m; 702 bus_dmamap_t rx_dmamap; 703 struct rx_desc *rx_desc; 704 }; 705 706 struct age_chain_data{ 707 struct age_txdesc age_txdesc[AGE_TX_RING_CNT]; 708 struct age_rxdesc age_rxdesc[AGE_RX_RING_CNT]; 709 bus_dmamap_t age_tx_ring_map; 710 bus_dma_segment_t age_tx_ring_seg; 711 bus_dmamap_t age_rx_ring_map; 712 bus_dma_segment_t age_rx_ring_seg; 713 bus_dmamap_t age_rx_sparemap; 714 bus_dmamap_t age_rr_ring_map; 715 bus_dma_segment_t age_rr_ring_seg; 716 bus_dmamap_t age_cmb_block_map; 717 bus_dma_segment_t age_cmb_block_seg; 718 bus_dmamap_t age_smb_block_map; 719 bus_dma_segment_t age_smb_block_seg; 720 721 int age_tx_prod; 722 int age_tx_cons; 723 int age_tx_cnt; 724 int age_rx_cons; 725 int age_rr_cons; 726 int age_rxlen; 727 728 struct mbuf *age_rxhead; 729 struct mbuf *age_rxtail; 730 struct mbuf *age_rxprev_tail; 731 }; 732 733 struct age_ring_data { 734 struct tx_desc *age_tx_ring; 735 bus_dma_segment_t age_tx_ring_seg; 736 bus_addr_t age_tx_ring_paddr; 737 struct rx_desc *age_rx_ring; 738 bus_dma_segment_t age_rx_ring_seg; 739 bus_addr_t age_rx_ring_paddr; 740 struct rx_rdesc *age_rr_ring; 741 bus_dma_segment_t age_rr_ring_seg; 742 bus_addr_t age_rr_ring_paddr; 743 struct cmb *age_cmb_block; 744 bus_dma_segment_t age_cmb_block_seg; 745 bus_addr_t age_cmb_block_paddr; 746 struct smb *age_smb_block; 747 bus_dma_segment_t age_smb_block_seg; 748 bus_addr_t age_smb_block_paddr; 749 }; 750 751 #define AGE_TX_RING_SZ \ 752 (sizeof(struct tx_desc) * AGE_TX_RING_CNT) 753 #define AGE_RX_RING_SZ \ 754 (sizeof(struct rx_desc) * AGE_RX_RING_CNT) 755 #define AGE_RR_RING_SZ \ 756 (sizeof(struct rx_rdesc) * AGE_RR_RING_CNT) 757 #define AGE_CMB_BLOCK_SZ sizeof(struct cmb) 758 #define AGE_SMB_BLOCK_SZ sizeof(struct smb) 759 760 struct age_stats { 761 /* Rx stats. */ 762 uint64_t rx_frames; 763 uint64_t rx_bcast_frames; 764 uint64_t rx_mcast_frames; 765 uint32_t rx_pause_frames; 766 uint32_t rx_control_frames; 767 uint32_t rx_crcerrs; 768 uint32_t rx_lenerrs; 769 uint64_t rx_bytes; 770 uint32_t rx_runts; 771 uint64_t rx_fragments; 772 uint64_t rx_pkts_64; 773 uint64_t rx_pkts_65_127; 774 uint64_t rx_pkts_128_255; 775 uint64_t rx_pkts_256_511; 776 uint64_t rx_pkts_512_1023; 777 uint64_t rx_pkts_1024_1518; 778 uint64_t rx_pkts_1519_max; 779 uint64_t rx_pkts_truncated; 780 uint32_t rx_fifo_oflows; 781 uint32_t rx_desc_oflows; 782 uint32_t rx_alignerrs; 783 uint64_t rx_bcast_bytes; 784 uint64_t rx_mcast_bytes; 785 uint64_t rx_pkts_filtered; 786 /* Tx stats. */ 787 uint64_t tx_frames; 788 uint64_t tx_bcast_frames; 789 uint64_t tx_mcast_frames; 790 uint32_t tx_pause_frames; 791 uint32_t tx_excess_defer; 792 uint32_t tx_control_frames; 793 uint32_t tx_deferred; 794 uint64_t tx_bytes; 795 uint64_t tx_pkts_64; 796 uint64_t tx_pkts_65_127; 797 uint64_t tx_pkts_128_255; 798 uint64_t tx_pkts_256_511; 799 uint64_t tx_pkts_512_1023; 800 uint64_t tx_pkts_1024_1518; 801 uint64_t tx_pkts_1519_max; 802 uint32_t tx_single_colls; 803 uint32_t tx_multi_colls; 804 uint32_t tx_late_colls; 805 uint32_t tx_excess_colls; 806 uint32_t tx_underrun; 807 uint32_t tx_desc_underrun; 808 uint32_t tx_lenerrs; 809 uint32_t tx_pkts_truncated; 810 uint64_t tx_bcast_bytes; 811 uint64_t tx_mcast_bytes; 812 }; 813 814 /* 815 * Software state per device. 816 */ 817 struct age_softc { 818 struct device sc_dev; 819 struct arpcom sc_arpcom; 820 821 bus_space_tag_t sc_mem_bt; 822 bus_space_handle_t sc_mem_bh; 823 bus_size_t sc_mem_size; 824 bus_dma_tag_t sc_dmat; 825 pci_chipset_tag_t sc_pct; 826 pcitag_t sc_pcitag; 827 828 void *sc_irq_handle; 829 830 struct mii_data sc_miibus; 831 int age_rev; 832 int age_chip_rev; 833 int age_phyaddr; 834 835 uint8_t age_eaddr[ETHER_ADDR_LEN]; 836 uint32_t age_dma_rd_burst; 837 uint32_t age_dma_wr_burst; 838 839 uint32_t age_flags; 840 #define AGE_FLAG_PCIE 0x0001 841 #define AGE_FLAG_PCIX 0x0002 842 #define AGE_FLAG_MSI 0x0004 843 #define AGE_FLAG_MSIX 0x0008 844 #define AGE_FLAG_PMCAP 0x0010 845 #define AGE_FLAG_DETACH 0x4000 846 #define AGE_FLAG_LINK 0x8000 847 848 struct timeout age_tick_ch; 849 struct age_stats age_stat; 850 struct age_chain_data age_cdata; 851 struct age_ring_data age_rdata; 852 int age_process_limit; 853 int age_int_mod; 854 int age_max_frame_size; 855 int age_morework; 856 int age_rr_prod; 857 int age_tpd_cons; 858 859 int age_txd_spare; 860 }; 861 862 /* Register access macros. */ 863 #define CSR_WRITE_4(sc, reg, val) \ 864 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 865 #define CSR_WRITE_2(sc, reg, val) \ 866 bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 867 #define CSR_READ_2(sc, reg) \ 868 bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 869 #define CSR_READ_4(sc, reg) \ 870 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 871 872 873 #define AGE_COMMIT_MBOX(_sc) \ 874 do { \ 875 CSR_WRITE_4(_sc, AGE_MBOX, \ 876 (((_sc)->age_cdata.age_rx_cons << MBOX_RD_PROD_IDX_SHIFT) & \ 877 MBOX_RD_PROD_IDX_MASK) | \ 878 (((_sc)->age_cdata.age_rr_cons << \ 879 MBOX_RRD_CONS_IDX_SHIFT) & MBOX_RRD_CONS_IDX_MASK) | \ 880 (((_sc)->age_cdata.age_tx_prod << MBOX_TD_PROD_IDX_SHIFT) & \ 881 MBOX_TD_PROD_IDX_MASK)); \ 882 } while (0) 883 884 #define AGE_RXCHAIN_RESET(_sc) \ 885 do { \ 886 (_sc)->age_cdata.age_rxhead = NULL; \ 887 (_sc)->age_cdata.age_rxtail = NULL; \ 888 (_sc)->age_cdata.age_rxprev_tail = NULL; \ 889 (_sc)->age_cdata.age_rxlen = 0; \ 890 } while (0) 891 892 #define AGE_TX_TIMEOUT 5 893 #define AGE_RESET_TIMEOUT 100 894 #define AGE_TIMEOUT 1000 895 #define AGE_PHY_TIMEOUT 1000 896 897 #endif /* _IF_AGEREG_H */ 898