1 /* $OpenBSD: if_alc.c,v 1.54 2020/07/10 13:26:37 patrick Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR813x/AR815x/AR816x/AR817x PCIe Ethernet. */ 30 31 #include "bpfilter.h" 32 #include "vlan.h" 33 34 #include <sys/param.h> 35 #include <sys/endian.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/queue.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/timeout.h> 43 #include <sys/socket.h> 44 45 #include <machine/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 51 #include <netinet/in.h> 52 #include <netinet/if_ether.h> 53 54 #if NBPFILTER > 0 55 #include <net/bpf.h> 56 #endif 57 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/if_alcreg.h> 66 67 int alc_match(struct device *, void *, void *); 68 void alc_attach(struct device *, struct device *, void *); 69 int alc_detach(struct device *, int); 70 int alc_activate(struct device *, int); 71 72 int alc_init(struct ifnet *); 73 void alc_start(struct ifnet *); 74 int alc_ioctl(struct ifnet *, u_long, caddr_t); 75 void alc_watchdog(struct ifnet *); 76 int alc_mediachange(struct ifnet *); 77 void alc_mediastatus(struct ifnet *, struct ifmediareq *); 78 79 void alc_aspm(struct alc_softc *, int, uint64_t); 80 void alc_aspm_813x(struct alc_softc *, uint64_t); 81 void alc_aspm_816x(struct alc_softc *, int); 82 void alc_disable_l0s_l1(struct alc_softc *); 83 int alc_dma_alloc(struct alc_softc *); 84 void alc_dma_free(struct alc_softc *); 85 int alc_encap(struct alc_softc *, struct mbuf *); 86 void alc_get_macaddr(struct alc_softc *); 87 void alc_get_macaddr_813x(struct alc_softc *); 88 void alc_get_macaddr_816x(struct alc_softc *); 89 void alc_get_macaddr_par(struct alc_softc *); 90 void alc_init_cmb(struct alc_softc *); 91 void alc_init_rr_ring(struct alc_softc *); 92 int alc_init_rx_ring(struct alc_softc *); 93 void alc_init_smb(struct alc_softc *); 94 void alc_init_tx_ring(struct alc_softc *); 95 int alc_intr(void *); 96 void alc_mac_config(struct alc_softc *); 97 int alc_mii_readreg_813x(struct device *, int, int); 98 int alc_mii_readreg_816x(struct device *, int, int); 99 void alc_mii_writereg_813x(struct device *, int, int, int); 100 void alc_mii_writereg_816x(struct device *, int, int, int); 101 void alc_dsp_fixup(struct alc_softc *, int); 102 int alc_miibus_readreg(struct device *, int, int); 103 void alc_miibus_statchg(struct device *); 104 void alc_miibus_writereg(struct device *, int, int, int); 105 int alc_miidbg_readreg(struct alc_softc *, int); 106 void alc_miidbg_writereg(struct alc_softc *, int, int); 107 int alc_miiext_readreg(struct alc_softc *, int, int); 108 void alc_miiext_writereg(struct alc_softc *, int, int, int); 109 void alc_phy_reset_813x(struct alc_softc *); 110 void alc_phy_reset_816x(struct alc_softc *); 111 int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 112 void alc_phy_down(struct alc_softc *); 113 void alc_phy_reset(struct alc_softc *); 114 void alc_reset(struct alc_softc *); 115 void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 116 int alc_rxintr(struct alc_softc *); 117 void alc_iff(struct alc_softc *); 118 void alc_rxvlan(struct alc_softc *); 119 void alc_start_queue(struct alc_softc *); 120 void alc_stats_clear(struct alc_softc *); 121 void alc_stats_update(struct alc_softc *); 122 void alc_stop(struct alc_softc *); 123 void alc_stop_mac(struct alc_softc *); 124 void alc_stop_queue(struct alc_softc *); 125 void alc_tick(void *); 126 void alc_txeof(struct alc_softc *); 127 void alc_init_pcie(struct alc_softc *, int); 128 void alc_config_msi(struct alc_softc *); 129 int alc_dma_alloc(struct alc_softc *); 130 void alc_dma_free(struct alc_softc *); 131 int alc_encap(struct alc_softc *, struct mbuf *); 132 void alc_osc_reset(struct alc_softc *); 133 134 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 135 136 const struct pci_matchid alc_devices[] = { 137 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1C }, 138 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C }, 139 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D }, 140 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D_1 }, 141 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_1 }, 142 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_2 }, 143 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8161 }, 144 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8162 }, 145 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8171 }, 146 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8172 }, 147 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2200 }, 148 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2400 }, 149 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2500 } 150 }; 151 152 struct cfattach alc_ca = { 153 sizeof (struct alc_softc), alc_match, alc_attach, alc_detach, 154 alc_activate 155 }; 156 157 struct cfdriver alc_cd = { 158 NULL, "alc", DV_IFNET 159 }; 160 161 int alcdebug = 0; 162 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 163 164 #define ALC_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) 165 166 int 167 alc_miibus_readreg(struct device *dev, int phy, int reg) 168 { 169 struct alc_softc *sc = (struct alc_softc *)dev; 170 uint32_t v; 171 172 if (phy != sc->alc_phyaddr) 173 return (0); 174 175 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 176 v = alc_mii_readreg_816x(dev, phy, reg); 177 else 178 v = alc_mii_readreg_813x(dev, phy, reg); 179 180 return (v); 181 } 182 183 int 184 alc_mii_readreg_813x(struct device *dev, int phy, int reg) 185 { 186 struct alc_softc *sc = (struct alc_softc *)dev; 187 uint32_t v; 188 int i; 189 190 /* 191 * For AR8132 fast ethernet controller, do not report 1000baseT 192 * capability to mii(4). Even though AR8132 uses the same 193 * model/revision number of F1 gigabit PHY, the PHY has no 194 * ability to establish 1000baseT link. 195 */ 196 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 197 reg == MII_EXTSR) 198 return (0); 199 200 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 201 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 202 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 203 DELAY(5); 204 v = CSR_READ_4(sc, ALC_MDIO); 205 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 206 break; 207 } 208 209 if (i == 0) { 210 printf("%s: phy read timeout: phy %d, reg %d\n", 211 sc->sc_dev.dv_xname, phy, reg); 212 return (0); 213 } 214 215 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 216 } 217 218 int 219 alc_mii_readreg_816x(struct device *dev, int phy, int reg) 220 { 221 struct alc_softc *sc = (struct alc_softc *)dev; 222 uint32_t clk, v; 223 int i; 224 225 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 226 clk = MDIO_CLK_25_128; 227 else 228 clk = MDIO_CLK_25_4; 229 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 230 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 231 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 232 DELAY(5); 233 v = CSR_READ_4(sc, ALC_MDIO); 234 if ((v & MDIO_OP_BUSY) == 0) 235 break; 236 } 237 238 if (i == 0) { 239 printf("%s: phy read timeout: phy %d, reg %d\n", 240 sc->sc_dev.dv_xname, phy, reg); 241 return (0); 242 } 243 244 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 245 } 246 247 void 248 alc_miibus_writereg(struct device *dev, int phy, int reg, int val) 249 { 250 struct alc_softc *sc = (struct alc_softc *)dev; 251 252 if (phy != sc->alc_phyaddr) 253 return; 254 255 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 256 alc_mii_writereg_816x(dev, phy, reg, val); 257 else 258 alc_mii_writereg_813x(dev, phy, reg, val); 259 } 260 261 void 262 alc_mii_writereg_813x(struct device *dev, int phy, int reg, int val) 263 { 264 struct alc_softc *sc = (struct alc_softc *)dev; 265 uint32_t v; 266 int i; 267 268 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 269 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 270 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 271 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 272 DELAY(5); 273 v = CSR_READ_4(sc, ALC_MDIO); 274 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 275 break; 276 } 277 278 if (i == 0) 279 printf("%s: phy write timeout: phy %d, reg %d\n", 280 sc->sc_dev.dv_xname, phy, reg); 281 } 282 283 void 284 alc_mii_writereg_816x(struct device *dev, int phy, int reg, int val) 285 { 286 struct alc_softc *sc = (struct alc_softc *)dev; 287 uint32_t clk, v; 288 int i; 289 290 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 291 clk = MDIO_CLK_25_128; 292 else 293 clk = MDIO_CLK_25_4; 294 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 295 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 296 MDIO_SUP_PREAMBLE | clk); 297 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 298 DELAY(5); 299 v = CSR_READ_4(sc, ALC_MDIO); 300 if ((v & MDIO_OP_BUSY) == 0) 301 break; 302 } 303 304 if (i == 0) 305 printf("%s: phy write timeout: phy %d, reg %d\n", 306 sc->sc_dev.dv_xname, phy, reg); 307 } 308 309 void 310 alc_miibus_statchg(struct device *dev) 311 { 312 struct alc_softc *sc = (struct alc_softc *)dev; 313 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 314 struct mii_data *mii = &sc->sc_miibus; 315 uint32_t reg; 316 317 if ((ifp->if_flags & IFF_RUNNING) == 0) 318 return; 319 320 sc->alc_flags &= ~ALC_FLAG_LINK; 321 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 322 (IFM_ACTIVE | IFM_AVALID)) { 323 switch (IFM_SUBTYPE(mii->mii_media_active)) { 324 case IFM_10_T: 325 case IFM_100_TX: 326 sc->alc_flags |= ALC_FLAG_LINK; 327 break; 328 case IFM_1000_T: 329 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 330 sc->alc_flags |= ALC_FLAG_LINK; 331 break; 332 default: 333 break; 334 } 335 } 336 /* Stop Rx/Tx MACs. */ 337 alc_stop_mac(sc); 338 339 /* Program MACs with resolved speed/duplex/flow-control. */ 340 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 341 alc_start_queue(sc); 342 alc_mac_config(sc); 343 /* Re-enable Tx/Rx MACs. */ 344 reg = CSR_READ_4(sc, ALC_MAC_CFG); 345 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 346 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 347 } 348 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 349 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 350 } 351 352 int 353 alc_miidbg_readreg(struct alc_softc *sc, int reg) 354 { 355 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 356 reg); 357 return (alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 358 ALC_MII_DBG_DATA)); 359 } 360 361 362 void 363 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 364 { 365 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 366 reg); 367 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 368 val); 369 } 370 371 int 372 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 373 { 374 uint32_t clk, v; 375 int i; 376 377 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 378 EXT_MDIO_DEVADDR(devaddr)); 379 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 380 clk = MDIO_CLK_25_128; 381 else 382 clk = MDIO_CLK_25_4; 383 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 384 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 385 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 386 DELAY(5); 387 v = CSR_READ_4(sc, ALC_MDIO); 388 if ((v & MDIO_OP_BUSY) == 0) 389 break; 390 } 391 392 if (i == 0) { 393 printf("%s: phy ext read timeout: phy %d, reg %d\n", 394 sc->sc_dev.dv_xname, devaddr, reg); 395 return (0); 396 } 397 398 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 399 } 400 401 void 402 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 403 { 404 uint32_t clk, v; 405 int i; 406 407 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 408 EXT_MDIO_DEVADDR(devaddr)); 409 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 410 clk = MDIO_CLK_25_128; 411 else 412 clk = MDIO_CLK_25_4; 413 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 414 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 415 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 416 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 417 DELAY(5); 418 v = CSR_READ_4(sc, ALC_MDIO); 419 if ((v & MDIO_OP_BUSY) == 0) 420 break; 421 } 422 423 if (i == 0) 424 printf("%s: phy ext write timeout: phy %d, reg %d\n", 425 sc->sc_dev.dv_xname, devaddr, reg); 426 } 427 428 void 429 alc_dsp_fixup(struct alc_softc *sc, int media) 430 { 431 uint16_t agc, len, val; 432 433 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 434 return; 435 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 436 return; 437 438 /* 439 * Vendor PHY magic. 440 * 1000BT/AZ, wrong cable length 441 */ 442 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 443 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 444 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 445 EXT_CLDCTL6_CAB_LEN_MASK; 446 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 447 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 448 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 449 agc > DBG_AGC_LONG1G_LIMT) || 450 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 451 agc > DBG_AGC_LONG1G_LIMT)) { 452 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 453 DBG_AZ_ANADECT_LONG); 454 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 455 MII_EXT_ANEG_AFE); 456 val |= ANEG_AFEE_10BT_100M_TH; 457 alc_miiext_writereg(sc, MII_EXT_ANEG, 458 MII_EXT_ANEG_AFE, val); 459 } else { 460 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 461 DBG_AZ_ANADECT_DEFAULT); 462 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 463 MII_EXT_ANEG_AFE); 464 val &= ~ANEG_AFEE_10BT_100M_TH; 465 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 466 val); 467 } 468 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 469 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 470 if (media == IFM_1000_T) { 471 /* 472 * Giga link threshold, raise the tolerance of 473 * noise 50%. 474 */ 475 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 476 val &= ~DBG_MSE20DB_TH_MASK; 477 val |= (DBG_MSE20DB_TH_HI << 478 DBG_MSE20DB_TH_SHIFT); 479 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 480 } else if (media == IFM_100_TX) 481 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 482 DBG_MSE16DB_UP); 483 } 484 } else { 485 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 486 val &= ~ANEG_AFEE_10BT_100M_TH; 487 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 488 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 489 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 490 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 491 DBG_MSE16DB_DOWN); 492 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 493 val &= ~DBG_MSE20DB_TH_MASK; 494 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 495 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 496 } 497 } 498 } 499 500 void 501 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 502 { 503 struct alc_softc *sc = ifp->if_softc; 504 struct mii_data *mii = &sc->sc_miibus; 505 506 if ((ifp->if_flags & IFF_UP) == 0) 507 return; 508 509 mii_pollstat(mii); 510 ifmr->ifm_status = mii->mii_media_status; 511 ifmr->ifm_active = mii->mii_media_active; 512 } 513 514 int 515 alc_mediachange(struct ifnet *ifp) 516 { 517 struct alc_softc *sc = ifp->if_softc; 518 struct mii_data *mii = &sc->sc_miibus; 519 int error; 520 521 if (mii->mii_instance != 0) { 522 struct mii_softc *miisc; 523 524 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 525 mii_phy_reset(miisc); 526 } 527 error = mii_mediachg(mii); 528 529 return (error); 530 } 531 532 int 533 alc_match(struct device *dev, void *match, void *aux) 534 { 535 return pci_matchbyid((struct pci_attach_args *)aux, alc_devices, 536 nitems(alc_devices)); 537 } 538 539 void 540 alc_get_macaddr(struct alc_softc *sc) 541 { 542 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 543 alc_get_macaddr_816x(sc); 544 else 545 alc_get_macaddr_813x(sc); 546 } 547 548 void 549 alc_get_macaddr_813x(struct alc_softc *sc) 550 { 551 uint32_t opt; 552 uint16_t val; 553 int eeprom, i; 554 555 eeprom = 0; 556 opt = CSR_READ_4(sc, ALC_OPT_CFG); 557 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 558 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 559 /* 560 * EEPROM found, let TWSI reload EEPROM configuration. 561 * This will set ethernet address of controller. 562 */ 563 eeprom++; 564 switch (sc->sc_product) { 565 case PCI_PRODUCT_ATTANSIC_L1C: 566 case PCI_PRODUCT_ATTANSIC_L2C: 567 if ((opt & OPT_CFG_CLK_ENB) == 0) { 568 opt |= OPT_CFG_CLK_ENB; 569 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 570 CSR_READ_4(sc, ALC_OPT_CFG); 571 DELAY(1000); 572 } 573 break; 574 case PCI_PRODUCT_ATTANSIC_L1D: 575 case PCI_PRODUCT_ATTANSIC_L1D_1: 576 case PCI_PRODUCT_ATTANSIC_L2C_1: 577 case PCI_PRODUCT_ATTANSIC_L2C_2: 578 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 579 ALC_MII_DBG_ADDR, 0x00); 580 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 581 ALC_MII_DBG_DATA); 582 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 583 ALC_MII_DBG_DATA, val & 0xFF7F); 584 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 585 ALC_MII_DBG_ADDR, 0x3B); 586 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 587 ALC_MII_DBG_DATA); 588 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 589 ALC_MII_DBG_DATA, val | 0x0008); 590 DELAY(20); 591 break; 592 } 593 594 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 595 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 596 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 597 CSR_READ_4(sc, ALC_WOL_CFG); 598 599 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 600 TWSI_CFG_SW_LD_START); 601 for (i = 100; i > 0; i--) { 602 DELAY(1000); 603 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 604 TWSI_CFG_SW_LD_START) == 0) 605 break; 606 } 607 if (i == 0) 608 printf("%s: reloading EEPROM timeout!\n", 609 sc->sc_dev.dv_xname); 610 } else { 611 if (alcdebug) 612 printf("%s: EEPROM not found!\n", sc->sc_dev.dv_xname); 613 } 614 if (eeprom != 0) { 615 switch (sc->sc_product) { 616 case PCI_PRODUCT_ATTANSIC_L1C: 617 case PCI_PRODUCT_ATTANSIC_L2C: 618 if ((opt & OPT_CFG_CLK_ENB) != 0) { 619 opt &= ~OPT_CFG_CLK_ENB; 620 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 621 CSR_READ_4(sc, ALC_OPT_CFG); 622 DELAY(1000); 623 } 624 break; 625 case PCI_PRODUCT_ATTANSIC_L1D: 626 case PCI_PRODUCT_ATTANSIC_L1D_1: 627 case PCI_PRODUCT_ATTANSIC_L2C_1: 628 case PCI_PRODUCT_ATTANSIC_L2C_2: 629 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 630 ALC_MII_DBG_ADDR, 0x00); 631 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 632 ALC_MII_DBG_DATA); 633 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 634 ALC_MII_DBG_DATA, val | 0x0080); 635 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 636 ALC_MII_DBG_ADDR, 0x3B); 637 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 638 ALC_MII_DBG_DATA); 639 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 640 ALC_MII_DBG_DATA, val & 0xFFF7); 641 DELAY(20); 642 break; 643 } 644 } 645 646 alc_get_macaddr_par(sc); 647 } 648 649 void 650 alc_get_macaddr_816x(struct alc_softc *sc) 651 { 652 uint32_t reg; 653 int i, reloaded; 654 655 reloaded = 0; 656 /* Try to reload station address via TWSI. */ 657 for (i = 100; i > 0; i--) { 658 reg = CSR_READ_4(sc, ALC_SLD); 659 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 660 break; 661 DELAY(1000); 662 } 663 if (i != 0) { 664 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 665 for (i = 100; i > 0; i--) { 666 DELAY(1000); 667 reg = CSR_READ_4(sc, ALC_SLD); 668 if ((reg & SLD_START) == 0) 669 break; 670 } 671 if (i != 0) 672 reloaded++; 673 else if (alcdebug) 674 printf("%s: reloading station address via TWSI timed" 675 "out!\n", sc->sc_dev.dv_xname); 676 } 677 678 /* Try to reload station address from EEPROM or FLASH. */ 679 if (reloaded == 0) { 680 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 681 if ((reg & (EEPROM_LD_EEPROM_EXIST | 682 EEPROM_LD_FLASH_EXIST)) != 0) { 683 for (i = 100; i > 0; i--) { 684 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 685 if ((reg & (EEPROM_LD_PROGRESS | 686 EEPROM_LD_START)) == 0) 687 break; 688 DELAY(1000); 689 } 690 if (i != 0) { 691 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 692 EEPROM_LD_START); 693 for (i = 100; i > 0; i--) { 694 DELAY(1000); 695 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 696 if ((reg & EEPROM_LD_START) == 0) 697 break; 698 } 699 } else if (alcdebug) 700 printf("%s: reloading EEPROM/FLASH timed out!\n", 701 sc->sc_dev.dv_xname); 702 } 703 } 704 705 alc_get_macaddr_par(sc); 706 } 707 708 void 709 alc_get_macaddr_par(struct alc_softc *sc) 710 { 711 uint32_t ea[2]; 712 713 ea[0] = CSR_READ_4(sc, ALC_PAR0); 714 ea[1] = CSR_READ_4(sc, ALC_PAR1); 715 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 716 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 717 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 718 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 719 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 720 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 721 } 722 723 void 724 alc_disable_l0s_l1(struct alc_softc *sc) 725 { 726 uint32_t pmcfg; 727 728 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 729 /* Another magic from vendor. */ 730 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 731 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 732 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 733 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 734 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 735 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 736 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 737 } 738 } 739 740 void 741 alc_phy_reset(struct alc_softc *sc) 742 { 743 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 744 alc_phy_reset_816x(sc); 745 else 746 alc_phy_reset_813x(sc); 747 } 748 749 void 750 alc_phy_reset_813x(struct alc_softc *sc) 751 { 752 uint16_t data; 753 754 /* Reset magic from Linux. */ 755 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 756 CSR_READ_2(sc, ALC_GPHY_CFG); 757 DELAY(10 * 1000); 758 759 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 760 GPHY_CFG_SEL_ANA_RESET); 761 CSR_READ_2(sc, ALC_GPHY_CFG); 762 DELAY(10 * 1000); 763 764 /* DSP fixup, Vendor magic. */ 765 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { 766 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 767 ALC_MII_DBG_ADDR, 0x000A); 768 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 769 ALC_MII_DBG_DATA); 770 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 771 ALC_MII_DBG_DATA, data & 0xDFFF); 772 } 773 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 774 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 775 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 776 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) { 777 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 778 ALC_MII_DBG_ADDR, 0x003B); 779 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 780 ALC_MII_DBG_DATA); 781 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 782 ALC_MII_DBG_DATA, data & 0xFFF7); 783 DELAY(20 * 1000); 784 } 785 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D) { 786 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 787 ALC_MII_DBG_ADDR, 0x0029); 788 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 789 ALC_MII_DBG_DATA, 0x929D); 790 } 791 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C || 792 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C || 793 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 794 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) { 795 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 796 ALC_MII_DBG_ADDR, 0x0029); 797 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 798 ALC_MII_DBG_DATA, 0xB6DD); 799 } 800 801 /* Load DSP codes, vendor magic. */ 802 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 803 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 804 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 805 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 806 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 807 ALC_MII_DBG_DATA, data); 808 809 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 810 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 811 ANA_SERDES_EN_LCKDT; 812 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 813 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 814 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 815 ALC_MII_DBG_DATA, data); 816 817 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 818 ANA_LONG_CABLE_TH_100_MASK) | 819 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 820 ANA_SHORT_CABLE_TH_100_SHIFT) | 821 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 822 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 823 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 824 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 825 ALC_MII_DBG_DATA, data); 826 827 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 828 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 829 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 830 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 831 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 832 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 833 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 834 ALC_MII_DBG_DATA, data); 835 836 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 837 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 838 ANA_OEN_125M; 839 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 840 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 841 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 842 ALC_MII_DBG_DATA, data); 843 DELAY(1000); 844 845 /* Disable hibernation. */ 846 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 847 0x0029); 848 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 849 ALC_MII_DBG_DATA); 850 data &= ~0x8000; 851 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 852 data); 853 854 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 855 0x000B); 856 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 857 ALC_MII_DBG_DATA); 858 data &= ~0x8000; 859 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 860 data); 861 } 862 863 void 864 alc_phy_reset_816x(struct alc_softc *sc) 865 { 866 uint32_t val; 867 868 val = CSR_READ_4(sc, ALC_GPHY_CFG); 869 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 870 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 871 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 872 val |= GPHY_CFG_SEL_ANA_RESET; 873 /* Disable PHY hibernation. */ 874 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 875 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 876 DELAY(10); 877 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 878 DELAY(800); 879 /* Vendor PHY magic. */ 880 /* Disable PHY hibernation. */ 881 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 882 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 883 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, DBG_HIBNEG_DEFAULT & 884 ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 885 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 886 /* XXX Disable EEE. */ 887 val = CSR_READ_4(sc, ALC_LPI_CTL); 888 val &= ~LPI_CTL_ENB; 889 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 890 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 891 /* PHY power saving. */ 892 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 893 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 894 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 895 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 896 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 897 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 898 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 899 /* RTL8139C, 120m issue. */ 900 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 901 ANEG_NLP78_120M_DEFAULT); 902 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 903 ANEG_S3DIG10_DEFAULT); 904 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 905 /* Turn off half amplitude. */ 906 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 907 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 908 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 909 /* Turn off Green feature. */ 910 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 911 val |= DBG_GREENCFG2_BP_GREEN; 912 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 913 /* Turn off half bias. */ 914 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 915 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 916 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 917 } 918 } 919 920 void 921 alc_phy_down(struct alc_softc *sc) 922 { 923 uint32_t gphy; 924 925 switch (sc->sc_product) { 926 case PCI_PRODUCT_ATTANSIC_AR8161: 927 case PCI_PRODUCT_ATTANSIC_E2200: 928 case PCI_PRODUCT_ATTANSIC_E2400: 929 case PCI_PRODUCT_ATTANSIC_E2500: 930 case PCI_PRODUCT_ATTANSIC_AR8162: 931 case PCI_PRODUCT_ATTANSIC_AR8171: 932 case PCI_PRODUCT_ATTANSIC_AR8172: 933 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 934 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 935 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 936 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 937 GPHY_CFG_SEL_ANA_RESET; 938 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 939 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 940 break; 941 case PCI_PRODUCT_ATTANSIC_L1D: 942 case PCI_PRODUCT_ATTANSIC_L1D_1: 943 case PCI_PRODUCT_ATTANSIC_L2C_1: 944 case PCI_PRODUCT_ATTANSIC_L2C_2: 945 /* 946 * GPHY power down caused more problems on AR8151 v2.0. 947 * When driver is reloaded after GPHY power down, 948 * accesses to PHY/MAC registers hung the system. Only 949 * cold boot recovered from it. I'm not sure whether 950 * AR8151 v1.0 also requires this one though. I don't 951 * have AR8151 v1.0 controller in hand. 952 * The only option left is to isolate the PHY and 953 * initiates power down the PHY which in turn saves 954 * more power when driver is unloaded. 955 */ 956 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 957 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 958 break; 959 default: 960 /* Force PHY down. */ 961 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 962 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 963 GPHY_CFG_PWDOWN_HW); 964 DELAY(1000); 965 break; 966 } 967 } 968 969 void 970 alc_aspm(struct alc_softc *sc, int init, uint64_t media) 971 { 972 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 973 alc_aspm_816x(sc, init); 974 else 975 alc_aspm_813x(sc, media); 976 } 977 978 void 979 alc_aspm_813x(struct alc_softc *sc, uint64_t media) 980 { 981 uint32_t pmcfg; 982 uint16_t linkcfg; 983 984 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 985 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 986 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 987 linkcfg = CSR_READ_2(sc, sc->alc_expcap + PCI_PCIE_LCSR); 988 else 989 linkcfg = 0; 990 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 991 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 992 pmcfg |= PM_CFG_MAC_ASPM_CHK; 993 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 994 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 995 996 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 997 /* Disable extended sync except AR8152 B v1.0 */ 998 linkcfg &= ~0x80; 999 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && 1000 sc->alc_rev == ATHEROS_AR8152_B_V10) 1001 linkcfg |= 0x80; 1002 CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR, linkcfg); 1003 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1004 PM_CFG_HOTRST); 1005 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1006 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1007 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1008 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1009 PM_CFG_PM_REQ_TIMER_SHIFT); 1010 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1011 } 1012 1013 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1014 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1015 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1016 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1017 pmcfg |= PM_CFG_ASPM_L1_ENB; 1018 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1019 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) 1020 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1021 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1022 PM_CFG_SERDES_PLL_L1_ENB | 1023 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1024 pmcfg |= PM_CFG_CLK_SWH_L1; 1025 if (media == IFM_100_TX || media == IFM_1000_T) { 1026 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1027 switch (sc->sc_product) { 1028 case PCI_PRODUCT_ATTANSIC_L2C_1: 1029 pmcfg |= (7 << 1030 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1031 break; 1032 case PCI_PRODUCT_ATTANSIC_L1D_1: 1033 case PCI_PRODUCT_ATTANSIC_L2C_2: 1034 pmcfg |= (4 << 1035 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1036 break; 1037 default: 1038 pmcfg |= (15 << 1039 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1040 break; 1041 } 1042 } 1043 } else { 1044 pmcfg |= PM_CFG_SERDES_L1_ENB | 1045 PM_CFG_SERDES_PLL_L1_ENB | 1046 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1047 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1048 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1049 } 1050 } else { 1051 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1052 PM_CFG_SERDES_PLL_L1_ENB); 1053 pmcfg |= PM_CFG_CLK_SWH_L1; 1054 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1055 pmcfg |= PM_CFG_ASPM_L1_ENB; 1056 } 1057 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1058 } 1059 1060 void 1061 alc_aspm_816x(struct alc_softc *sc, int init) 1062 { 1063 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1064 uint32_t pmcfg; 1065 1066 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1067 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1068 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1069 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1070 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1071 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1072 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1073 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1074 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1075 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1076 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1077 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1078 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1079 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1080 (sc->alc_rev & 0x01) != 0) 1081 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1082 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1083 /* Link up, enable both L0s, L1s. */ 1084 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1085 PM_CFG_MAC_ASPM_CHK; 1086 } else { 1087 if (init != 0) 1088 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1089 PM_CFG_MAC_ASPM_CHK; 1090 else if ((ifp->if_flags & IFF_RUNNING) != 0) 1091 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1092 } 1093 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1094 } 1095 1096 void 1097 alc_init_pcie(struct alc_softc *sc, int base) 1098 { 1099 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1100 uint32_t cap, ctl, val; 1101 int state; 1102 1103 /* Clear data link and flow-control protocol error. */ 1104 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1105 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1106 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1107 1108 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1109 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1110 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1111 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1112 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1113 PCIE_PHYMISC_FORCE_RCV_DET); 1114 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && 1115 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1116 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1117 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1118 PCIE_PHYMISC2_SERDES_TH_MASK); 1119 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1120 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1121 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1122 } 1123 /* Disable ASPM L0S and L1. */ 1124 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1125 base + PCI_PCIE_LCAP) >> 16; 1126 if ((cap & 0x00000c00) != 0) { 1127 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1128 base + PCI_PCIE_LCSR) >> 16; 1129 if ((ctl & 0x08) != 0) 1130 sc->alc_rcb = DMA_CFG_RCB_128; 1131 if (alcdebug) 1132 printf("%s: RCB %u bytes\n", 1133 sc->sc_dev.dv_xname, 1134 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1135 state = ctl & 0x03; 1136 if (state & 0x01) 1137 sc->alc_flags |= ALC_FLAG_L0S; 1138 if (state & 0x02) 1139 sc->alc_flags |= ALC_FLAG_L1S; 1140 if (alcdebug) 1141 printf("%s: ASPM %s %s\n", 1142 sc->sc_dev.dv_xname, 1143 aspm_state[state], 1144 state == 0 ? "disabled" : "enabled"); 1145 alc_disable_l0s_l1(sc); 1146 } 1147 } else { 1148 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1149 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1150 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1151 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1152 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1153 (sc->alc_rev & 0x01) != 0) { 1154 if ((val & MASTER_WAKEN_25M) == 0 || 1155 (val & MASTER_CLK_SEL_DIS) == 0) { 1156 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1157 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1158 } 1159 } else { 1160 if ((val & MASTER_WAKEN_25M) == 0 || 1161 (val & MASTER_CLK_SEL_DIS) != 0) { 1162 val |= MASTER_WAKEN_25M; 1163 val &= ~MASTER_CLK_SEL_DIS; 1164 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1165 } 1166 } 1167 } 1168 } 1169 1170 void 1171 alc_config_msi(struct alc_softc *sc) 1172 { 1173 uint32_t ctl, mod; 1174 1175 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1176 /* 1177 * It seems interrupt moderation is controlled by 1178 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1179 * Driver uses RX interrupt moderation parameter to 1180 * program ALC_MSI_RETRANS_TIMER register. 1181 */ 1182 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1183 ctl &= ~MSI_RETRANS_TIMER_MASK; 1184 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1185 mod = ALC_USECS(sc->alc_int_rx_mod); 1186 if (mod == 0) 1187 mod = 1; 1188 ctl |= mod; 1189 if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1190 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1191 MSI_RETRANS_MASK_SEL_LINE); 1192 else 1193 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1194 } 1195 } 1196 1197 void 1198 alc_attach(struct device *parent, struct device *self, void *aux) 1199 { 1200 struct alc_softc *sc = (struct alc_softc *)self; 1201 struct pci_attach_args *pa = aux; 1202 pci_chipset_tag_t pc = pa->pa_pc; 1203 pci_intr_handle_t ih; 1204 const char *intrstr; 1205 struct ifnet *ifp; 1206 pcireg_t memtype; 1207 uint16_t burst; 1208 int base, error = 0; 1209 1210 /* Set PHY address. */ 1211 sc->alc_phyaddr = ALC_PHY_ADDR; 1212 1213 /* Get PCI and chip id/revision. */ 1214 sc->sc_product = PCI_PRODUCT(pa->pa_id); 1215 sc->alc_rev = PCI_REVISION(pa->pa_class); 1216 1217 /* 1218 * One odd thing is AR8132 uses the same PHY hardware(F1 1219 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1220 * the PHY supports 1000Mbps but that's not true. The PHY 1221 * used in AR8132 can't establish gigabit link even if it 1222 * shows the same PHY model/revision number of AR8131. 1223 */ 1224 switch (sc->sc_product) { 1225 case PCI_PRODUCT_ATTANSIC_E2200: 1226 case PCI_PRODUCT_ATTANSIC_E2400: 1227 case PCI_PRODUCT_ATTANSIC_E2500: 1228 sc->alc_flags |= ALC_FLAG_E2X00; 1229 /* FALLTHROUGH */ 1230 case PCI_PRODUCT_ATTANSIC_AR8161: 1231 if (AR816X_REV(sc->alc_rev) == 0) 1232 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1233 /* FALLTHROUGH */ 1234 case PCI_PRODUCT_ATTANSIC_AR8171: 1235 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1236 break; 1237 case PCI_PRODUCT_ATTANSIC_AR8162: 1238 case PCI_PRODUCT_ATTANSIC_AR8172: 1239 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1240 break; 1241 case PCI_PRODUCT_ATTANSIC_L2C_1: 1242 case PCI_PRODUCT_ATTANSIC_L2C_2: 1243 sc->alc_flags |= ALC_FLAG_APS; 1244 /* FALLTHROUGH */ 1245 case PCI_PRODUCT_ATTANSIC_L2C: 1246 sc->alc_flags |= ALC_FLAG_FASTETHER; 1247 break; 1248 case PCI_PRODUCT_ATTANSIC_L1D: 1249 case PCI_PRODUCT_ATTANSIC_L1D_1: 1250 sc->alc_flags |= ALC_FLAG_APS; 1251 /* FALLTHROUGH */ 1252 default: 1253 break; 1254 } 1255 sc->alc_flags |= ALC_FLAG_JUMBO; 1256 1257 /* 1258 * Allocate IO memory 1259 */ 1260 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 1261 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 1262 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 1263 printf(": can't map mem space\n"); 1264 return; 1265 } 1266 1267 sc->alc_flags |= ALC_FLAG_MSI; 1268 if (pci_intr_map_msi(pa, &ih) != 0) { 1269 if (pci_intr_map(pa, &ih) != 0) { 1270 printf(": can't map interrupt\n"); 1271 goto fail; 1272 } 1273 sc->alc_flags &= ~ALC_FLAG_MSI; 1274 } 1275 1276 /* 1277 * Allocate IRQ 1278 */ 1279 intrstr = pci_intr_string(pc, ih); 1280 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc, 1281 sc->sc_dev.dv_xname); 1282 if (sc->sc_irq_handle == NULL) { 1283 printf(": could not establish interrupt"); 1284 if (intrstr != NULL) 1285 printf(" at %s", intrstr); 1286 printf("\n"); 1287 goto fail; 1288 } 1289 printf(": %s", intrstr); 1290 1291 alc_config_msi(sc); 1292 1293 sc->sc_dmat = pa->pa_dmat; 1294 sc->sc_pct = pa->pa_pc; 1295 sc->sc_pcitag = pa->pa_tag; 1296 1297 switch (sc->sc_product) { 1298 case PCI_PRODUCT_ATTANSIC_L1D: 1299 case PCI_PRODUCT_ATTANSIC_L1D_1: 1300 case PCI_PRODUCT_ATTANSIC_L2C_1: 1301 case PCI_PRODUCT_ATTANSIC_L2C_2: 1302 sc->alc_max_framelen = 6 * 1024; 1303 break; 1304 default: 1305 sc->alc_max_framelen = 9 * 1024; 1306 break; 1307 } 1308 1309 /* 1310 * It seems that AR813x/AR815x has silicon bug for SMB. In 1311 * addition, Atheros said that enabling SMB wouldn't improve 1312 * performance. However I think it's bad to access lots of 1313 * registers to extract MAC statistics. 1314 */ 1315 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1316 /* 1317 * Don't use Tx CMB. It is known to have silicon bug. 1318 */ 1319 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1320 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1321 MASTER_CHIP_REV_SHIFT; 1322 if (alcdebug) { 1323 printf("%s: PCI device revision : 0x%04x\n", 1324 sc->sc_dev.dv_xname, sc->alc_rev); 1325 printf("%s: Chip id/revision : 0x%04x\n", 1326 sc->sc_dev.dv_xname, sc->alc_chip_rev); 1327 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, 1328 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1329 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1330 } 1331 1332 /* Initialize DMA parameters. */ 1333 sc->alc_dma_rd_burst = 0; 1334 sc->alc_dma_wr_burst = 0; 1335 sc->alc_rcb = DMA_CFG_RCB_64; 1336 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 1337 &base, NULL)) { 1338 sc->alc_flags |= ALC_FLAG_PCIE; 1339 sc->alc_expcap = base; 1340 burst = CSR_READ_2(sc, base + PCI_PCIE_DCSR); 1341 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 1342 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 1343 if (alcdebug) { 1344 printf("%s: Read request size : %u bytes.\n", 1345 sc->sc_dev.dv_xname, 1346 alc_dma_burst[sc->alc_dma_rd_burst]); 1347 printf("%s: TLP payload size : %u bytes.\n", 1348 sc->sc_dev.dv_xname, 1349 alc_dma_burst[sc->alc_dma_wr_burst]); 1350 } 1351 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1352 sc->alc_dma_rd_burst = 3; 1353 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1354 sc->alc_dma_wr_burst = 3; 1355 /* 1356 * Force maximum payload size to 128 bytes for 1357 * E2200/E2400/E2500. 1358 * Otherwise it triggers DMA write error. 1359 */ 1360 if ((sc->alc_flags & ALC_FLAG_E2X00) != 0) 1361 sc->alc_dma_wr_burst = 0; 1362 alc_init_pcie(sc, base); 1363 } 1364 1365 /* Reset PHY. */ 1366 alc_phy_reset(sc); 1367 1368 /* Reset the ethernet controller. */ 1369 alc_stop_mac(sc); 1370 alc_reset(sc); 1371 1372 error = alc_dma_alloc(sc); 1373 if (error) 1374 goto fail; 1375 1376 /* Load station address. */ 1377 alc_get_macaddr(sc); 1378 1379 ifp = &sc->sc_arpcom.ac_if; 1380 ifp->if_softc = sc; 1381 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1382 ifp->if_ioctl = alc_ioctl; 1383 ifp->if_start = alc_start; 1384 ifp->if_watchdog = alc_watchdog; 1385 ifq_set_maxlen(&ifp->if_snd, ALC_TX_RING_CNT - 1); 1386 bcopy(sc->alc_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 1387 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1388 1389 ifp->if_capabilities = IFCAP_VLAN_MTU; 1390 1391 #ifdef ALC_CHECKSUM 1392 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1393 IFCAP_CSUM_UDPv4; 1394 #endif 1395 1396 #if NVLAN > 0 1397 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1398 #endif 1399 1400 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 1401 1402 /* Set up MII bus. */ 1403 sc->sc_miibus.mii_ifp = ifp; 1404 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 1405 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 1406 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 1407 1408 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 1409 alc_mediastatus); 1410 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 1411 MII_OFFSET_ANY, MIIF_DOPAUSE); 1412 1413 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 1414 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 1415 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 1416 0, NULL); 1417 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 1418 } else 1419 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 1420 1421 if_attach(ifp); 1422 ether_ifattach(ifp); 1423 1424 timeout_set(&sc->alc_tick_ch, alc_tick, sc); 1425 1426 return; 1427 fail: 1428 alc_dma_free(sc); 1429 if (sc->sc_irq_handle != NULL) 1430 pci_intr_disestablish(pc, sc->sc_irq_handle); 1431 if (sc->sc_mem_size) 1432 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1433 } 1434 1435 int 1436 alc_detach(struct device *self, int flags) 1437 { 1438 struct alc_softc *sc = (struct alc_softc *)self; 1439 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1440 int s; 1441 1442 s = splnet(); 1443 alc_stop(sc); 1444 splx(s); 1445 1446 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 1447 1448 /* Delete all remaining media. */ 1449 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 1450 1451 ether_ifdetach(ifp); 1452 if_detach(ifp); 1453 alc_dma_free(sc); 1454 1455 alc_phy_down(sc); 1456 if (sc->sc_irq_handle != NULL) { 1457 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1458 sc->sc_irq_handle = NULL; 1459 } 1460 1461 return (0); 1462 } 1463 1464 int 1465 alc_activate(struct device *self, int act) 1466 { 1467 struct alc_softc *sc = (struct alc_softc *)self; 1468 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1469 int rv = 0; 1470 1471 switch (act) { 1472 case DVACT_SUSPEND: 1473 if (ifp->if_flags & IFF_RUNNING) 1474 alc_stop(sc); 1475 rv = config_activate_children(self, act); 1476 break; 1477 case DVACT_RESUME: 1478 if (ifp->if_flags & IFF_UP) 1479 alc_init(ifp); 1480 break; 1481 default: 1482 rv = config_activate_children(self, act); 1483 break; 1484 } 1485 return (rv); 1486 } 1487 1488 int 1489 alc_dma_alloc(struct alc_softc *sc) 1490 { 1491 struct alc_txdesc *txd; 1492 struct alc_rxdesc *rxd; 1493 int nsegs, error, i; 1494 1495 /* 1496 * Create DMA stuffs for TX ring 1497 */ 1498 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 1499 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 1500 if (error) 1501 return (ENOBUFS); 1502 1503 /* Allocate DMA'able memory for TX ring */ 1504 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 1505 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 1506 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1507 if (error) { 1508 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 1509 sc->sc_dev.dv_xname); 1510 return (error); 1511 } 1512 1513 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 1514 nsegs, ALC_TX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_tx_ring, 1515 BUS_DMA_NOWAIT); 1516 if (error) 1517 return (ENOBUFS); 1518 1519 /* Load the DMA map for Tx ring. */ 1520 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 1521 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 1522 if (error) { 1523 printf("%s: could not load DMA'able memory for Tx ring.\n", 1524 sc->sc_dev.dv_xname); 1525 bus_dmamem_free(sc->sc_dmat, 1526 (bus_dma_segment_t *)&sc->alc_rdata.alc_tx_ring, 1); 1527 return (error); 1528 } 1529 1530 sc->alc_rdata.alc_tx_ring_paddr = 1531 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 1532 1533 /* 1534 * Create DMA stuffs for RX ring 1535 */ 1536 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1537 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1538 if (error) 1539 return (ENOBUFS); 1540 1541 /* Allocate DMA'able memory for RX ring */ 1542 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1543 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1544 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1545 if (error) { 1546 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1547 sc->sc_dev.dv_xname); 1548 return (error); 1549 } 1550 1551 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1552 nsegs, ALC_RX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rx_ring, 1553 BUS_DMA_NOWAIT); 1554 if (error) 1555 return (ENOBUFS); 1556 1557 /* Load the DMA map for Rx ring. */ 1558 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1559 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1560 if (error) { 1561 printf("%s: could not load DMA'able memory for Rx ring.\n", 1562 sc->sc_dev.dv_xname); 1563 bus_dmamem_free(sc->sc_dmat, 1564 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 1565 return (error); 1566 } 1567 1568 sc->alc_rdata.alc_rx_ring_paddr = 1569 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1570 1571 /* 1572 * Create DMA stuffs for RX return ring 1573 */ 1574 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1575 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1576 if (error) 1577 return (ENOBUFS); 1578 1579 /* Allocate DMA'able memory for RX return ring */ 1580 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1581 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1582 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1583 if (error) { 1584 printf("%s: could not allocate DMA'able memory for Rx " 1585 "return ring.\n", sc->sc_dev.dv_xname); 1586 return (error); 1587 } 1588 1589 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1590 nsegs, ALC_RR_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rr_ring, 1591 BUS_DMA_NOWAIT); 1592 if (error) 1593 return (ENOBUFS); 1594 1595 /* Load the DMA map for Rx return ring. */ 1596 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1597 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1598 if (error) { 1599 printf("%s: could not load DMA'able memory for Rx return ring." 1600 "\n", sc->sc_dev.dv_xname); 1601 bus_dmamem_free(sc->sc_dmat, 1602 (bus_dma_segment_t *)&sc->alc_rdata.alc_rr_ring, 1); 1603 return (error); 1604 } 1605 1606 sc->alc_rdata.alc_rr_ring_paddr = 1607 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1608 1609 /* 1610 * Create DMA stuffs for CMB block 1611 */ 1612 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1613 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1614 &sc->alc_cdata.alc_cmb_map); 1615 if (error) 1616 return (ENOBUFS); 1617 1618 /* Allocate DMA'able memory for CMB block */ 1619 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1620 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1621 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1622 if (error) { 1623 printf("%s: could not allocate DMA'able memory for " 1624 "CMB block\n", sc->sc_dev.dv_xname); 1625 return (error); 1626 } 1627 1628 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1629 nsegs, ALC_CMB_SZ, (caddr_t *)&sc->alc_rdata.alc_cmb, 1630 BUS_DMA_NOWAIT); 1631 if (error) 1632 return (ENOBUFS); 1633 1634 /* Load the DMA map for CMB block. */ 1635 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1636 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1637 BUS_DMA_WAITOK); 1638 if (error) { 1639 printf("%s: could not load DMA'able memory for CMB block\n", 1640 sc->sc_dev.dv_xname); 1641 bus_dmamem_free(sc->sc_dmat, 1642 (bus_dma_segment_t *)&sc->alc_rdata.alc_cmb, 1); 1643 return (error); 1644 } 1645 1646 sc->alc_rdata.alc_cmb_paddr = 1647 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1648 1649 /* 1650 * Create DMA stuffs for SMB block 1651 */ 1652 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1653 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1654 &sc->alc_cdata.alc_smb_map); 1655 if (error) 1656 return (ENOBUFS); 1657 1658 /* Allocate DMA'able memory for SMB block */ 1659 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1660 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1661 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1662 if (error) { 1663 printf("%s: could not allocate DMA'able memory for " 1664 "SMB block\n", sc->sc_dev.dv_xname); 1665 return (error); 1666 } 1667 1668 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1669 nsegs, ALC_SMB_SZ, (caddr_t *)&sc->alc_rdata.alc_smb, 1670 BUS_DMA_NOWAIT); 1671 if (error) 1672 return (ENOBUFS); 1673 1674 /* Load the DMA map for SMB block */ 1675 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1676 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1677 BUS_DMA_WAITOK); 1678 if (error) { 1679 printf("%s: could not load DMA'able memory for SMB block\n", 1680 sc->sc_dev.dv_xname); 1681 bus_dmamem_free(sc->sc_dmat, 1682 (bus_dma_segment_t *)&sc->alc_rdata.alc_smb, 1); 1683 return (error); 1684 } 1685 1686 sc->alc_rdata.alc_smb_paddr = 1687 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1688 1689 1690 /* Create DMA maps for Tx buffers. */ 1691 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1692 txd = &sc->alc_cdata.alc_txdesc[i]; 1693 txd->tx_m = NULL; 1694 txd->tx_dmamap = NULL; 1695 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1696 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1697 &txd->tx_dmamap); 1698 if (error) { 1699 printf("%s: could not create Tx dmamap.\n", 1700 sc->sc_dev.dv_xname); 1701 return (error); 1702 } 1703 } 1704 1705 /* Create DMA maps for Rx buffers. */ 1706 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1707 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1708 if (error) { 1709 printf("%s: could not create spare Rx dmamap.\n", 1710 sc->sc_dev.dv_xname); 1711 return (error); 1712 } 1713 1714 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1715 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1716 rxd->rx_m = NULL; 1717 rxd->rx_dmamap = NULL; 1718 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1719 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1720 if (error) { 1721 printf("%s: could not create Rx dmamap.\n", 1722 sc->sc_dev.dv_xname); 1723 return (error); 1724 } 1725 } 1726 1727 return (0); 1728 } 1729 1730 void 1731 alc_dma_free(struct alc_softc *sc) 1732 { 1733 struct alc_txdesc *txd; 1734 struct alc_rxdesc *rxd; 1735 int i; 1736 1737 /* Tx buffers */ 1738 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1739 txd = &sc->alc_cdata.alc_txdesc[i]; 1740 if (txd->tx_dmamap != NULL) { 1741 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1742 txd->tx_dmamap = NULL; 1743 } 1744 } 1745 /* Rx buffers */ 1746 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1747 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1748 if (rxd->rx_dmamap != NULL) { 1749 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1750 rxd->rx_dmamap = NULL; 1751 } 1752 } 1753 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1754 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1755 sc->alc_cdata.alc_rx_sparemap = NULL; 1756 } 1757 1758 /* Tx ring. */ 1759 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1760 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1761 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1762 sc->alc_rdata.alc_tx_ring != NULL) 1763 bus_dmamem_free(sc->sc_dmat, 1764 (bus_dma_segment_t *)sc->alc_rdata.alc_tx_ring, 1); 1765 sc->alc_rdata.alc_tx_ring = NULL; 1766 sc->alc_cdata.alc_tx_ring_map = NULL; 1767 1768 /* Rx ring. */ 1769 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1770 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1771 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1772 sc->alc_rdata.alc_rx_ring != NULL) 1773 bus_dmamem_free(sc->sc_dmat, 1774 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 1775 sc->alc_rdata.alc_rx_ring = NULL; 1776 sc->alc_cdata.alc_rx_ring_map = NULL; 1777 1778 /* Rx return ring. */ 1779 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1780 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1781 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1782 sc->alc_rdata.alc_rr_ring != NULL) 1783 bus_dmamem_free(sc->sc_dmat, 1784 (bus_dma_segment_t *)sc->alc_rdata.alc_rr_ring, 1); 1785 sc->alc_rdata.alc_rr_ring = NULL; 1786 sc->alc_cdata.alc_rr_ring_map = NULL; 1787 1788 /* CMB block */ 1789 if (sc->alc_cdata.alc_cmb_map != NULL) 1790 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1791 if (sc->alc_cdata.alc_cmb_map != NULL && 1792 sc->alc_rdata.alc_cmb != NULL) 1793 bus_dmamem_free(sc->sc_dmat, 1794 (bus_dma_segment_t *)sc->alc_rdata.alc_cmb, 1); 1795 sc->alc_rdata.alc_cmb = NULL; 1796 sc->alc_cdata.alc_cmb_map = NULL; 1797 1798 /* SMB block */ 1799 if (sc->alc_cdata.alc_smb_map != NULL) 1800 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1801 if (sc->alc_cdata.alc_smb_map != NULL && 1802 sc->alc_rdata.alc_smb != NULL) 1803 bus_dmamem_free(sc->sc_dmat, 1804 (bus_dma_segment_t *)sc->alc_rdata.alc_smb, 1); 1805 sc->alc_rdata.alc_smb = NULL; 1806 sc->alc_cdata.alc_smb_map = NULL; 1807 } 1808 1809 int 1810 alc_encap(struct alc_softc *sc, struct mbuf *m) 1811 { 1812 struct alc_txdesc *txd, *txd_last; 1813 struct tx_desc *desc; 1814 bus_dmamap_t map; 1815 uint32_t cflags, poff, vtag; 1816 int error, idx, prod; 1817 1818 cflags = vtag = 0; 1819 poff = 0; 1820 1821 prod = sc->alc_cdata.alc_tx_prod; 1822 txd = &sc->alc_cdata.alc_txdesc[prod]; 1823 txd_last = txd; 1824 map = txd->tx_dmamap; 1825 1826 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 1827 if (error != 0 && error != EFBIG) 1828 goto drop; 1829 if (error != 0) { 1830 if (m_defrag(m, M_DONTWAIT)) { 1831 error = ENOBUFS; 1832 goto drop; 1833 } 1834 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1835 BUS_DMA_NOWAIT); 1836 if (error != 0) 1837 goto drop; 1838 } 1839 1840 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1841 BUS_DMASYNC_PREWRITE); 1842 1843 desc = NULL; 1844 idx = 0; 1845 #if NVLAN > 0 1846 /* Configure VLAN hardware tag insertion. */ 1847 if (m->m_flags & M_VLANTAG) { 1848 vtag = htons(m->m_pkthdr.ether_vtag); 1849 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1850 cflags |= TD_INS_VLAN_TAG; 1851 } 1852 #endif 1853 /* Configure Tx checksum offload. */ 1854 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1855 cflags |= TD_CUSTOM_CSUM; 1856 /* Set checksum start offset. */ 1857 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1858 TD_PLOAD_OFFSET_MASK; 1859 } 1860 1861 for (; idx < map->dm_nsegs; idx++) { 1862 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1863 desc->len = 1864 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1865 desc->flags = htole32(cflags); 1866 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1867 sc->alc_cdata.alc_tx_cnt++; 1868 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1869 } 1870 1871 /* Update producer index. */ 1872 sc->alc_cdata.alc_tx_prod = prod; 1873 1874 /* Finally set EOP on the last descriptor. */ 1875 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1876 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1877 desc->flags |= htole32(TD_EOP); 1878 1879 /* Swap dmamap of the first and the last. */ 1880 txd = &sc->alc_cdata.alc_txdesc[prod]; 1881 map = txd_last->tx_dmamap; 1882 txd_last->tx_dmamap = txd->tx_dmamap; 1883 txd->tx_dmamap = map; 1884 txd->tx_m = m; 1885 1886 return (0); 1887 1888 drop: 1889 m_freem(m); 1890 return (error); 1891 } 1892 1893 void 1894 alc_start(struct ifnet *ifp) 1895 { 1896 struct alc_softc *sc = ifp->if_softc; 1897 struct mbuf *m; 1898 int enq = 0; 1899 1900 /* Reclaim transmitted frames. */ 1901 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1902 alc_txeof(sc); 1903 1904 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1905 return; 1906 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1907 return; 1908 if (ifq_empty(&ifp->if_snd)) 1909 return; 1910 1911 for (;;) { 1912 if (sc->alc_cdata.alc_tx_cnt + ALC_MAXTXSEGS >= 1913 ALC_TX_RING_CNT - 3) { 1914 ifq_set_oactive(&ifp->if_snd); 1915 break; 1916 } 1917 1918 m = ifq_dequeue(&ifp->if_snd); 1919 if (m == NULL) 1920 break; 1921 1922 if (alc_encap(sc, m) != 0) { 1923 ifp->if_oerrors++; 1924 continue; 1925 } 1926 enq++; 1927 1928 #if NBPFILTER > 0 1929 /* 1930 * If there's a BPF listener, bounce a copy of this frame 1931 * to him. 1932 */ 1933 if (ifp->if_bpf != NULL) 1934 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1935 #endif 1936 } 1937 1938 if (enq > 0) { 1939 /* Sync descriptors. */ 1940 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1941 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1942 BUS_DMASYNC_PREWRITE); 1943 /* Kick. Assume we're using normal Tx priority queue. */ 1944 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1945 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 1946 (uint16_t)sc->alc_cdata.alc_tx_prod); 1947 else 1948 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 1949 (sc->alc_cdata.alc_tx_prod << 1950 MBOX_TD_PROD_LO_IDX_SHIFT) & 1951 MBOX_TD_PROD_LO_IDX_MASK); 1952 /* Set a timeout in case the chip goes out to lunch. */ 1953 ifp->if_timer = ALC_TX_TIMEOUT; 1954 } 1955 } 1956 1957 void 1958 alc_watchdog(struct ifnet *ifp) 1959 { 1960 struct alc_softc *sc = ifp->if_softc; 1961 1962 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 1963 printf("%s: watchdog timeout (missed link)\n", 1964 sc->sc_dev.dv_xname); 1965 ifp->if_oerrors++; 1966 alc_init(ifp); 1967 return; 1968 } 1969 1970 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1971 ifp->if_oerrors++; 1972 alc_init(ifp); 1973 alc_start(ifp); 1974 } 1975 1976 int 1977 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1978 { 1979 struct alc_softc *sc = ifp->if_softc; 1980 struct mii_data *mii = &sc->sc_miibus; 1981 struct ifreq *ifr = (struct ifreq *)data; 1982 int s, error = 0; 1983 1984 s = splnet(); 1985 1986 switch (cmd) { 1987 case SIOCSIFADDR: 1988 ifp->if_flags |= IFF_UP; 1989 if (!(ifp->if_flags & IFF_RUNNING)) 1990 alc_init(ifp); 1991 break; 1992 1993 case SIOCSIFFLAGS: 1994 if (ifp->if_flags & IFF_UP) { 1995 if (ifp->if_flags & IFF_RUNNING) 1996 error = ENETRESET; 1997 else 1998 alc_init(ifp); 1999 } else { 2000 if (ifp->if_flags & IFF_RUNNING) 2001 alc_stop(sc); 2002 } 2003 break; 2004 2005 case SIOCSIFMEDIA: 2006 case SIOCGIFMEDIA: 2007 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2008 break; 2009 2010 default: 2011 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 2012 break; 2013 } 2014 2015 if (error == ENETRESET) { 2016 if (ifp->if_flags & IFF_RUNNING) 2017 alc_iff(sc); 2018 error = 0; 2019 } 2020 2021 splx(s); 2022 return (error); 2023 } 2024 2025 void 2026 alc_mac_config(struct alc_softc *sc) 2027 { 2028 struct mii_data *mii; 2029 uint32_t reg; 2030 2031 mii = &sc->sc_miibus; 2032 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2033 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2034 MAC_CFG_SPEED_MASK); 2035 if ((sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 2036 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 2037 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2 || 2038 sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2039 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2040 /* Reprogram MAC with resolved speed/duplex. */ 2041 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2042 case IFM_10_T: 2043 case IFM_100_TX: 2044 reg |= MAC_CFG_SPEED_10_100; 2045 break; 2046 case IFM_1000_T: 2047 reg |= MAC_CFG_SPEED_1000; 2048 break; 2049 } 2050 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2051 reg |= MAC_CFG_FULL_DUPLEX; 2052 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2053 reg |= MAC_CFG_TX_FC; 2054 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2055 reg |= MAC_CFG_RX_FC; 2056 } 2057 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2058 } 2059 2060 void 2061 alc_stats_clear(struct alc_softc *sc) 2062 { 2063 struct smb sb, *smb; 2064 uint32_t *reg; 2065 int i; 2066 2067 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2068 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2069 sc->alc_cdata.alc_smb_map->dm_mapsize, 2070 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2071 smb = sc->alc_rdata.alc_smb; 2072 /* Update done, clear. */ 2073 smb->updated = 0; 2074 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2075 sc->alc_cdata.alc_smb_map->dm_mapsize, 2076 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2077 } else { 2078 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2079 reg++) { 2080 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2081 i += sizeof(uint32_t); 2082 } 2083 /* Read Tx statistics. */ 2084 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2085 reg++) { 2086 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2087 i += sizeof(uint32_t); 2088 } 2089 } 2090 } 2091 2092 void 2093 alc_stats_update(struct alc_softc *sc) 2094 { 2095 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2096 struct alc_hw_stats *stat; 2097 struct smb sb, *smb; 2098 uint32_t *reg; 2099 int i; 2100 2101 stat = &sc->alc_stats; 2102 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2103 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2104 sc->alc_cdata.alc_smb_map->dm_mapsize, 2105 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2106 smb = sc->alc_rdata.alc_smb; 2107 if (smb->updated == 0) 2108 return; 2109 } else { 2110 smb = &sb; 2111 /* Read Rx statistics. */ 2112 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2113 reg++) { 2114 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2115 i += sizeof(uint32_t); 2116 } 2117 /* Read Tx statistics. */ 2118 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2119 reg++) { 2120 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2121 i += sizeof(uint32_t); 2122 } 2123 } 2124 2125 /* Rx stats. */ 2126 stat->rx_frames += smb->rx_frames; 2127 stat->rx_bcast_frames += smb->rx_bcast_frames; 2128 stat->rx_mcast_frames += smb->rx_mcast_frames; 2129 stat->rx_pause_frames += smb->rx_pause_frames; 2130 stat->rx_control_frames += smb->rx_control_frames; 2131 stat->rx_crcerrs += smb->rx_crcerrs; 2132 stat->rx_lenerrs += smb->rx_lenerrs; 2133 stat->rx_bytes += smb->rx_bytes; 2134 stat->rx_runts += smb->rx_runts; 2135 stat->rx_fragments += smb->rx_fragments; 2136 stat->rx_pkts_64 += smb->rx_pkts_64; 2137 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2138 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2139 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2140 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2141 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2142 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2143 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2144 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2145 stat->rx_rrs_errs += smb->rx_rrs_errs; 2146 stat->rx_alignerrs += smb->rx_alignerrs; 2147 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2148 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2149 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2150 2151 /* Tx stats. */ 2152 stat->tx_frames += smb->tx_frames; 2153 stat->tx_bcast_frames += smb->tx_bcast_frames; 2154 stat->tx_mcast_frames += smb->tx_mcast_frames; 2155 stat->tx_pause_frames += smb->tx_pause_frames; 2156 stat->tx_excess_defer += smb->tx_excess_defer; 2157 stat->tx_control_frames += smb->tx_control_frames; 2158 stat->tx_deferred += smb->tx_deferred; 2159 stat->tx_bytes += smb->tx_bytes; 2160 stat->tx_pkts_64 += smb->tx_pkts_64; 2161 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2162 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2163 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2164 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2165 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2166 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2167 stat->tx_single_colls += smb->tx_single_colls; 2168 stat->tx_multi_colls += smb->tx_multi_colls; 2169 stat->tx_late_colls += smb->tx_late_colls; 2170 stat->tx_excess_colls += smb->tx_excess_colls; 2171 stat->tx_underrun += smb->tx_underrun; 2172 stat->tx_desc_underrun += smb->tx_desc_underrun; 2173 stat->tx_lenerrs += smb->tx_lenerrs; 2174 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2175 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2176 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2177 2178 ifp->if_collisions += smb->tx_single_colls + 2179 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2180 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2181 2182 ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls + 2183 smb->tx_underrun + smb->tx_pkts_truncated; 2184 2185 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2186 smb->rx_runts + smb->rx_pkts_truncated + 2187 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2188 smb->rx_alignerrs; 2189 2190 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2191 /* Update done, clear. */ 2192 smb->updated = 0; 2193 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2194 sc->alc_cdata.alc_smb_map->dm_mapsize, 2195 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2196 } 2197 } 2198 2199 int 2200 alc_intr(void *arg) 2201 { 2202 struct alc_softc *sc = arg; 2203 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2204 uint32_t status; 2205 int claimed = 0; 2206 2207 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2208 if ((status & ALC_INTRS) == 0) 2209 return (0); 2210 2211 /* Disable interrupts. */ 2212 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2213 2214 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2215 if ((status & ALC_INTRS) == 0) 2216 goto back; 2217 2218 /* Acknowledge and disable interrupts. */ 2219 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2220 2221 if (ifp->if_flags & IFF_RUNNING) { 2222 int error = 0; 2223 2224 if (status & INTR_RX_PKT) { 2225 error = alc_rxintr(sc); 2226 if (error) { 2227 alc_init(ifp); 2228 return (0); 2229 } 2230 } 2231 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2232 INTR_TXQ_TO_RST)) { 2233 if (status & INTR_DMA_RD_TO_RST) 2234 printf("%s: DMA read error! -- resetting\n", 2235 sc->sc_dev.dv_xname); 2236 if (status & INTR_DMA_WR_TO_RST) 2237 printf("%s: DMA write error! -- resetting\n", 2238 sc->sc_dev.dv_xname); 2239 if (status & INTR_TXQ_TO_RST) 2240 printf("%s: TxQ reset! -- resetting\n", 2241 sc->sc_dev.dv_xname); 2242 alc_init(ifp); 2243 return (0); 2244 } 2245 2246 alc_txeof(sc); 2247 alc_start(ifp); 2248 } 2249 2250 claimed = 1; 2251 back: 2252 /* Re-enable interrupts. */ 2253 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2254 return (claimed); 2255 } 2256 2257 void 2258 alc_txeof(struct alc_softc *sc) 2259 { 2260 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2261 struct alc_txdesc *txd; 2262 uint32_t cons, prod; 2263 int prog; 2264 2265 if (sc->alc_cdata.alc_tx_cnt == 0) 2266 return; 2267 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2268 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2269 BUS_DMASYNC_POSTWRITE); 2270 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2271 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2272 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2273 BUS_DMASYNC_POSTREAD); 2274 prod = sc->alc_rdata.alc_cmb->cons; 2275 } else { 2276 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2277 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 2278 else { 2279 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2280 /* Assume we're using normal Tx priority queue. */ 2281 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2282 MBOX_TD_CONS_LO_IDX_SHIFT; 2283 } 2284 } 2285 cons = sc->alc_cdata.alc_tx_cons; 2286 /* 2287 * Go through our Tx list and free mbufs for those 2288 * frames which have been transmitted. 2289 */ 2290 for (prog = 0; cons != prod; prog++, 2291 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2292 if (sc->alc_cdata.alc_tx_cnt <= 0) 2293 break; 2294 prog++; 2295 ifq_clr_oactive(&ifp->if_snd); 2296 sc->alc_cdata.alc_tx_cnt--; 2297 txd = &sc->alc_cdata.alc_txdesc[cons]; 2298 if (txd->tx_m != NULL) { 2299 /* Reclaim transmitted mbufs. */ 2300 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 2301 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2302 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2303 m_freem(txd->tx_m); 2304 txd->tx_m = NULL; 2305 } 2306 } 2307 2308 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2309 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2310 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2311 sc->alc_cdata.alc_tx_cons = cons; 2312 /* 2313 * Unarm watchdog timer only when there is no pending 2314 * frames in Tx queue. 2315 */ 2316 if (sc->alc_cdata.alc_tx_cnt == 0) 2317 ifp->if_timer = 0; 2318 } 2319 2320 int 2321 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2322 { 2323 struct mbuf *m; 2324 bus_dmamap_t map; 2325 int error; 2326 2327 MGETHDR(m, M_DONTWAIT, MT_DATA); 2328 if (m == NULL) 2329 return (ENOBUFS); 2330 MCLGET(m, M_DONTWAIT); 2331 if (!(m->m_flags & M_EXT)) { 2332 m_freem(m); 2333 return (ENOBUFS); 2334 } 2335 2336 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2337 2338 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2339 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 2340 2341 if (error != 0) { 2342 m_freem(m); 2343 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 2344 return (error); 2345 } 2346 2347 if (rxd->rx_m != NULL) { 2348 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2349 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2350 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2351 } 2352 map = rxd->rx_dmamap; 2353 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2354 sc->alc_cdata.alc_rx_sparemap = map; 2355 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 2356 BUS_DMASYNC_PREREAD); 2357 rxd->rx_m = m; 2358 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2359 return (0); 2360 } 2361 2362 int 2363 alc_rxintr(struct alc_softc *sc) 2364 { 2365 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2366 struct rx_rdesc *rrd; 2367 uint32_t nsegs, status; 2368 int rr_cons, prog; 2369 2370 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2371 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2372 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2373 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2374 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2375 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2376 rr_cons = sc->alc_cdata.alc_rr_cons; 2377 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2378 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2379 status = letoh32(rrd->status); 2380 if ((status & RRD_VALID) == 0) 2381 break; 2382 nsegs = RRD_RD_CNT(letoh32(rrd->rdinfo)); 2383 if (nsegs == 0) { 2384 /* This should not happen! */ 2385 if (alcdebug) 2386 printf("%s: unexpected segment count -- " 2387 "resetting\n", sc->sc_dev.dv_xname); 2388 return (EIO); 2389 } 2390 alc_rxeof(sc, rrd); 2391 /* Clear Rx return status. */ 2392 rrd->status = 0; 2393 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2394 sc->alc_cdata.alc_rx_cons += nsegs; 2395 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2396 prog += nsegs; 2397 } 2398 2399 if (prog > 0) { 2400 /* Update the consumer index. */ 2401 sc->alc_cdata.alc_rr_cons = rr_cons; 2402 /* Sync Rx return descriptors. */ 2403 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2404 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2405 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2406 /* 2407 * Sync updated Rx descriptors such that controller see 2408 * modified buffer addresses. 2409 */ 2410 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2411 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2412 BUS_DMASYNC_PREWRITE); 2413 /* 2414 * Let controller know availability of new Rx buffers. 2415 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2416 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2417 * only when Rx buffer pre-fetching is required. In 2418 * addition we already set ALC_RX_RD_FREE_THRESH to 2419 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2420 * it still seems that pre-fetching needs more 2421 * experimentation. 2422 */ 2423 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2424 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 2425 (uint16_t)sc->alc_cdata.alc_rx_cons); 2426 else 2427 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2428 sc->alc_cdata.alc_rx_cons); 2429 } 2430 2431 return (0); 2432 } 2433 2434 /* Receive a frame. */ 2435 void 2436 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2437 { 2438 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2439 struct alc_rxdesc *rxd; 2440 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2441 struct mbuf *mp, *m; 2442 uint32_t rdinfo, status; 2443 int count, nsegs, rx_cons; 2444 2445 status = letoh32(rrd->status); 2446 rdinfo = letoh32(rrd->rdinfo); 2447 rx_cons = RRD_RD_IDX(rdinfo); 2448 nsegs = RRD_RD_CNT(rdinfo); 2449 2450 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2451 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 2452 /* 2453 * We want to pass the following frames to upper 2454 * layer regardless of error status of Rx return 2455 * ring. 2456 * 2457 * o IP/TCP/UDP checksum is bad. 2458 * o frame length and protocol specific length 2459 * does not match. 2460 * 2461 * Force network stack compute checksum for 2462 * errored frames. 2463 */ 2464 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2465 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2466 return; 2467 } 2468 2469 for (count = 0; count < nsegs; count++, 2470 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2471 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2472 mp = rxd->rx_m; 2473 /* Add a new receive buffer to the ring. */ 2474 if (alc_newbuf(sc, rxd) != 0) { 2475 ifp->if_iqdrops++; 2476 /* Reuse Rx buffers. */ 2477 m_freem(sc->alc_cdata.alc_rxhead); 2478 break; 2479 } 2480 2481 /* 2482 * Assume we've received a full sized frame. 2483 * Actual size is fixed when we encounter the end of 2484 * multi-segmented frame. 2485 */ 2486 mp->m_len = sc->alc_buf_size; 2487 2488 /* Chain received mbufs. */ 2489 if (sc->alc_cdata.alc_rxhead == NULL) { 2490 sc->alc_cdata.alc_rxhead = mp; 2491 sc->alc_cdata.alc_rxtail = mp; 2492 } else { 2493 mp->m_flags &= ~M_PKTHDR; 2494 sc->alc_cdata.alc_rxprev_tail = 2495 sc->alc_cdata.alc_rxtail; 2496 sc->alc_cdata.alc_rxtail->m_next = mp; 2497 sc->alc_cdata.alc_rxtail = mp; 2498 } 2499 2500 if (count == nsegs - 1) { 2501 /* Last desc. for this frame. */ 2502 m = sc->alc_cdata.alc_rxhead; 2503 m->m_flags |= M_PKTHDR; 2504 /* 2505 * It seems that L1C/L2C controller has no way 2506 * to tell hardware to strip CRC bytes. 2507 */ 2508 m->m_pkthdr.len = 2509 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2510 if (nsegs > 1) { 2511 /* Set last mbuf size. */ 2512 mp->m_len = sc->alc_cdata.alc_rxlen - 2513 (nsegs - 1) * sc->alc_buf_size; 2514 /* Remove the CRC bytes in chained mbufs. */ 2515 if (mp->m_len <= ETHER_CRC_LEN) { 2516 sc->alc_cdata.alc_rxtail = 2517 sc->alc_cdata.alc_rxprev_tail; 2518 sc->alc_cdata.alc_rxtail->m_len -= 2519 (ETHER_CRC_LEN - mp->m_len); 2520 sc->alc_cdata.alc_rxtail->m_next = NULL; 2521 m_freem(mp); 2522 } else { 2523 mp->m_len -= ETHER_CRC_LEN; 2524 } 2525 } else 2526 m->m_len = m->m_pkthdr.len; 2527 /* 2528 * Due to hardware bugs, Rx checksum offloading 2529 * was intentionally disabled. 2530 */ 2531 #if NVLAN > 0 2532 if (status & RRD_VLAN_TAG) { 2533 u_int32_t vtag = RRD_VLAN(letoh32(rrd->vtag)); 2534 m->m_pkthdr.ether_vtag = ntohs(vtag); 2535 m->m_flags |= M_VLANTAG; 2536 } 2537 #endif 2538 2539 2540 ml_enqueue(&ml, m); 2541 } 2542 } 2543 if_input(ifp, &ml); 2544 2545 /* Reset mbuf chains. */ 2546 ALC_RXCHAIN_RESET(sc); 2547 } 2548 2549 void 2550 alc_tick(void *xsc) 2551 { 2552 struct alc_softc *sc = xsc; 2553 struct mii_data *mii = &sc->sc_miibus; 2554 int s; 2555 2556 s = splnet(); 2557 mii_tick(mii); 2558 alc_stats_update(sc); 2559 2560 timeout_add_sec(&sc->alc_tick_ch, 1); 2561 splx(s); 2562 } 2563 2564 void 2565 alc_osc_reset(struct alc_softc *sc) 2566 { 2567 uint32_t reg; 2568 2569 reg = CSR_READ_4(sc, ALC_MISC3); 2570 reg &= ~MISC3_25M_BY_SW; 2571 reg |= MISC3_25M_NOTO_INTNL; 2572 CSR_WRITE_4(sc, ALC_MISC3, reg); 2573 reg = CSR_READ_4(sc, ALC_MISC); 2574 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 2575 /* 2576 * Restore over-current protection default value. 2577 * This value could be reset by MAC reset. 2578 */ 2579 reg &= ~MISC_PSW_OCP_MASK; 2580 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 2581 reg &= ~MISC_INTNLOSC_OPEN; 2582 CSR_WRITE_4(sc, ALC_MISC, reg); 2583 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2584 reg = CSR_READ_4(sc, ALC_MISC2); 2585 reg &= ~MISC2_CALB_START; 2586 CSR_WRITE_4(sc, ALC_MISC2, reg); 2587 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 2588 } else { 2589 reg &= ~MISC_INTNLOSC_OPEN; 2590 /* Disable isolate for revision A devices. */ 2591 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2592 reg &= ~MISC_ISO_ENB; 2593 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2594 CSR_WRITE_4(sc, ALC_MISC, reg); 2595 } 2596 DELAY(20); 2597 } 2598 2599 void 2600 alc_reset(struct alc_softc *sc) 2601 { 2602 uint32_t reg, pmcfg = 0; 2603 int i; 2604 2605 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2606 /* Reset workaround. */ 2607 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 2608 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2609 (sc->alc_rev & 0x01) != 0) { 2610 /* Disable L0s/L1s before reset. */ 2611 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 2612 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | 2613 PM_CFG_ASPM_L1_ENB))!= 0) { 2614 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 2615 PM_CFG_ASPM_L1_ENB); 2616 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2617 } 2618 } 2619 } 2620 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2621 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2622 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2623 2624 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2625 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2626 DELAY(10); 2627 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 2628 break; 2629 } 2630 if (i == 0) 2631 printf("MAC reset timeout!\n"); 2632 } 2633 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2634 DELAY(10); 2635 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2636 break; 2637 } 2638 if (i == 0) 2639 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); 2640 2641 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2642 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2643 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 2644 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2645 break; 2646 DELAY(10); 2647 } 2648 2649 if (i == 0) 2650 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 2651 reg); 2652 2653 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2654 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2655 (sc->alc_rev & 0x01) != 0) { 2656 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2657 reg |= MASTER_CLK_SEL_DIS; 2658 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2659 /* Restore L0s/L1s config. */ 2660 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | 2661 PM_CFG_ASPM_L1_ENB)) != 0) 2662 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2663 } 2664 alc_osc_reset(sc); 2665 reg = CSR_READ_4(sc, ALC_MISC3); 2666 reg &= ~MISC3_25M_BY_SW; 2667 reg |= MISC3_25M_NOTO_INTNL; 2668 CSR_WRITE_4(sc, ALC_MISC3, reg); 2669 reg = CSR_READ_4(sc, ALC_MISC); 2670 reg &= ~MISC_INTNLOSC_OPEN; 2671 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2672 reg &= ~MISC_ISO_ENB; 2673 CSR_WRITE_4(sc, ALC_MISC, reg); 2674 DELAY(20); 2675 } 2676 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 2677 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 2678 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 2679 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2680 CSR_READ_4(sc, ALC_SERDES_LOCK) | 2681 SERDES_MAC_CLK_SLOWDOWN | SERDES_PHY_CLK_SLOWDOWN); 2682 } 2683 2684 int 2685 alc_init(struct ifnet *ifp) 2686 { 2687 struct alc_softc *sc = ifp->if_softc; 2688 uint8_t eaddr[ETHER_ADDR_LEN]; 2689 bus_addr_t paddr; 2690 uint32_t reg, rxf_hi, rxf_lo; 2691 int error; 2692 2693 /* 2694 * Cancel any pending I/O. 2695 */ 2696 alc_stop(sc); 2697 /* 2698 * Reset the chip to a known state. 2699 */ 2700 alc_reset(sc); 2701 2702 /* Initialize Rx descriptors. */ 2703 error = alc_init_rx_ring(sc); 2704 if (error != 0) { 2705 printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname); 2706 alc_stop(sc); 2707 return (error); 2708 } 2709 alc_init_rr_ring(sc); 2710 alc_init_tx_ring(sc); 2711 alc_init_cmb(sc); 2712 alc_init_smb(sc); 2713 2714 /* Enable all clocks. */ 2715 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2716 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 2717 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 2718 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 2719 CLK_GATING_RXMAC_ENB); 2720 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 2721 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 2722 IDLE_DECISN_TIMER_DEFAULT_1MS); 2723 } else 2724 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2725 2726 /* Reprogram the station address. */ 2727 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 2728 CSR_WRITE_4(sc, ALC_PAR0, 2729 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2730 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2731 /* 2732 * Clear WOL status and disable all WOL feature as WOL 2733 * would interfere Rx operation under normal environments. 2734 */ 2735 CSR_READ_4(sc, ALC_WOL_CFG); 2736 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2737 /* Set Tx descriptor base addresses. */ 2738 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2739 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2740 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2741 /* We don't use high priority ring. */ 2742 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2743 /* Set Tx descriptor counter. */ 2744 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2745 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2746 /* Set Rx descriptor base addresses. */ 2747 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2748 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2749 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2750 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2751 /* We use one Rx ring. */ 2752 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2753 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2754 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2755 } 2756 /* Set Rx descriptor counter. */ 2757 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2758 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2759 2760 /* 2761 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2762 * if it do not fit the buffer size. Rx return descriptor holds 2763 * a counter that indicates how many fragments were made by the 2764 * hardware. The buffer size should be multiple of 8 bytes. 2765 * Since hardware has limit on the size of buffer size, always 2766 * use the maximum value. 2767 * For strict-alignment architectures make sure to reduce buffer 2768 * size by 8 bytes to make room for alignment fixup. 2769 */ 2770 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2771 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2772 2773 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2774 /* Set Rx return descriptor base addresses. */ 2775 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2776 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2777 /* We use one Rx return ring. */ 2778 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2779 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2780 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2781 } 2782 /* Set Rx return descriptor counter. */ 2783 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2784 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2785 paddr = sc->alc_rdata.alc_cmb_paddr; 2786 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2787 paddr = sc->alc_rdata.alc_smb_paddr; 2788 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2789 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2790 2791 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { 2792 /* Reconfigure SRAM - Vendor magic. */ 2793 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2794 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2795 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2796 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2797 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2798 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2799 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2800 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2801 } 2802 2803 /* Tell hardware that we're ready to load DMA blocks. */ 2804 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2805 2806 /* Configure interrupt moderation timer. */ 2807 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2808 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2809 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2810 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 2811 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2812 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2813 /* 2814 * We don't want to automatic interrupt clear as task queue 2815 * for the interrupt should know interrupt status. 2816 */ 2817 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2818 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2819 reg |= MASTER_SA_TIMER_ENB; 2820 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2821 reg |= MASTER_IM_RX_TIMER_ENB; 2822 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 2823 ALC_USECS(sc->alc_int_tx_mod) != 0) 2824 reg |= MASTER_IM_TX_TIMER_ENB; 2825 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2826 /* 2827 * Disable interrupt re-trigger timer. We don't want automatic 2828 * re-triggering of un-ACKed interrupts. 2829 */ 2830 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2831 /* Configure CMB. */ 2832 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2833 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 2834 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 2835 ALC_USECS(sc->alc_int_tx_mod)); 2836 } else { 2837 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2838 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2839 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2840 } else 2841 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2842 } 2843 /* 2844 * Hardware can be configured to issue SMB interrupt based 2845 * on programmed interval. Since there is a callout that is 2846 * invoked for every hz in driver we use that instead of 2847 * relying on periodic SMB interrupt. 2848 */ 2849 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2850 /* Clear MAC statistics. */ 2851 alc_stats_clear(sc); 2852 2853 /* 2854 * Always use maximum frame size that controller can support. 2855 * Otherwise received frames that has larger frame length 2856 * than alc(4) MTU would be silently dropped in hardware. This 2857 * would make path-MTU discovery hard as sender wouldn't get 2858 * any responses from receiver. alc(4) supports 2859 * multi-fragmented frames on Rx path so it has no issue on 2860 * assembling fragmented frames. Using maximum frame size also 2861 * removes the need to reinitialize hardware when interface 2862 * MTU configuration was changed. 2863 * 2864 * Be conservative in what you do, be liberal in what you 2865 * accept from others - RFC 793. 2866 */ 2867 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_max_framelen); 2868 2869 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2870 /* Disable header split(?) */ 2871 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2872 /* Configure IPG/IFG parameters. */ 2873 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2874 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 2875 IPG_IFG_IPGT_MASK) | 2876 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 2877 IPG_IFG_MIFG_MASK) | 2878 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 2879 IPG_IFG_IPG1_MASK) | 2880 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 2881 IPG_IFG_IPG2_MASK)); 2882 /* Set parameters for half-duplex media. */ 2883 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2884 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2885 HDPX_CFG_LCOL_MASK) | 2886 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2887 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2888 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2889 HDPX_CFG_ABEBT_MASK) | 2890 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2891 HDPX_CFG_JAMIPG_MASK)); 2892 } 2893 2894 /* 2895 * Set TSO/checksum offload threshold. For frames that is 2896 * larger than this threshold, hardware wouldn't do 2897 * TSO/checksum offloading. 2898 */ 2899 reg = (sc->alc_max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2900 TSO_OFFLOAD_THRESH_MASK; 2901 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2902 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 2903 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 2904 /* Configure TxQ. */ 2905 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2906 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2907 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 2908 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 2909 reg >>= 1; 2910 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2911 TXQ_CFG_TD_BURST_MASK; 2912 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 2913 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2914 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2915 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 2916 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 2917 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 2918 HQTD_CFG_BURST_ENB); 2919 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 2920 reg = WRR_PRI_RESTRICT_NONE; 2921 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 2922 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 2923 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 2924 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 2925 CSR_WRITE_4(sc, ALC_WRR, reg); 2926 } else { 2927 /* Configure Rx free descriptor pre-fetching. */ 2928 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2929 ((RX_RD_FREE_THRESH_HI_DEFAULT << 2930 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 2931 ((RX_RD_FREE_THRESH_LO_DEFAULT << 2932 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 2933 } 2934 2935 /* 2936 * Configure flow control parameters. 2937 * XON : 80% of Rx FIFO 2938 * XOFF : 30% of Rx FIFO 2939 */ 2940 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2941 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2942 reg &= SRAM_RX_FIFO_LEN_MASK; 2943 reg *= 8; 2944 if (reg > 8 * 1024) 2945 reg -= RX_FIFO_PAUSE_816X_RSVD; 2946 else 2947 reg -= RX_BUF_SIZE_MAX; 2948 reg /= 8; 2949 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2950 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2951 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2952 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 2953 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2954 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2955 } else if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C|| 2956 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C) { 2957 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2958 rxf_hi = (reg * 8) / 10; 2959 rxf_lo = (reg * 3) / 10; 2960 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2961 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2962 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2963 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2964 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2965 } 2966 2967 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2968 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 2969 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 2970 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 2971 } 2972 2973 /* Configure RxQ. */ 2974 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2975 RXQ_CFG_RD_BURST_MASK; 2976 reg |= RXQ_CFG_RSS_MODE_DIS; 2977 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2978 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 2979 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 2980 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 2981 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2982 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 2983 } else { 2984 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 2985 sc->sc_product != PCI_PRODUCT_ATTANSIC_L1D_1) 2986 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 2987 } 2988 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2989 2990 /* Configure DMA parameters. */ 2991 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 2992 reg |= sc->alc_rcb; 2993 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2994 reg |= DMA_CFG_CMB_ENB; 2995 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 2996 reg |= DMA_CFG_SMB_ENB; 2997 else 2998 reg |= DMA_CFG_SMB_DIS; 2999 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3000 DMA_CFG_RD_BURST_SHIFT; 3001 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3002 DMA_CFG_WR_BURST_SHIFT; 3003 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3004 DMA_CFG_RD_DELAY_CNT_MASK; 3005 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3006 DMA_CFG_WR_DELAY_CNT_MASK; 3007 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3008 switch (AR816X_REV(sc->alc_rev)) { 3009 case AR816X_REV_A0: 3010 case AR816X_REV_A1: 3011 reg |= DMA_CFG_RD_CHNL_SEL_2; 3012 break; 3013 case AR816X_REV_B0: 3014 /* FALLTHROUGH */ 3015 default: 3016 reg |= DMA_CFG_RD_CHNL_SEL_4; 3017 break; 3018 } 3019 } 3020 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3021 3022 /* 3023 * Configure Tx/Rx MACs. 3024 * - Auto-padding for short frames. 3025 * - Enable CRC generation. 3026 * Actual reconfiguration of MAC for resolved speed/duplex 3027 * is followed after detection of link establishment. 3028 * AR813x/AR815x always does checksum computation regardless 3029 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3030 * have bug in protocol field in Rx return structure so 3031 * these controllers can't handle fragmented frames. Disable 3032 * Rx checksum offloading until there is a newer controller 3033 * that has sane implementation. 3034 */ 3035 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3036 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3037 MAC_CFG_PREAMBLE_MASK); 3038 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3039 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 3040 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 3041 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 3042 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3043 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3044 reg |= MAC_CFG_SPEED_10_100; 3045 else 3046 reg |= MAC_CFG_SPEED_1000; 3047 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3048 3049 /* Set up the receive filter. */ 3050 alc_iff(sc); 3051 3052 alc_rxvlan(sc); 3053 3054 /* Acknowledge all pending interrupts and clear it. */ 3055 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3056 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3057 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3058 3059 ifp->if_flags |= IFF_RUNNING; 3060 ifq_clr_oactive(&ifp->if_snd); 3061 3062 sc->alc_flags &= ~ALC_FLAG_LINK; 3063 /* Switch to the current media. */ 3064 alc_mediachange(ifp); 3065 3066 timeout_add_sec(&sc->alc_tick_ch, 1); 3067 3068 return (0); 3069 } 3070 3071 void 3072 alc_stop(struct alc_softc *sc) 3073 { 3074 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 3075 struct alc_txdesc *txd; 3076 struct alc_rxdesc *rxd; 3077 uint32_t reg; 3078 int i; 3079 3080 /* 3081 * Mark the interface down and cancel the watchdog timer. 3082 */ 3083 ifp->if_flags &= ~IFF_RUNNING; 3084 ifq_clr_oactive(&ifp->if_snd); 3085 ifp->if_timer = 0; 3086 3087 timeout_del(&sc->alc_tick_ch); 3088 sc->alc_flags &= ~ALC_FLAG_LINK; 3089 3090 alc_stats_update(sc); 3091 3092 /* Disable interrupts. */ 3093 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3094 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3095 3096 /* Disable DMA. */ 3097 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3098 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3099 reg |= DMA_CFG_SMB_DIS; 3100 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3101 DELAY(1000); 3102 3103 /* Stop Rx/Tx MACs. */ 3104 alc_stop_mac(sc); 3105 3106 /* Disable interrupts which might be touched in taskq handler. */ 3107 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3108 3109 /* Disable L0s/L1s */ 3110 reg = CSR_READ_4(sc, ALC_PM_CFG); 3111 if ((reg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))!= 0) { 3112 reg &= ~(PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB); 3113 CSR_WRITE_4(sc, ALC_PM_CFG, reg); 3114 } 3115 3116 /* Reclaim Rx buffers that have been processed. */ 3117 m_freem(sc->alc_cdata.alc_rxhead); 3118 ALC_RXCHAIN_RESET(sc); 3119 /* 3120 * Free Tx/Rx mbufs still in the queues. 3121 */ 3122 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3123 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3124 if (rxd->rx_m != NULL) { 3125 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 3126 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3127 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 3128 m_freem(rxd->rx_m); 3129 rxd->rx_m = NULL; 3130 } 3131 } 3132 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3133 txd = &sc->alc_cdata.alc_txdesc[i]; 3134 if (txd->tx_m != NULL) { 3135 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 3136 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3137 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 3138 m_freem(txd->tx_m); 3139 txd->tx_m = NULL; 3140 } 3141 } 3142 } 3143 3144 void 3145 alc_stop_mac(struct alc_softc *sc) 3146 { 3147 uint32_t reg; 3148 int i; 3149 3150 alc_stop_queue(sc); 3151 /* Disable Rx/Tx MAC. */ 3152 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3153 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3154 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3155 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3156 } 3157 for (i = ALC_TIMEOUT; i > 0; i--) { 3158 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3159 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 3160 break; 3161 DELAY(10); 3162 } 3163 if (i == 0) 3164 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 3165 sc->sc_dev.dv_xname, reg); 3166 } 3167 3168 void 3169 alc_start_queue(struct alc_softc *sc) 3170 { 3171 uint32_t qcfg[] = { 3172 0, 3173 RXQ_CFG_QUEUE0_ENB, 3174 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3175 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3176 RXQ_CFG_ENB 3177 }; 3178 uint32_t cfg; 3179 3180 /* Enable RxQ. */ 3181 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3182 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3183 cfg &= ~RXQ_CFG_ENB; 3184 cfg |= qcfg[1]; 3185 } else 3186 cfg |= RXQ_CFG_QUEUE0_ENB; 3187 3188 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3189 /* Enable TxQ. */ 3190 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3191 cfg |= TXQ_CFG_ENB; 3192 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3193 } 3194 3195 void 3196 alc_stop_queue(struct alc_softc *sc) 3197 { 3198 uint32_t reg; 3199 int i; 3200 3201 /* Disable RxQ. */ 3202 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3203 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3204 if ((reg & RXQ_CFG_ENB) != 0) { 3205 reg &= ~RXQ_CFG_ENB; 3206 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3207 } 3208 } else { 3209 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 3210 reg &= ~RXQ_CFG_QUEUE0_ENB; 3211 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3212 } 3213 } 3214 /* Disable TxQ. */ 3215 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3216 if ((reg & TXQ_CFG_ENB) != 0) { 3217 reg &= ~TXQ_CFG_ENB; 3218 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3219 } 3220 DELAY(40); 3221 for (i = ALC_TIMEOUT; i > 0; i--) { 3222 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3223 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3224 break; 3225 DELAY(10); 3226 } 3227 if (i == 0) 3228 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 3229 sc->sc_dev.dv_xname, reg); 3230 } 3231 3232 void 3233 alc_init_tx_ring(struct alc_softc *sc) 3234 { 3235 struct alc_ring_data *rd; 3236 struct alc_txdesc *txd; 3237 int i; 3238 3239 sc->alc_cdata.alc_tx_prod = 0; 3240 sc->alc_cdata.alc_tx_cons = 0; 3241 sc->alc_cdata.alc_tx_cnt = 0; 3242 3243 rd = &sc->alc_rdata; 3244 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3245 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3246 txd = &sc->alc_cdata.alc_txdesc[i]; 3247 txd->tx_m = NULL; 3248 } 3249 3250 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 3251 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3252 } 3253 3254 int 3255 alc_init_rx_ring(struct alc_softc *sc) 3256 { 3257 struct alc_ring_data *rd; 3258 struct alc_rxdesc *rxd; 3259 int i; 3260 3261 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3262 rd = &sc->alc_rdata; 3263 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3264 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3265 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3266 rxd->rx_m = NULL; 3267 rxd->rx_desc = &rd->alc_rx_ring[i]; 3268 if (alc_newbuf(sc, rxd) != 0) 3269 return (ENOBUFS); 3270 } 3271 3272 /* 3273 * Since controller does not update Rx descriptors, driver 3274 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3275 * is enough to ensure coherence. 3276 */ 3277 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 3278 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3279 /* Let controller know availability of new Rx buffers. */ 3280 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3281 3282 return (0); 3283 } 3284 3285 void 3286 alc_init_rr_ring(struct alc_softc *sc) 3287 { 3288 struct alc_ring_data *rd; 3289 3290 sc->alc_cdata.alc_rr_cons = 0; 3291 ALC_RXCHAIN_RESET(sc); 3292 3293 rd = &sc->alc_rdata; 3294 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3295 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 3296 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 3297 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3298 } 3299 3300 void 3301 alc_init_cmb(struct alc_softc *sc) 3302 { 3303 struct alc_ring_data *rd; 3304 3305 rd = &sc->alc_rdata; 3306 bzero(rd->alc_cmb, ALC_CMB_SZ); 3307 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 3308 sc->alc_cdata.alc_cmb_map->dm_mapsize, 3309 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3310 } 3311 3312 void 3313 alc_init_smb(struct alc_softc *sc) 3314 { 3315 struct alc_ring_data *rd; 3316 3317 rd = &sc->alc_rdata; 3318 bzero(rd->alc_smb, ALC_SMB_SZ); 3319 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 3320 sc->alc_cdata.alc_smb_map->dm_mapsize, 3321 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3322 } 3323 3324 void 3325 alc_rxvlan(struct alc_softc *sc) 3326 { 3327 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 3328 uint32_t reg; 3329 3330 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3331 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 3332 reg |= MAC_CFG_VLAN_TAG_STRIP; 3333 else 3334 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3335 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3336 } 3337 3338 void 3339 alc_iff(struct alc_softc *sc) 3340 { 3341 struct arpcom *ac = &sc->sc_arpcom; 3342 struct ifnet *ifp = &ac->ac_if; 3343 struct ether_multi *enm; 3344 struct ether_multistep step; 3345 uint32_t crc; 3346 uint32_t mchash[2]; 3347 uint32_t rxcfg; 3348 3349 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3350 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3351 ifp->if_flags &= ~IFF_ALLMULTI; 3352 3353 /* 3354 * Always accept broadcast frames. 3355 */ 3356 rxcfg |= MAC_CFG_BCAST; 3357 3358 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 3359 ifp->if_flags |= IFF_ALLMULTI; 3360 if (ifp->if_flags & IFF_PROMISC) 3361 rxcfg |= MAC_CFG_PROMISC; 3362 else 3363 rxcfg |= MAC_CFG_ALLMULTI; 3364 mchash[0] = mchash[1] = 0xFFFFFFFF; 3365 } else { 3366 /* Program new filter. */ 3367 bzero(mchash, sizeof(mchash)); 3368 3369 ETHER_FIRST_MULTI(step, ac, enm); 3370 while (enm != NULL) { 3371 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3372 3373 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3374 3375 ETHER_NEXT_MULTI(step, enm); 3376 } 3377 } 3378 3379 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3380 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3381 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3382 } 3383