1 /* $OpenBSD: if_ale.c,v 1.52 2024/08/31 16:23:09 deraadt Exp $ */
2 /*-
3 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $
29 */
30
31 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
32
33 #include "bpfilter.h"
34 #include "vlan.h"
35
36 #include <sys/param.h>
37 #include <sys/endian.h>
38 #include <sys/systm.h>
39 #include <sys/sockio.h>
40 #include <sys/mbuf.h>
41 #include <sys/queue.h>
42 #include <sys/device.h>
43 #include <sys/timeout.h>
44
45 #include <machine/bus.h>
46
47 #include <net/if.h>
48 #include <net/if_dl.h>
49 #include <net/if_llc.h>
50 #include <net/if_media.h>
51
52 #include <netinet/in.h>
53 #include <netinet/ip.h>
54 #include <netinet/if_ether.h>
55
56 #if NBPFILTER > 0
57 #include <net/bpf.h>
58 #endif
59
60 #include <dev/mii/mii.h>
61 #include <dev/mii/miivar.h>
62
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
65 #include <dev/pci/pcidevs.h>
66
67 #include <dev/pci/if_alereg.h>
68
69 int ale_match(struct device *, void *, void *);
70 void ale_attach(struct device *, struct device *, void *);
71 int ale_detach(struct device *, int);
72 int ale_activate(struct device *, int);
73
74 int ale_miibus_readreg(struct device *, int, int);
75 void ale_miibus_writereg(struct device *, int, int, int);
76 void ale_miibus_statchg(struct device *);
77
78 int ale_init(struct ifnet *);
79 void ale_start(struct ifnet *);
80 int ale_ioctl(struct ifnet *, u_long, caddr_t);
81 void ale_watchdog(struct ifnet *);
82 int ale_mediachange(struct ifnet *);
83 void ale_mediastatus(struct ifnet *, struct ifmediareq *);
84
85 int ale_intr(void *);
86 int ale_rxeof(struct ale_softc *sc);
87 void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
88 uint32_t, uint32_t *);
89 void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
90 void ale_txeof(struct ale_softc *);
91
92 int ale_dma_alloc(struct ale_softc *);
93 void ale_dma_free(struct ale_softc *);
94 int ale_encap(struct ale_softc *, struct mbuf *);
95 void ale_init_rx_pages(struct ale_softc *);
96 void ale_init_tx_ring(struct ale_softc *);
97
98 void ale_stop(struct ale_softc *);
99 void ale_tick(void *);
100 void ale_get_macaddr(struct ale_softc *);
101 void ale_mac_config(struct ale_softc *);
102 void ale_phy_reset(struct ale_softc *);
103 void ale_reset(struct ale_softc *);
104 void ale_iff(struct ale_softc *);
105 void ale_rxvlan(struct ale_softc *);
106 void ale_stats_clear(struct ale_softc *);
107 void ale_stats_update(struct ale_softc *);
108 void ale_stop_mac(struct ale_softc *);
109
110 const struct pci_matchid ale_devices[] = {
111 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1E }
112 };
113
114 const struct cfattach ale_ca = {
115 sizeof (struct ale_softc), ale_match, ale_attach, NULL,
116 ale_activate
117 };
118
119 struct cfdriver ale_cd = {
120 NULL, "ale", DV_IFNET
121 };
122
123 int aledebug = 0;
124 #define DPRINTF(x) do { if (aledebug) printf x; } while (0)
125
126 #define ALE_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)
127
128 int
ale_miibus_readreg(struct device * dev,int phy,int reg)129 ale_miibus_readreg(struct device *dev, int phy, int reg)
130 {
131 struct ale_softc *sc = (struct ale_softc *)dev;
132 uint32_t v;
133 int i;
134
135 if (phy != sc->ale_phyaddr)
136 return (0);
137
138 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0 &&
139 reg == MII_EXTSR)
140 return (0);
141
142 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
143 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
144 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
145 DELAY(5);
146 v = CSR_READ_4(sc, ALE_MDIO);
147 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
148 break;
149 }
150
151 if (i == 0) {
152 printf("%s: phy read timeout: phy %d, reg %d\n",
153 sc->sc_dev.dv_xname, phy, reg);
154 return (0);
155 }
156
157 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
158 }
159
160 void
ale_miibus_writereg(struct device * dev,int phy,int reg,int val)161 ale_miibus_writereg(struct device *dev, int phy, int reg, int val)
162 {
163 struct ale_softc *sc = (struct ale_softc *)dev;
164 uint32_t v;
165 int i;
166
167 if (phy != sc->ale_phyaddr)
168 return;
169
170 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
171 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
172 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
173 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
174 DELAY(5);
175 v = CSR_READ_4(sc, ALE_MDIO);
176 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
177 break;
178 }
179
180 if (i == 0)
181 printf("%s: phy write timeout: phy %d, reg %d\n",
182 sc->sc_dev.dv_xname, phy, reg);
183 }
184
185 void
ale_miibus_statchg(struct device * dev)186 ale_miibus_statchg(struct device *dev)
187 {
188 struct ale_softc *sc = (struct ale_softc *)dev;
189 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
190 struct mii_data *mii = &sc->sc_miibus;
191 uint32_t reg;
192
193 if ((ifp->if_flags & IFF_RUNNING) == 0)
194 return;
195
196 sc->ale_flags &= ~ALE_FLAG_LINK;
197 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
198 (IFM_ACTIVE | IFM_AVALID)) {
199 switch (IFM_SUBTYPE(mii->mii_media_active)) {
200 case IFM_10_T:
201 case IFM_100_TX:
202 sc->ale_flags |= ALE_FLAG_LINK;
203 break;
204
205 case IFM_1000_T:
206 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
207 sc->ale_flags |= ALE_FLAG_LINK;
208 break;
209
210 default:
211 break;
212 }
213 }
214
215 /* Stop Rx/Tx MACs. */
216 ale_stop_mac(sc);
217
218 /* Program MACs with resolved speed/duplex/flow-control. */
219 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
220 ale_mac_config(sc);
221 /* Reenable Tx/Rx MACs. */
222 reg = CSR_READ_4(sc, ALE_MAC_CFG);
223 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
224 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
225 }
226 }
227
228 void
ale_mediastatus(struct ifnet * ifp,struct ifmediareq * ifmr)229 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
230 {
231 struct ale_softc *sc = ifp->if_softc;
232 struct mii_data *mii = &sc->sc_miibus;
233
234 if ((ifp->if_flags & IFF_UP) == 0)
235 return;
236
237 mii_pollstat(mii);
238 ifmr->ifm_status = mii->mii_media_status;
239 ifmr->ifm_active = mii->mii_media_active;
240 }
241
242 int
ale_mediachange(struct ifnet * ifp)243 ale_mediachange(struct ifnet *ifp)
244 {
245 struct ale_softc *sc = ifp->if_softc;
246 struct mii_data *mii = &sc->sc_miibus;
247 int error;
248
249 if (mii->mii_instance != 0) {
250 struct mii_softc *miisc;
251
252 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
253 mii_phy_reset(miisc);
254 }
255 error = mii_mediachg(mii);
256
257 return (error);
258 }
259
260 int
ale_match(struct device * dev,void * match,void * aux)261 ale_match(struct device *dev, void *match, void *aux)
262 {
263 return pci_matchbyid((struct pci_attach_args *)aux, ale_devices,
264 sizeof (ale_devices) / sizeof (ale_devices[0]));
265 }
266
267 void
ale_get_macaddr(struct ale_softc * sc)268 ale_get_macaddr(struct ale_softc *sc)
269 {
270 uint32_t ea[2], reg;
271 int i, vpdc;
272
273 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
274 if ((reg & SPI_VPD_ENB) != 0) {
275 reg &= ~SPI_VPD_ENB;
276 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
277 }
278
279 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD,
280 &vpdc, NULL)) {
281 /*
282 * PCI VPD capability found, let TWSI reload EEPROM.
283 * This will set ethernet address of controller.
284 */
285 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
286 TWSI_CTRL_SW_LD_START);
287 for (i = 100; i > 0; i--) {
288 DELAY(1000);
289 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
290 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
291 break;
292 }
293 if (i == 0)
294 printf("%s: reloading EEPROM timeout!\n",
295 sc->sc_dev.dv_xname);
296 } else {
297 if (aledebug)
298 printf("%s: PCI VPD capability not found!\n",
299 sc->sc_dev.dv_xname);
300 }
301
302 ea[0] = CSR_READ_4(sc, ALE_PAR0);
303 ea[1] = CSR_READ_4(sc, ALE_PAR1);
304 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
305 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
306 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
307 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
308 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
309 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
310 }
311
312 void
ale_phy_reset(struct ale_softc * sc)313 ale_phy_reset(struct ale_softc *sc)
314 {
315 /* Reset magic from Linux. */
316 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
317 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
318 GPHY_CTRL_PHY_PLL_ON);
319 DELAY(1000);
320 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
321 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
322 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
323 DELAY(1000);
324
325 #define ATPHY_DBG_ADDR 0x1D
326 #define ATPHY_DBG_DATA 0x1E
327
328 /* Enable hibernation mode. */
329 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr,
330 ATPHY_DBG_ADDR, 0x0B);
331 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr,
332 ATPHY_DBG_DATA, 0xBC00);
333 /* Set Class A/B for all modes. */
334 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr,
335 ATPHY_DBG_ADDR, 0x00);
336 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr,
337 ATPHY_DBG_DATA, 0x02EF);
338 /* Enable 10BT power saving. */
339 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr,
340 ATPHY_DBG_ADDR, 0x12);
341 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr,
342 ATPHY_DBG_DATA, 0x4C04);
343 /* Adjust 1000T power. */
344 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr,
345 ATPHY_DBG_ADDR, 0x04);
346 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr,
347 ATPHY_DBG_ADDR, 0x8BBB);
348 /* 10BT center tap voltage. */
349 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr,
350 ATPHY_DBG_ADDR, 0x05);
351 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr,
352 ATPHY_DBG_ADDR, 0x2C46);
353
354 #undef ATPHY_DBG_ADDR
355 #undef ATPHY_DBG_DATA
356 DELAY(1000);
357 }
358
359 void
ale_attach(struct device * parent,struct device * self,void * aux)360 ale_attach(struct device *parent, struct device *self, void *aux)
361 {
362 struct ale_softc *sc = (struct ale_softc *)self;
363 struct pci_attach_args *pa = aux;
364 pci_chipset_tag_t pc = pa->pa_pc;
365 pci_intr_handle_t ih;
366 const char *intrstr;
367 struct ifnet *ifp;
368 pcireg_t memtype;
369 int mii_flags, error = 0;
370 uint32_t rxf_len, txf_len;
371 const char *chipname;
372
373 /*
374 * Allocate IO memory
375 */
376 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALE_PCIR_BAR);
377 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt,
378 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) {
379 printf(": can't map mem space\n");
380 return;
381 }
382
383 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) {
384 printf(": can't map interrupt\n");
385 goto fail;
386 }
387
388 /*
389 * Allocate IRQ
390 */
391 intrstr = pci_intr_string(pc, ih);
392 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc,
393 sc->sc_dev.dv_xname);
394 if (sc->sc_irq_handle == NULL) {
395 printf(": could not establish interrupt");
396 if (intrstr != NULL)
397 printf(" at %s", intrstr);
398 printf("\n");
399 goto fail;
400 }
401
402 sc->sc_dmat = pa->pa_dmat;
403 sc->sc_pct = pa->pa_pc;
404 sc->sc_pcitag = pa->pa_tag;
405
406 /* Set PHY address. */
407 sc->ale_phyaddr = ALE_PHY_ADDR;
408
409 /* Reset PHY. */
410 ale_phy_reset(sc);
411
412 /* Reset the ethernet controller. */
413 ale_reset(sc);
414
415 /* Get PCI and chip id/revision. */
416 sc->ale_rev = PCI_REVISION(pa->pa_class);
417 if (sc->ale_rev >= 0xF0) {
418 /* L2E Rev. B. AR8114 */
419 sc->ale_flags |= ALE_FLAG_FASTETHER;
420 chipname = "AR8114";
421 } else {
422 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
423 /* L1E AR8121 */
424 sc->ale_flags |= ALE_FLAG_JUMBO;
425 chipname = "AR8121";
426 } else {
427 /* L2E Rev. A. AR8113 */
428 sc->ale_flags |= ALE_FLAG_FASTETHER;
429 chipname = "AR8113";
430 }
431 }
432
433 printf(": %s, %s", chipname, intrstr);
434
435 /*
436 * All known controllers seems to require 4 bytes alignment
437 * of Tx buffers to make Tx checksum offload with custom
438 * checksum generation method work.
439 */
440 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
441
442 /*
443 * All known controllers seems to have issues on Rx checksum
444 * offload for fragmented IP datagrams.
445 */
446 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
447
448 /*
449 * Don't use Tx CMB. It is known to cause RRS update failure
450 * under certain circumstances. Typical phenomenon of the
451 * issue would be unexpected sequence number encountered in
452 * Rx handler.
453 */
454 sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
455 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
456 MASTER_CHIP_REV_SHIFT;
457 if (aledebug) {
458 printf("%s: PCI device revision : 0x%04x\n",
459 sc->sc_dev.dv_xname, sc->ale_rev);
460 printf("%s: Chip id/revision : 0x%04x\n",
461 sc->sc_dev.dv_xname, sc->ale_chip_rev);
462 }
463
464 /*
465 * Uninitialized hardware returns an invalid chip id/revision
466 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
467 */
468 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
469 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
470 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
471 rxf_len == 0xFFFFFFF) {
472 printf("%s: chip revision : 0x%04x, %u Tx FIFO "
473 "%u Rx FIFO -- not initialized?\n", sc->sc_dev.dv_xname,
474 sc->ale_chip_rev, txf_len, rxf_len);
475 goto fail;
476 }
477
478 if (aledebug) {
479 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname,
480 txf_len, rxf_len);
481 }
482
483 /* Set max allowable DMA size. */
484 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
485 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
486
487 error = ale_dma_alloc(sc);
488 if (error)
489 goto fail;
490
491 /* Load station address. */
492 ale_get_macaddr(sc);
493
494 ifp = &sc->sc_arpcom.ac_if;
495 ifp->if_softc = sc;
496 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
497 ifp->if_ioctl = ale_ioctl;
498 ifp->if_start = ale_start;
499 ifp->if_watchdog = ale_watchdog;
500 ifq_init_maxlen(&ifp->if_snd, ALE_TX_RING_CNT - 1);
501 bcopy(sc->ale_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
502 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
503
504 ifp->if_capabilities = IFCAP_VLAN_MTU;
505
506 #ifdef ALE_CHECKSUM
507 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 |
508 IFCAP_CSUM_UDPv4;
509 #endif
510
511 #if NVLAN > 0
512 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
513 #endif
514
515 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
516
517 /* Set up MII bus. */
518 sc->sc_miibus.mii_ifp = ifp;
519 sc->sc_miibus.mii_readreg = ale_miibus_readreg;
520 sc->sc_miibus.mii_writereg = ale_miibus_writereg;
521 sc->sc_miibus.mii_statchg = ale_miibus_statchg;
522
523 ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange,
524 ale_mediastatus);
525 mii_flags = 0;
526 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
527 mii_flags |= MIIF_DOPAUSE;
528 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY,
529 MII_OFFSET_ANY, mii_flags);
530
531 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) {
532 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname);
533 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL,
534 0, NULL);
535 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL);
536 } else
537 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO);
538
539 if_attach(ifp);
540 ether_ifattach(ifp);
541
542 timeout_set(&sc->ale_tick_ch, ale_tick, sc);
543
544 return;
545 fail:
546 ale_dma_free(sc);
547 if (sc->sc_irq_handle != NULL)
548 pci_intr_disestablish(pc, sc->sc_irq_handle);
549 if (sc->sc_mem_size)
550 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size);
551 }
552
553 int
ale_detach(struct device * self,int flags)554 ale_detach(struct device *self, int flags)
555 {
556 struct ale_softc *sc = (struct ale_softc *)self;
557 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
558 int s;
559
560 s = splnet();
561 ale_stop(sc);
562 splx(s);
563
564 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY);
565
566 /* Delete all remaining media. */
567 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY);
568
569 ether_ifdetach(ifp);
570 if_detach(ifp);
571 ale_dma_free(sc);
572
573 if (sc->sc_irq_handle != NULL) {
574 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle);
575 sc->sc_irq_handle = NULL;
576 }
577
578 return (0);
579 }
580
581 int
ale_activate(struct device * self,int act)582 ale_activate(struct device *self, int act)
583 {
584 struct ale_softc *sc = (struct ale_softc *)self;
585 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
586
587 switch (act) {
588 case DVACT_SUSPEND:
589 if (ifp->if_flags & IFF_RUNNING)
590 ale_stop(sc);
591 break;
592 case DVACT_RESUME:
593 if (ifp->if_flags & IFF_UP)
594 ale_init(ifp);
595 break;
596 }
597 return (0);
598 }
599
600 int
ale_dma_alloc(struct ale_softc * sc)601 ale_dma_alloc(struct ale_softc *sc)
602 {
603 struct ale_txdesc *txd;
604 int nsegs, error, guard_size, i;
605
606 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
607 guard_size = ALE_JUMBO_FRAMELEN;
608 else
609 guard_size = ALE_MAX_FRAMELEN;
610 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
611 ALE_RX_PAGE_ALIGN);
612
613 /*
614 * Create DMA stuffs for TX ring
615 */
616 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1,
617 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map);
618 if (error)
619 return (ENOBUFS);
620
621 /* Allocate DMA'able memory for TX ring */
622 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ,
623 ETHER_ALIGN, 0, &sc->ale_cdata.ale_tx_ring_seg, 1,
624 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO);
625 if (error) {
626 printf("%s: could not allocate DMA'able memory for Tx ring.\n",
627 sc->sc_dev.dv_xname);
628 return error;
629 }
630
631 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg,
632 nsegs, ALE_TX_RING_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_ring,
633 BUS_DMA_NOWAIT);
634 if (error)
635 return (ENOBUFS);
636
637 /* Load the DMA map for Tx ring. */
638 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map,
639 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK);
640 if (error) {
641 printf("%s: could not load DMA'able memory for Tx ring.\n",
642 sc->sc_dev.dv_xname);
643 bus_dmamem_free(sc->sc_dmat,
644 (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_ring, 1);
645 return error;
646 }
647 sc->ale_cdata.ale_tx_ring_paddr =
648 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr;
649
650 for (i = 0; i < ALE_RX_PAGES; i++) {
651 /*
652 * Create DMA stuffs for RX pages
653 */
654 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1,
655 sc->ale_pagesize, 0, BUS_DMA_NOWAIT,
656 &sc->ale_cdata.ale_rx_page[i].page_map);
657 if (error)
658 return (ENOBUFS);
659
660 /* Allocate DMA'able memory for RX pages */
661 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize,
662 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg,
663 1, &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO);
664 if (error) {
665 printf("%s: could not allocate DMA'able memory for "
666 "Rx ring.\n", sc->sc_dev.dv_xname);
667 return error;
668 }
669 error = bus_dmamem_map(sc->sc_dmat,
670 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs,
671 sc->ale_pagesize,
672 (caddr_t *)&sc->ale_cdata.ale_rx_page[i].page_addr,
673 BUS_DMA_NOWAIT);
674 if (error)
675 return (ENOBUFS);
676
677 /* Load the DMA map for Rx pages. */
678 error = bus_dmamap_load(sc->sc_dmat,
679 sc->ale_cdata.ale_rx_page[i].page_map,
680 sc->ale_cdata.ale_rx_page[i].page_addr,
681 sc->ale_pagesize, NULL, BUS_DMA_WAITOK);
682 if (error) {
683 printf("%s: could not load DMA'able memory for "
684 "Rx pages.\n", sc->sc_dev.dv_xname);
685 bus_dmamem_free(sc->sc_dmat,
686 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].page_addr, 1);
687 return error;
688 }
689 sc->ale_cdata.ale_rx_page[i].page_paddr =
690 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr;
691 }
692
693 /*
694 * Create DMA stuffs for Tx CMB.
695 */
696 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1,
697 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map);
698 if (error)
699 return (ENOBUFS);
700
701 /* Allocate DMA'able memory for Tx CMB. */
702 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0,
703 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs,
704 BUS_DMA_WAITOK |BUS_DMA_ZERO);
705
706 if (error) {
707 printf("%s: could not allocate DMA'able memory for Tx CMB.\n",
708 sc->sc_dev.dv_xname);
709 return error;
710 }
711
712 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg,
713 nsegs, ALE_TX_CMB_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_cmb,
714 BUS_DMA_NOWAIT);
715 if (error)
716 return (ENOBUFS);
717
718 /* Load the DMA map for Tx CMB. */
719 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map,
720 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK);
721 if (error) {
722 printf("%s: could not load DMA'able memory for Tx CMB.\n",
723 sc->sc_dev.dv_xname);
724 bus_dmamem_free(sc->sc_dmat,
725 (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_cmb, 1);
726 return error;
727 }
728
729 sc->ale_cdata.ale_tx_cmb_paddr =
730 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr;
731
732 for (i = 0; i < ALE_RX_PAGES; i++) {
733 /*
734 * Create DMA stuffs for Rx CMB.
735 */
736 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1,
737 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT,
738 &sc->ale_cdata.ale_rx_page[i].cmb_map);
739 if (error)
740 return (ENOBUFS);
741
742 /* Allocate DMA'able memory for Rx CMB */
743 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ,
744 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1,
745 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO);
746 if (error) {
747 printf("%s: could not allocate DMA'able memory for "
748 "Rx CMB\n", sc->sc_dev.dv_xname);
749 return error;
750 }
751 error = bus_dmamem_map(sc->sc_dmat,
752 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs,
753 ALE_RX_CMB_SZ,
754 (caddr_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
755 BUS_DMA_NOWAIT);
756 if (error)
757 return (ENOBUFS);
758
759 /* Load the DMA map for Rx CMB */
760 error = bus_dmamap_load(sc->sc_dmat,
761 sc->ale_cdata.ale_rx_page[i].cmb_map,
762 sc->ale_cdata.ale_rx_page[i].cmb_addr,
763 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK);
764 if (error) {
765 printf("%s: could not load DMA'able memory for Rx CMB"
766 "\n", sc->sc_dev.dv_xname);
767 bus_dmamem_free(sc->sc_dmat,
768 (bus_dma_segment_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1);
769 return error;
770 }
771 sc->ale_cdata.ale_rx_page[i].cmb_paddr =
772 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr;
773 }
774
775
776 /* Create DMA maps for Tx buffers. */
777 for (i = 0; i < ALE_TX_RING_CNT; i++) {
778 txd = &sc->ale_cdata.ale_txdesc[i];
779 txd->tx_m = NULL;
780 txd->tx_dmamap = NULL;
781 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE,
782 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT,
783 &txd->tx_dmamap);
784 if (error) {
785 printf("%s: could not create Tx dmamap.\n",
786 sc->sc_dev.dv_xname);
787 return error;
788 }
789 }
790
791 return (0);
792 }
793
794 void
ale_dma_free(struct ale_softc * sc)795 ale_dma_free(struct ale_softc *sc)
796 {
797 struct ale_txdesc *txd;
798 int i;
799
800 /* Tx buffers. */
801 for (i = 0; i < ALE_TX_RING_CNT; i++) {
802 txd = &sc->ale_cdata.ale_txdesc[i];
803 if (txd->tx_dmamap != NULL) {
804 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap);
805 txd->tx_dmamap = NULL;
806 }
807 }
808
809 /* Tx descriptor ring. */
810 if (sc->ale_cdata.ale_tx_ring_map != NULL)
811 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map);
812 if (sc->ale_cdata.ale_tx_ring_map != NULL &&
813 sc->ale_cdata.ale_tx_ring != NULL)
814 bus_dmamem_free(sc->sc_dmat,
815 (bus_dma_segment_t *)sc->ale_cdata.ale_tx_ring, 1);
816 sc->ale_cdata.ale_tx_ring = NULL;
817 sc->ale_cdata.ale_tx_ring_map = NULL;
818
819 /* Rx page block. */
820 for (i = 0; i < ALE_RX_PAGES; i++) {
821 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL)
822 bus_dmamap_unload(sc->sc_dmat,
823 sc->ale_cdata.ale_rx_page[i].page_map);
824 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL &&
825 sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
826 bus_dmamem_free(sc->sc_dmat,
827 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].page_addr, 1);
828 sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
829 sc->ale_cdata.ale_rx_page[i].page_map = NULL;
830 }
831
832 /* Rx CMB. */
833 for (i = 0; i < ALE_RX_PAGES; i++) {
834 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL)
835 bus_dmamap_unload(sc->sc_dmat,
836 sc->ale_cdata.ale_rx_page[i].cmb_map);
837 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL &&
838 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
839 bus_dmamem_free(sc->sc_dmat,
840 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].cmb_addr, 1);
841 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
842 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL;
843 }
844
845 /* Tx CMB. */
846 if (sc->ale_cdata.ale_tx_cmb_map != NULL)
847 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map);
848 if (sc->ale_cdata.ale_tx_cmb_map != NULL &&
849 sc->ale_cdata.ale_tx_cmb != NULL)
850 bus_dmamem_free(sc->sc_dmat,
851 (bus_dma_segment_t *)sc->ale_cdata.ale_tx_cmb, 1);
852 sc->ale_cdata.ale_tx_cmb = NULL;
853 sc->ale_cdata.ale_tx_cmb_map = NULL;
854
855 }
856
857 int
ale_encap(struct ale_softc * sc,struct mbuf * m)858 ale_encap(struct ale_softc *sc, struct mbuf *m)
859 {
860 struct ale_txdesc *txd, *txd_last;
861 struct tx_desc *desc;
862 bus_dmamap_t map;
863 uint32_t cflags, poff, vtag;
864 int error, i, prod;
865
866 cflags = vtag = 0;
867 poff = 0;
868
869 prod = sc->ale_cdata.ale_tx_prod;
870 txd = &sc->ale_cdata.ale_txdesc[prod];
871 txd_last = txd;
872 map = txd->tx_dmamap;
873
874 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT);
875 if (error != 0 && error != EFBIG)
876 goto drop;
877 if (error != 0) {
878 if (m_defrag(m, M_DONTWAIT)) {
879 error = ENOBUFS;
880 goto drop;
881 }
882 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
883 BUS_DMA_NOWAIT);
884 if (error != 0)
885 goto drop;
886 }
887
888 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
889 BUS_DMASYNC_PREWRITE);
890
891 /* Configure Tx checksum offload. */
892 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
893 /*
894 * AR81xx supports Tx custom checksum offload feature
895 * that offloads single 16bit checksum computation.
896 * So you can choose one among IP, TCP and UDP.
897 * Normally driver sets checksum start/insertion
898 * position from the information of TCP/UDP frame as
899 * TCP/UDP checksum takes more time than that of IP.
900 * However it seems that custom checksum offload
901 * requires 4 bytes aligned Tx buffers due to hardware
902 * bug.
903 * AR81xx also supports explicit Tx checksum computation
904 * if it is told that the size of IP header and TCP
905 * header(for UDP, the header size does not matter
906 * because it's fixed length). However with this scheme
907 * TSO does not work so you have to choose one either
908 * TSO or explicit Tx checksum offload. I chosen TSO
909 * plus custom checksum offload with work-around which
910 * will cover most common usage for this consumer
911 * ethernet controller. The work-around takes a lot of
912 * CPU cycles if Tx buffer is not aligned on 4 bytes
913 * boundary, though.
914 */
915 cflags |= ALE_TD_CXSUM;
916 /* Set checksum start offset. */
917 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
918 }
919
920 #if NVLAN > 0
921 /* Configure VLAN hardware tag insertion. */
922 if (m->m_flags & M_VLANTAG) {
923 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
924 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
925 cflags |= ALE_TD_INSERT_VLAN_TAG;
926 }
927 #endif
928
929 desc = NULL;
930 for (i = 0; i < map->dm_nsegs; i++) {
931 desc = &sc->ale_cdata.ale_tx_ring[prod];
932 desc->addr = htole64(map->dm_segs[i].ds_addr);
933 desc->len =
934 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag);
935 desc->flags = htole32(cflags);
936 sc->ale_cdata.ale_tx_cnt++;
937 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
938 }
939
940 /* Update producer index. */
941 sc->ale_cdata.ale_tx_prod = prod;
942
943 /* Finally set EOP on the last descriptor. */
944 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
945 desc = &sc->ale_cdata.ale_tx_ring[prod];
946 desc->flags |= htole32(ALE_TD_EOP);
947
948 /* Swap dmamap of the first and the last. */
949 txd = &sc->ale_cdata.ale_txdesc[prod];
950 map = txd_last->tx_dmamap;
951 txd_last->tx_dmamap = txd->tx_dmamap;
952 txd->tx_dmamap = map;
953 txd->tx_m = m;
954
955 /* Sync descriptors. */
956 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0,
957 sc->ale_cdata.ale_tx_ring_map->dm_mapsize,
958 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
959
960 return (0);
961
962 drop:
963 m_freem(m);
964 return (error);
965 }
966
967 void
ale_start(struct ifnet * ifp)968 ale_start(struct ifnet *ifp)
969 {
970 struct ale_softc *sc = ifp->if_softc;
971 struct mbuf *m;
972 int enq;
973
974 /* Reclaim transmitted frames. */
975 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
976 ale_txeof(sc);
977
978 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd))
979 return;
980 if ((sc->ale_flags & ALE_FLAG_LINK) == 0)
981 return;
982 if (ifq_empty(&ifp->if_snd))
983 return;
984
985 enq = 0;
986 for (;;) {
987 /* Check descriptor overrun. */
988 if (sc->ale_cdata.ale_tx_cnt + ALE_MAXTXSEGS >=
989 ALE_TX_RING_CNT - 2) {
990 ifq_set_oactive(&ifp->if_snd);
991 break;
992 }
993
994 m = ifq_dequeue(&ifp->if_snd);
995 if (m == NULL)
996 break;
997
998 /*
999 * Pack the data into the transmit ring. If we
1000 * don't have room, set the OACTIVE flag and wait
1001 * for the NIC to drain the ring.
1002 */
1003 if (ale_encap(sc, m) != 0) {
1004 ifp->if_oerrors++;
1005 continue;
1006 }
1007
1008 enq = 1;
1009
1010 #if NBPFILTER > 0
1011 /*
1012 * If there's a BPF listener, bounce a copy of this frame
1013 * to him.
1014 */
1015 if (ifp->if_bpf != NULL)
1016 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT);
1017 #endif
1018 }
1019
1020 if (enq) {
1021 /* Kick. */
1022 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1023 sc->ale_cdata.ale_tx_prod);
1024
1025 /* Set a timeout in case the chip goes out to lunch. */
1026 ifp->if_timer = ALE_TX_TIMEOUT;
1027 }
1028 }
1029
1030 void
ale_watchdog(struct ifnet * ifp)1031 ale_watchdog(struct ifnet *ifp)
1032 {
1033 struct ale_softc *sc = ifp->if_softc;
1034
1035 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1036 printf("%s: watchdog timeout (missed link)\n",
1037 sc->sc_dev.dv_xname);
1038 ifp->if_oerrors++;
1039 ale_init(ifp);
1040 return;
1041 }
1042
1043 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
1044 ifp->if_oerrors++;
1045 ale_init(ifp);
1046 ale_start(ifp);
1047 }
1048
1049 int
ale_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data)1050 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1051 {
1052 struct ale_softc *sc = ifp->if_softc;
1053 struct mii_data *mii = &sc->sc_miibus;
1054 struct ifreq *ifr = (struct ifreq *)data;
1055 int s, error = 0;
1056
1057 s = splnet();
1058
1059 switch (cmd) {
1060 case SIOCSIFADDR:
1061 ifp->if_flags |= IFF_UP;
1062 if (!(ifp->if_flags & IFF_RUNNING))
1063 ale_init(ifp);
1064 break;
1065
1066 case SIOCSIFFLAGS:
1067 if (ifp->if_flags & IFF_UP) {
1068 if (ifp->if_flags & IFF_RUNNING)
1069 error = ENETRESET;
1070 else
1071 ale_init(ifp);
1072 } else {
1073 if (ifp->if_flags & IFF_RUNNING)
1074 ale_stop(sc);
1075 }
1076 break;
1077
1078 case SIOCSIFMEDIA:
1079 case SIOCGIFMEDIA:
1080 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1081 break;
1082
1083 default:
1084 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data);
1085 break;
1086 }
1087
1088 if (error == ENETRESET) {
1089 if (ifp->if_flags & IFF_RUNNING)
1090 ale_iff(sc);
1091 error = 0;
1092 }
1093
1094 splx(s);
1095 return (error);
1096 }
1097
1098 void
ale_mac_config(struct ale_softc * sc)1099 ale_mac_config(struct ale_softc *sc)
1100 {
1101 struct mii_data *mii;
1102 uint32_t reg;
1103
1104 mii = &sc->sc_miibus;
1105 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1106 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
1107 MAC_CFG_SPEED_MASK);
1108 /* Reprogram MAC with resolved speed/duplex. */
1109 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1110 case IFM_10_T:
1111 case IFM_100_TX:
1112 reg |= MAC_CFG_SPEED_10_100;
1113 break;
1114 case IFM_1000_T:
1115 reg |= MAC_CFG_SPEED_1000;
1116 break;
1117 }
1118 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1119 reg |= MAC_CFG_FULL_DUPLEX;
1120 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1121 reg |= MAC_CFG_TX_FC;
1122 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1123 reg |= MAC_CFG_RX_FC;
1124 }
1125 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1126 }
1127
1128 void
ale_stats_clear(struct ale_softc * sc)1129 ale_stats_clear(struct ale_softc *sc)
1130 {
1131 struct smb sb;
1132 uint32_t *reg;
1133 int i;
1134
1135 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
1136 CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
1137 i += sizeof(uint32_t);
1138 }
1139 /* Read Tx statistics. */
1140 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
1141 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
1142 i += sizeof(uint32_t);
1143 }
1144 }
1145
1146 void
ale_stats_update(struct ale_softc * sc)1147 ale_stats_update(struct ale_softc *sc)
1148 {
1149 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1150 struct ale_hw_stats *stat;
1151 struct smb sb, *smb;
1152 uint32_t *reg;
1153 int i;
1154
1155 stat = &sc->ale_stats;
1156 smb = &sb;
1157
1158 /* Read Rx statistics. */
1159 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
1160 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
1161 i += sizeof(uint32_t);
1162 }
1163 /* Read Tx statistics. */
1164 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
1165 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
1166 i += sizeof(uint32_t);
1167 }
1168
1169 /* Rx stats. */
1170 stat->rx_frames += smb->rx_frames;
1171 stat->rx_bcast_frames += smb->rx_bcast_frames;
1172 stat->rx_mcast_frames += smb->rx_mcast_frames;
1173 stat->rx_pause_frames += smb->rx_pause_frames;
1174 stat->rx_control_frames += smb->rx_control_frames;
1175 stat->rx_crcerrs += smb->rx_crcerrs;
1176 stat->rx_lenerrs += smb->rx_lenerrs;
1177 stat->rx_bytes += smb->rx_bytes;
1178 stat->rx_runts += smb->rx_runts;
1179 stat->rx_fragments += smb->rx_fragments;
1180 stat->rx_pkts_64 += smb->rx_pkts_64;
1181 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
1182 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
1183 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
1184 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
1185 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
1186 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
1187 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
1188 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
1189 stat->rx_rrs_errs += smb->rx_rrs_errs;
1190 stat->rx_alignerrs += smb->rx_alignerrs;
1191 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
1192 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
1193 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
1194
1195 /* Tx stats. */
1196 stat->tx_frames += smb->tx_frames;
1197 stat->tx_bcast_frames += smb->tx_bcast_frames;
1198 stat->tx_mcast_frames += smb->tx_mcast_frames;
1199 stat->tx_pause_frames += smb->tx_pause_frames;
1200 stat->tx_excess_defer += smb->tx_excess_defer;
1201 stat->tx_control_frames += smb->tx_control_frames;
1202 stat->tx_deferred += smb->tx_deferred;
1203 stat->tx_bytes += smb->tx_bytes;
1204 stat->tx_pkts_64 += smb->tx_pkts_64;
1205 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
1206 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
1207 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
1208 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
1209 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
1210 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
1211 stat->tx_single_colls += smb->tx_single_colls;
1212 stat->tx_multi_colls += smb->tx_multi_colls;
1213 stat->tx_late_colls += smb->tx_late_colls;
1214 stat->tx_excess_colls += smb->tx_excess_colls;
1215 stat->tx_underrun += smb->tx_underrun;
1216 stat->tx_desc_underrun += smb->tx_desc_underrun;
1217 stat->tx_lenerrs += smb->tx_lenerrs;
1218 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
1219 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
1220 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
1221
1222 ifp->if_collisions += smb->tx_single_colls +
1223 smb->tx_multi_colls * 2 + smb->tx_late_colls +
1224 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT;
1225
1226 ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls +
1227 smb->tx_underrun + smb->tx_pkts_truncated;
1228
1229 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
1230 smb->rx_runts + smb->rx_pkts_truncated +
1231 smb->rx_fifo_oflows + smb->rx_rrs_errs +
1232 smb->rx_alignerrs;
1233 }
1234
1235 int
ale_intr(void * xsc)1236 ale_intr(void *xsc)
1237 {
1238 struct ale_softc *sc = xsc;
1239 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1240 uint32_t status;
1241
1242 status = CSR_READ_4(sc, ALE_INTR_STATUS);
1243 if ((status & ALE_INTRS) == 0)
1244 return (0);
1245
1246 /* Acknowledge and disable interrupts. */
1247 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
1248
1249 if (ifp->if_flags & IFF_RUNNING) {
1250 int error;
1251
1252 error = ale_rxeof(sc);
1253 if (error) {
1254 sc->ale_stats.reset_brk_seq++;
1255 ale_init(ifp);
1256 return (0);
1257 }
1258
1259 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) {
1260 if (status & INTR_DMA_RD_TO_RST)
1261 printf("%s: DMA read error! -- resetting\n",
1262 sc->sc_dev.dv_xname);
1263 if (status & INTR_DMA_WR_TO_RST)
1264 printf("%s: DMA write error! -- resetting\n",
1265 sc->sc_dev.dv_xname);
1266 ale_init(ifp);
1267 return (0);
1268 }
1269
1270 ale_txeof(sc);
1271 ale_start(ifp);
1272 }
1273
1274 /* Re-enable interrupts. */
1275 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
1276 return (1);
1277 }
1278
1279 void
ale_txeof(struct ale_softc * sc)1280 ale_txeof(struct ale_softc *sc)
1281 {
1282 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1283 struct ale_txdesc *txd;
1284 uint32_t cons, prod;
1285 int prog;
1286
1287 if (sc->ale_cdata.ale_tx_cnt == 0)
1288 return;
1289
1290 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0,
1291 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1292 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
1293 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0,
1294 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize,
1295 BUS_DMASYNC_POSTREAD);
1296 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
1297 } else
1298 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
1299 cons = sc->ale_cdata.ale_tx_cons;
1300 /*
1301 * Go through our Tx list and free mbufs for those
1302 * frames which have been transmitted.
1303 */
1304 for (prog = 0; cons != prod; prog++,
1305 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
1306 if (sc->ale_cdata.ale_tx_cnt <= 0)
1307 break;
1308 prog++;
1309 ifq_clr_oactive(&ifp->if_snd);
1310 sc->ale_cdata.ale_tx_cnt--;
1311 txd = &sc->ale_cdata.ale_txdesc[cons];
1312 if (txd->tx_m != NULL) {
1313 /* Reclaim transmitted mbufs. */
1314 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0,
1315 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1316 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap);
1317 m_freem(txd->tx_m);
1318 txd->tx_m = NULL;
1319 }
1320 }
1321
1322 if (prog > 0) {
1323 sc->ale_cdata.ale_tx_cons = cons;
1324 /*
1325 * Unarm watchdog timer only when there is no pending
1326 * Tx descriptors in queue.
1327 */
1328 if (sc->ale_cdata.ale_tx_cnt == 0)
1329 ifp->if_timer = 0;
1330 }
1331 }
1332
1333 void
ale_rx_update_page(struct ale_softc * sc,struct ale_rx_page ** page,uint32_t length,uint32_t * prod)1334 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
1335 uint32_t length, uint32_t *prod)
1336 {
1337 struct ale_rx_page *rx_page;
1338
1339 rx_page = *page;
1340 /* Update consumer position. */
1341 rx_page->cons += roundup(length + sizeof(struct rx_rs),
1342 ALE_RX_PAGE_ALIGN);
1343 if (rx_page->cons >= ALE_RX_PAGE_SZ) {
1344 /*
1345 * End of Rx page reached, let hardware reuse
1346 * this page.
1347 */
1348 rx_page->cons = 0;
1349 *rx_page->cmb_addr = 0;
1350 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0,
1351 rx_page->cmb_map->dm_mapsize,
1352 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1353 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
1354 RXF_VALID);
1355 /* Switch to alternate Rx page. */
1356 sc->ale_cdata.ale_rx_curp ^= 1;
1357 rx_page = *page =
1358 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
1359 /* Page flipped, sync CMB and Rx page. */
1360 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0,
1361 rx_page->page_map->dm_mapsize,
1362 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1363 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0,
1364 rx_page->cmb_map->dm_mapsize,
1365 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1366 /* Sync completed, cache updated producer index. */
1367 *prod = *rx_page->cmb_addr;
1368 }
1369 }
1370
1371
1372 /*
1373 * It seems that AR81xx controller can compute partial checksum.
1374 * The partial checksum value can be used to accelerate checksum
1375 * computation for fragmented TCP/UDP packets. Upper network stack
1376 * already takes advantage of the partial checksum value in IP
1377 * reassembly stage. But I'm not sure the correctness of the
1378 * partial hardware checksum assistance due to lack of data sheet.
1379 * In addition, the Rx feature of controller that requires copying
1380 * for every frames effectively nullifies one of most nice offload
1381 * capability of controller.
1382 */
1383 void
ale_rxcsum(struct ale_softc * sc,struct mbuf * m,uint32_t status)1384 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
1385 {
1386 struct ip *ip;
1387 char *p;
1388
1389 if ((status & ALE_RD_IPCSUM_NOK) == 0)
1390 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK;
1391
1392 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
1393 if (((status & ALE_RD_IPV4_FRAG) == 0) &&
1394 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
1395 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
1396 m->m_pkthdr.csum_flags |=
1397 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK;
1398 }
1399 } else {
1400 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
1401 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
1402 p = mtod(m, char *);
1403 p += ETHER_HDR_LEN;
1404 if ((status & ALE_RD_802_3) != 0)
1405 p += LLC_SNAPFRAMELEN;
1406 #if NVLAN > 0
1407 if (status & ALE_RD_VLAN)
1408 p += EVL_ENCAPLEN;
1409 #endif
1410 ip = (struct ip *)p;
1411 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
1412 return;
1413 m->m_pkthdr.csum_flags |=
1414 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK;
1415 }
1416 }
1417 /*
1418 * Don't mark bad checksum for TCP/UDP frames
1419 * as fragmented frames may always have set
1420 * bad checksummed bit of frame status.
1421 */
1422 }
1423
1424 /* Process received frames. */
1425 int
ale_rxeof(struct ale_softc * sc)1426 ale_rxeof(struct ale_softc *sc)
1427 {
1428 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1429 struct mbuf_list ml = MBUF_LIST_INITIALIZER();
1430 struct ale_rx_page *rx_page;
1431 struct rx_rs *rs;
1432 struct mbuf *m;
1433 uint32_t length, prod, seqno, status;
1434 int prog;
1435
1436 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
1437 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0,
1438 rx_page->cmb_map->dm_mapsize,
1439 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1440 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0,
1441 rx_page->page_map->dm_mapsize,
1442 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1443 /*
1444 * Don't directly access producer index as hardware may
1445 * update it while Rx handler is in progress. It would
1446 * be even better if there is a way to let hardware
1447 * know how far driver processed its received frames.
1448 * Alternatively, hardware could provide a way to disable
1449 * CMB updates until driver acknowledges the end of CMB
1450 * access.
1451 */
1452 prod = *rx_page->cmb_addr;
1453 for (prog = 0; ; prog++) {
1454 if (rx_page->cons >= prod)
1455 break;
1456 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
1457 seqno = ALE_RX_SEQNO(letoh32(rs->seqno));
1458 if (sc->ale_cdata.ale_rx_seqno != seqno) {
1459 /*
1460 * Normally I believe this should not happen unless
1461 * severe driver bug or corrupted memory. However
1462 * it seems to happen under certain conditions which
1463 * is triggered by abrupt Rx events such as initiation
1464 * of bulk transfer of remote host. It's not easy to
1465 * reproduce this and I doubt it could be related
1466 * with FIFO overflow of hardware or activity of Tx
1467 * CMB updates. I also remember similar behaviour
1468 * seen on Realtek 8139 which uses resembling Rx
1469 * scheme.
1470 */
1471 if (aledebug)
1472 printf("%s: garbled seq: %u, expected: %u -- "
1473 "resetting!\n", sc->sc_dev.dv_xname,
1474 seqno, sc->ale_cdata.ale_rx_seqno);
1475 return (EIO);
1476 }
1477 /* Frame received. */
1478 sc->ale_cdata.ale_rx_seqno++;
1479 length = ALE_RX_BYTES(letoh32(rs->length));
1480 status = letoh32(rs->flags);
1481 if (status & ALE_RD_ERROR) {
1482 /*
1483 * We want to pass the following frames to upper
1484 * layer regardless of error status of Rx return
1485 * status.
1486 *
1487 * o IP/TCP/UDP checksum is bad.
1488 * o frame length and protocol specific length
1489 * does not match.
1490 */
1491 if (status & (ALE_RD_CRC | ALE_RD_CODE |
1492 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
1493 ALE_RD_TRUNC)) {
1494 ale_rx_update_page(sc, &rx_page, length, &prod);
1495 continue;
1496 }
1497 }
1498 /*
1499 * m_devget(9) is major bottle-neck of ale(4)(It comes
1500 * from hardware limitation). For jumbo frames we could
1501 * get a slightly better performance if driver use
1502 * m_getjcl(9) with proper buffer size argument. However
1503 * that would make code more complicated and I don't
1504 * think users would expect good Rx performance numbers
1505 * on these low-end consumer ethernet controller.
1506 */
1507 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
1508 ETHER_ALIGN);
1509 if (m == NULL) {
1510 ifp->if_iqdrops++;
1511 ale_rx_update_page(sc, &rx_page, length, &prod);
1512 continue;
1513 }
1514 if (status & ALE_RD_IPV4)
1515 ale_rxcsum(sc, m, status);
1516 #if NVLAN > 0
1517 if (status & ALE_RD_VLAN) {
1518 uint32_t vtags = ALE_RX_VLAN(letoh32(rs->vtags));
1519 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags);
1520 m->m_flags |= M_VLANTAG;
1521 }
1522 #endif
1523
1524 ml_enqueue(&ml, m);
1525
1526 ale_rx_update_page(sc, &rx_page, length, &prod);
1527 }
1528
1529 if_input(ifp, &ml);
1530
1531 return 0;
1532 }
1533
1534 void
ale_tick(void * xsc)1535 ale_tick(void *xsc)
1536 {
1537 struct ale_softc *sc = xsc;
1538 struct mii_data *mii = &sc->sc_miibus;
1539 int s;
1540
1541 s = splnet();
1542 mii_tick(mii);
1543 ale_stats_update(sc);
1544
1545 timeout_add_sec(&sc->ale_tick_ch, 1);
1546 splx(s);
1547 }
1548
1549 void
ale_reset(struct ale_softc * sc)1550 ale_reset(struct ale_softc *sc)
1551 {
1552 uint32_t reg;
1553 int i;
1554
1555 /* Initialize PCIe module. From Linux. */
1556 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
1557
1558 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
1559 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
1560 DELAY(10);
1561 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
1562 break;
1563 }
1564 if (i == 0)
1565 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname);
1566
1567 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
1568 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
1569 break;
1570 DELAY(10);
1571 }
1572
1573 if (i == 0)
1574 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname,
1575 reg);
1576 }
1577
1578 int
ale_init(struct ifnet * ifp)1579 ale_init(struct ifnet *ifp)
1580 {
1581 struct ale_softc *sc = ifp->if_softc;
1582 struct mii_data *mii;
1583 uint8_t eaddr[ETHER_ADDR_LEN];
1584 bus_addr_t paddr;
1585 uint32_t reg, rxf_hi, rxf_lo;
1586
1587 /*
1588 * Cancel any pending I/O.
1589 */
1590 ale_stop(sc);
1591
1592 /*
1593 * Reset the chip to a known state.
1594 */
1595 ale_reset(sc);
1596
1597 /* Initialize Tx descriptors, DMA memory blocks. */
1598 ale_init_rx_pages(sc);
1599 ale_init_tx_ring(sc);
1600
1601 /* Reprogram the station address. */
1602 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN);
1603 CSR_WRITE_4(sc, ALE_PAR0,
1604 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
1605 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
1606
1607 /*
1608 * Clear WOL status and disable all WOL feature as WOL
1609 * would interfere Rx operation under normal environments.
1610 */
1611 CSR_READ_4(sc, ALE_WOL_CFG);
1612 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1613
1614 /*
1615 * Set Tx descriptor/RXF0/CMB base addresses. They share
1616 * the same high address part of DMAable region.
1617 */
1618 paddr = sc->ale_cdata.ale_tx_ring_paddr;
1619 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
1620 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
1621 CSR_WRITE_4(sc, ALE_TPD_CNT,
1622 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
1623
1624 /* Set Rx page base address, note we use single queue. */
1625 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
1626 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
1627 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
1628 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
1629
1630 /* Set Tx/Rx CMB addresses. */
1631 paddr = sc->ale_cdata.ale_tx_cmb_paddr;
1632 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
1633 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
1634 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
1635 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
1636 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
1637
1638 /* Mark RXF0 is valid. */
1639 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
1640 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
1641 /*
1642 * No need to initialize RFX1/RXF2/RXF3. We don't use
1643 * multi-queue yet.
1644 */
1645
1646 /* Set Rx page size, excluding guard frame size. */
1647 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
1648
1649 /* Tell hardware that we're ready to load DMA blocks. */
1650 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
1651
1652 /* Set Rx/Tx interrupt trigger threshold. */
1653 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
1654 (4 << INT_TRIG_TX_THRESH_SHIFT));
1655 /*
1656 * XXX
1657 * Set interrupt trigger timer, its purpose and relation
1658 * with interrupt moderation mechanism is not clear yet.
1659 */
1660 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
1661 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
1662 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
1663
1664 /* Configure interrupt moderation timer. */
1665 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
1666 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
1667 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
1668 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
1669 CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
1670 reg = CSR_READ_4(sc, ALE_MASTER_CFG);
1671 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
1672 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
1673 if (ALE_USECS(sc->ale_int_rx_mod) != 0)
1674 reg |= MASTER_IM_RX_TIMER_ENB;
1675 if (ALE_USECS(sc->ale_int_tx_mod) != 0)
1676 reg |= MASTER_IM_TX_TIMER_ENB;
1677 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
1678 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
1679
1680 /* Set Maximum frame size of controller. */
1681 if (ifp->if_mtu < ETHERMTU)
1682 sc->ale_max_frame_size = ETHERMTU;
1683 else
1684 sc->ale_max_frame_size = ifp->if_mtu;
1685 sc->ale_max_frame_size += ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN;
1686 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
1687
1688 /* Configure IPG/IFG parameters. */
1689 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
1690 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
1691 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
1692 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
1693 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
1694
1695 /* Set parameters for half-duplex media. */
1696 CSR_WRITE_4(sc, ALE_HDPX_CFG,
1697 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
1698 HDPX_CFG_LCOL_MASK) |
1699 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
1700 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
1701 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
1702 HDPX_CFG_ABEBT_MASK) |
1703 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
1704 HDPX_CFG_JAMIPG_MASK));
1705
1706 /* Configure Tx jumbo frame parameters. */
1707 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
1708 if (ifp->if_mtu < ETHERMTU)
1709 reg = sc->ale_max_frame_size;
1710 else if (ifp->if_mtu < 6 * 1024)
1711 reg = (sc->ale_max_frame_size * 2) / 3;
1712 else
1713 reg = sc->ale_max_frame_size / 2;
1714 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
1715 roundup(reg, TX_JUMBO_THRESH_UNIT) >>
1716 TX_JUMBO_THRESH_UNIT_SHIFT);
1717 }
1718
1719 /* Configure TxQ. */
1720 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
1721 << TXQ_CFG_TX_FIFO_BURST_SHIFT;
1722 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
1723 TXQ_CFG_TPD_BURST_MASK;
1724 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
1725
1726 /* Configure Rx jumbo frame & flow control parameters. */
1727 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
1728 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
1729 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
1730 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
1731 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
1732 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
1733 RX_JUMBO_LKAH_MASK));
1734 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
1735 rxf_hi = (reg * 7) / 10;
1736 rxf_lo = (reg * 3)/ 10;
1737 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
1738 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
1739 RX_FIFO_PAUSE_THRESH_LO_MASK) |
1740 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
1741 RX_FIFO_PAUSE_THRESH_HI_MASK));
1742 }
1743
1744 /* Disable RSS. */
1745 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
1746 CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
1747
1748 /* Configure RxQ. */
1749 CSR_WRITE_4(sc, ALE_RXQ_CFG,
1750 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
1751
1752 /* Configure DMA parameters. */
1753 reg = 0;
1754 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
1755 reg |= DMA_CFG_TXCMB_ENB;
1756 CSR_WRITE_4(sc, ALE_DMA_CFG,
1757 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
1758 sc->ale_dma_rd_burst | reg |
1759 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
1760 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
1761 DMA_CFG_RD_DELAY_CNT_MASK) |
1762 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
1763 DMA_CFG_WR_DELAY_CNT_MASK));
1764
1765 /*
1766 * Hardware can be configured to issue SMB interrupt based
1767 * on programmed interval. Since there is a callout that is
1768 * invoked for every hz in driver we use that instead of
1769 * relying on periodic SMB interrupt.
1770 */
1771 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
1772
1773 /* Clear MAC statistics. */
1774 ale_stats_clear(sc);
1775
1776 /*
1777 * Configure Tx/Rx MACs.
1778 * - Auto-padding for short frames.
1779 * - Enable CRC generation.
1780 * Actual reconfiguration of MAC for resolved speed/duplex
1781 * is followed after detection of link establishment.
1782 * AR81xx always does checksum computation regardless of
1783 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
1784 * cause Rx handling issue for fragmented IP datagrams due
1785 * to silicon bug.
1786 */
1787 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
1788 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
1789 MAC_CFG_PREAMBLE_MASK);
1790 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
1791 reg |= MAC_CFG_SPEED_10_100;
1792 else
1793 reg |= MAC_CFG_SPEED_1000;
1794 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1795
1796 /* Set up the receive filter. */
1797 ale_iff(sc);
1798
1799 ale_rxvlan(sc);
1800
1801 /* Acknowledge all pending interrupts and clear it. */
1802 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
1803 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
1804 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
1805
1806 sc->ale_flags &= ~ALE_FLAG_LINK;
1807
1808 /* Switch to the current media. */
1809 mii = &sc->sc_miibus;
1810 mii_mediachg(mii);
1811
1812 timeout_add_sec(&sc->ale_tick_ch, 1);
1813
1814 ifp->if_flags |= IFF_RUNNING;
1815 ifq_clr_oactive(&ifp->if_snd);
1816
1817 return 0;
1818 }
1819
1820 void
ale_stop(struct ale_softc * sc)1821 ale_stop(struct ale_softc *sc)
1822 {
1823 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1824 struct ale_txdesc *txd;
1825 uint32_t reg;
1826 int i;
1827
1828 /*
1829 * Mark the interface down and cancel the watchdog timer.
1830 */
1831 ifp->if_flags &= ~IFF_RUNNING;
1832 ifq_clr_oactive(&ifp->if_snd);
1833 ifp->if_timer = 0;
1834
1835 timeout_del(&sc->ale_tick_ch);
1836 sc->ale_flags &= ~ALE_FLAG_LINK;
1837
1838 ale_stats_update(sc);
1839
1840 /* Disable interrupts. */
1841 CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
1842 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
1843
1844 /* Disable queue processing and DMA. */
1845 reg = CSR_READ_4(sc, ALE_TXQ_CFG);
1846 reg &= ~TXQ_CFG_ENB;
1847 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
1848 reg = CSR_READ_4(sc, ALE_RXQ_CFG);
1849 reg &= ~RXQ_CFG_ENB;
1850 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
1851 reg = CSR_READ_4(sc, ALE_DMA_CFG);
1852 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
1853 CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
1854 DELAY(1000);
1855
1856 /* Stop Rx/Tx MACs. */
1857 ale_stop_mac(sc);
1858
1859 /* Disable interrupts again? XXX */
1860 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
1861
1862 /*
1863 * Free TX mbufs still in the queues.
1864 */
1865 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1866 txd = &sc->ale_cdata.ale_txdesc[i];
1867 if (txd->tx_m != NULL) {
1868 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0,
1869 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1870 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap);
1871 m_freem(txd->tx_m);
1872 txd->tx_m = NULL;
1873 }
1874 }
1875 }
1876
1877 void
ale_stop_mac(struct ale_softc * sc)1878 ale_stop_mac(struct ale_softc *sc)
1879 {
1880 uint32_t reg;
1881 int i;
1882
1883 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1884 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
1885 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
1886 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1887 }
1888
1889 for (i = ALE_TIMEOUT; i > 0; i--) {
1890 reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
1891 if (reg == 0)
1892 break;
1893 DELAY(10);
1894 }
1895 if (i == 0)
1896 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n",
1897 sc->sc_dev.dv_xname, reg);
1898 }
1899
1900 void
ale_init_tx_ring(struct ale_softc * sc)1901 ale_init_tx_ring(struct ale_softc *sc)
1902 {
1903 struct ale_txdesc *txd;
1904 int i;
1905
1906 sc->ale_cdata.ale_tx_prod = 0;
1907 sc->ale_cdata.ale_tx_cons = 0;
1908 sc->ale_cdata.ale_tx_cnt = 0;
1909
1910 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
1911 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
1912 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1913 txd = &sc->ale_cdata.ale_txdesc[i];
1914 txd->tx_m = NULL;
1915 }
1916 *sc->ale_cdata.ale_tx_cmb = 0;
1917 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0,
1918 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize,
1919 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1920 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0,
1921 sc->ale_cdata.ale_tx_ring_map->dm_mapsize,
1922 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1923 }
1924
1925 void
ale_init_rx_pages(struct ale_softc * sc)1926 ale_init_rx_pages(struct ale_softc *sc)
1927 {
1928 struct ale_rx_page *rx_page;
1929 int i;
1930
1931 sc->ale_cdata.ale_rx_seqno = 0;
1932 sc->ale_cdata.ale_rx_curp = 0;
1933
1934 for (i = 0; i < ALE_RX_PAGES; i++) {
1935 rx_page = &sc->ale_cdata.ale_rx_page[i];
1936 bzero(rx_page->page_addr, sc->ale_pagesize);
1937 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
1938 rx_page->cons = 0;
1939 *rx_page->cmb_addr = 0;
1940 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0,
1941 rx_page->page_map->dm_mapsize,
1942 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1943 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0,
1944 rx_page->cmb_map->dm_mapsize,
1945 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1946 }
1947 }
1948
1949 void
ale_rxvlan(struct ale_softc * sc)1950 ale_rxvlan(struct ale_softc *sc)
1951 {
1952 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1953 uint32_t reg;
1954
1955 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1956 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
1957 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)
1958 reg |= MAC_CFG_VLAN_TAG_STRIP;
1959 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1960 }
1961
1962 void
ale_iff(struct ale_softc * sc)1963 ale_iff(struct ale_softc *sc)
1964 {
1965 struct arpcom *ac = &sc->sc_arpcom;
1966 struct ifnet *ifp = &ac->ac_if;
1967 struct ether_multi *enm;
1968 struct ether_multistep step;
1969 uint32_t crc;
1970 uint32_t mchash[2];
1971 uint32_t rxcfg;
1972
1973 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
1974 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
1975 ifp->if_flags &= ~IFF_ALLMULTI;
1976
1977 /*
1978 * Always accept broadcast frames.
1979 */
1980 rxcfg |= MAC_CFG_BCAST;
1981
1982 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) {
1983 ifp->if_flags |= IFF_ALLMULTI;
1984 if (ifp->if_flags & IFF_PROMISC)
1985 rxcfg |= MAC_CFG_PROMISC;
1986 else
1987 rxcfg |= MAC_CFG_ALLMULTI;
1988 mchash[0] = mchash[1] = 0xFFFFFFFF;
1989 } else {
1990 /* Program new filter. */
1991 bzero(mchash, sizeof(mchash));
1992
1993 ETHER_FIRST_MULTI(step, ac, enm);
1994 while (enm != NULL) {
1995 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
1996
1997 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
1998
1999 ETHER_NEXT_MULTI(step, enm);
2000 }
2001 }
2002
2003 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
2004 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
2005 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
2006 }
2007