1 /* $OpenBSD: if_ale.c,v 1.9 2009/09/13 14:42:52 krw Exp $ */ 2 /*- 3 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 29 */ 30 31 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 32 33 #include "bpfilter.h" 34 #include "vlan.h" 35 36 #include <sys/param.h> 37 #include <sys/proc.h> 38 #include <sys/endian.h> 39 #include <sys/systm.h> 40 #include <sys/types.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/queue.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/timeout.h> 47 #include <sys/socket.h> 48 49 #include <machine/bus.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_ether.h> 62 #endif 63 64 #include <net/if_types.h> 65 #include <net/if_vlan_var.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #include <dev/rndvar.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_alereg.h> 81 82 int ale_match(struct device *, void *, void *); 83 void ale_attach(struct device *, struct device *, void *); 84 int ale_detach(struct device *, int); 85 86 int ale_miibus_readreg(struct device *, int, int); 87 void ale_miibus_writereg(struct device *, int, int, int); 88 void ale_miibus_statchg(struct device *); 89 90 int ale_init(struct ifnet *); 91 void ale_start(struct ifnet *); 92 int ale_ioctl(struct ifnet *, u_long, caddr_t); 93 void ale_watchdog(struct ifnet *); 94 int ale_mediachange(struct ifnet *); 95 void ale_mediastatus(struct ifnet *, struct ifmediareq *); 96 97 int ale_intr(void *); 98 int ale_rxeof(struct ale_softc *sc); 99 void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 100 uint32_t, uint32_t *); 101 void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 102 void ale_txeof(struct ale_softc *); 103 104 int ale_dma_alloc(struct ale_softc *); 105 void ale_dma_free(struct ale_softc *); 106 int ale_encap(struct ale_softc *, struct mbuf **); 107 void ale_init_rx_pages(struct ale_softc *); 108 void ale_init_tx_ring(struct ale_softc *); 109 110 void ale_stop(struct ale_softc *); 111 void ale_tick(void *); 112 void ale_get_macaddr(struct ale_softc *); 113 void ale_mac_config(struct ale_softc *); 114 void ale_phy_reset(struct ale_softc *); 115 void ale_reset(struct ale_softc *); 116 void ale_rxfilter(struct ale_softc *); 117 void ale_rxvlan(struct ale_softc *); 118 void ale_stats_clear(struct ale_softc *); 119 void ale_stats_update(struct ale_softc *); 120 void ale_stop_mac(struct ale_softc *); 121 122 const struct pci_matchid ale_devices[] = { 123 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1E } 124 }; 125 126 struct cfattach ale_ca = { 127 sizeof (struct ale_softc), ale_match, ale_attach 128 }; 129 130 struct cfdriver ale_cd = { 131 NULL, "ale", DV_IFNET 132 }; 133 134 int aledebug = 0; 135 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 136 137 #define ALE_CSUM_FEATURES (M_TCPV4_CSUM_OUT | M_UDPV4_CSUM_OUT) 138 139 int 140 ale_miibus_readreg(struct device *dev, int phy, int reg) 141 { 142 struct ale_softc *sc = (struct ale_softc *)dev; 143 uint32_t v; 144 int i; 145 146 if (phy != sc->ale_phyaddr) 147 return (0); 148 149 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 150 if (reg == MII_100T2CR || reg == MII_100T2SR || 151 reg == MII_EXTSR) 152 return (0); 153 } 154 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 155 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 156 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 157 DELAY(5); 158 v = CSR_READ_4(sc, ALE_MDIO); 159 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 160 break; 161 } 162 163 if (i == 0) { 164 printf("%s: phy read timeout: phy %d, reg %d\n", 165 sc->sc_dev.dv_xname, phy, reg); 166 return (0); 167 } 168 169 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 170 } 171 172 void 173 ale_miibus_writereg(struct device *dev, int phy, int reg, int val) 174 { 175 struct ale_softc *sc = (struct ale_softc *)dev; 176 uint32_t v; 177 int i; 178 179 if (phy != sc->ale_phyaddr) 180 return; 181 182 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 183 if (reg == MII_100T2CR || reg == MII_100T2SR || 184 reg == MII_EXTSR) 185 return; 186 } 187 188 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 189 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 190 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 191 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 192 DELAY(5); 193 v = CSR_READ_4(sc, ALE_MDIO); 194 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 195 break; 196 } 197 198 if (i == 0) 199 printf("%s: phy write timeout: phy %d, reg %d\n", 200 sc->sc_dev.dv_xname, phy, reg); 201 } 202 203 void 204 ale_miibus_statchg(struct device *dev) 205 { 206 struct ale_softc *sc = (struct ale_softc *)dev; 207 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 208 struct mii_data *mii; 209 uint32_t reg; 210 211 if ((ifp->if_flags & IFF_RUNNING) == 0) 212 return; 213 214 mii = &sc->sc_miibus; 215 216 sc->ale_flags &= ~ALE_FLAG_LINK; 217 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 218 (IFM_ACTIVE | IFM_AVALID)) { 219 switch (IFM_SUBTYPE(mii->mii_media_active)) { 220 case IFM_10_T: 221 case IFM_100_TX: 222 sc->ale_flags |= ALE_FLAG_LINK; 223 break; 224 225 case IFM_1000_T: 226 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 227 sc->ale_flags |= ALE_FLAG_LINK; 228 break; 229 230 default: 231 break; 232 } 233 } 234 235 /* Stop Rx/Tx MACs. */ 236 ale_stop_mac(sc); 237 238 /* Program MACs with resolved speed/duplex/flow-control. */ 239 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 240 ale_mac_config(sc); 241 /* Reenable Tx/Rx MACs. */ 242 reg = CSR_READ_4(sc, ALE_MAC_CFG); 243 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 244 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 245 } 246 } 247 248 void 249 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 250 { 251 struct ale_softc *sc = ifp->if_softc; 252 struct mii_data *mii = &sc->sc_miibus; 253 254 mii_pollstat(mii); 255 ifmr->ifm_status = mii->mii_media_status; 256 ifmr->ifm_active = mii->mii_media_active; 257 } 258 259 int 260 ale_mediachange(struct ifnet *ifp) 261 { 262 struct ale_softc *sc = ifp->if_softc; 263 struct mii_data *mii = &sc->sc_miibus; 264 int error; 265 266 if (mii->mii_instance != 0) { 267 struct mii_softc *miisc; 268 269 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 270 mii_phy_reset(miisc); 271 } 272 error = mii_mediachg(mii); 273 274 return (error); 275 } 276 277 int 278 ale_match(struct device *dev, void *match, void *aux) 279 { 280 return pci_matchbyid((struct pci_attach_args *)aux, ale_devices, 281 sizeof (ale_devices) / sizeof (ale_devices[0])); 282 } 283 284 void 285 ale_get_macaddr(struct ale_softc *sc) 286 { 287 uint32_t ea[2], reg; 288 int i, vpdc; 289 290 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 291 if ((reg & SPI_VPD_ENB) != 0) { 292 reg &= ~SPI_VPD_ENB; 293 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 294 } 295 296 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 297 &vpdc, NULL)) { 298 /* 299 * PCI VPD capability found, let TWSI reload EEPROM. 300 * This will set ethernet address of controller. 301 */ 302 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 303 TWSI_CTRL_SW_LD_START); 304 for (i = 100; i > 0; i--) { 305 DELAY(1000); 306 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 307 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 308 break; 309 } 310 if (i == 0) 311 printf("%s: reloading EEPROM timeout!\n", 312 sc->sc_dev.dv_xname); 313 } else { 314 if (aledebug) 315 printf("%s: PCI VPD capability not found!\n", 316 sc->sc_dev.dv_xname); 317 } 318 319 ea[0] = CSR_READ_4(sc, ALE_PAR0); 320 ea[1] = CSR_READ_4(sc, ALE_PAR1); 321 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 322 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 323 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 324 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 325 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 326 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 327 } 328 329 void 330 ale_phy_reset(struct ale_softc *sc) 331 { 332 /* Reset magic from Linux. */ 333 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 334 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 335 GPHY_CTRL_PHY_PLL_ON); 336 DELAY(1000); 337 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 338 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 339 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 340 DELAY(1000); 341 342 #define ATPHY_DBG_ADDR 0x1D 343 #define ATPHY_DBG_DATA 0x1E 344 345 /* Enable hibernation mode. */ 346 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 347 ATPHY_DBG_ADDR, 0x0B); 348 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 349 ATPHY_DBG_DATA, 0xBC00); 350 /* Set Class A/B for all modes. */ 351 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 352 ATPHY_DBG_ADDR, 0x00); 353 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 354 ATPHY_DBG_DATA, 0x02EF); 355 /* Enable 10BT power saving. */ 356 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 357 ATPHY_DBG_ADDR, 0x12); 358 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 359 ATPHY_DBG_DATA, 0x4C04); 360 /* Adjust 1000T power. */ 361 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 362 ATPHY_DBG_ADDR, 0x04); 363 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 364 ATPHY_DBG_ADDR, 0x8BBB); 365 /* 10BT center tap voltage. */ 366 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 367 ATPHY_DBG_ADDR, 0x05); 368 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 369 ATPHY_DBG_ADDR, 0x2C46); 370 371 #undef ATPHY_DBG_ADDR 372 #undef ATPHY_DBG_DATA 373 DELAY(1000); 374 } 375 376 void 377 ale_attach(struct device *parent, struct device *self, void *aux) 378 { 379 struct ale_softc *sc = (struct ale_softc *)self; 380 struct pci_attach_args *pa = aux; 381 pci_chipset_tag_t pc = pa->pa_pc; 382 pci_intr_handle_t ih; 383 const char *intrstr; 384 struct ifnet *ifp; 385 pcireg_t memtype; 386 int mii_flags, error = 0; 387 uint32_t rxf_len, txf_len; 388 const char *chipname; 389 390 /* 391 * Allocate IO memory 392 */ 393 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALE_PCIR_BAR); 394 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 395 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 396 printf(": can't map mem space\n"); 397 return; 398 } 399 400 if (pci_intr_map(pa, &ih) != 0) { 401 printf(": can't map interrupt\n"); 402 goto fail; 403 } 404 405 /* 406 * Allocate IRQ 407 */ 408 intrstr = pci_intr_string(pc, ih); 409 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc, 410 sc->sc_dev.dv_xname); 411 if (sc->sc_irq_handle == NULL) { 412 printf(": could not establish interrupt"); 413 if (intrstr != NULL) 414 printf(" at %s", intrstr); 415 printf("\n"); 416 goto fail; 417 } 418 419 sc->sc_dmat = pa->pa_dmat; 420 sc->sc_pct = pa->pa_pc; 421 sc->sc_pcitag = pa->pa_tag; 422 423 /* Set PHY address. */ 424 sc->ale_phyaddr = ALE_PHY_ADDR; 425 426 /* Reset PHY. */ 427 ale_phy_reset(sc); 428 429 /* Reset the ethernet controller. */ 430 ale_reset(sc); 431 432 /* Get PCI and chip id/revision. */ 433 sc->ale_rev = PCI_REVISION(pa->pa_class); 434 if (sc->ale_rev >= 0xF0) { 435 /* L2E Rev. B. AR8114 */ 436 sc->ale_flags |= ALE_FLAG_FASTETHER; 437 chipname = "AR8114"; 438 } else { 439 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 440 /* L1E AR8121 */ 441 sc->ale_flags |= ALE_FLAG_JUMBO; 442 chipname = "AR8121"; 443 } else { 444 /* L2E Rev. A. AR8113 */ 445 sc->ale_flags |= ALE_FLAG_FASTETHER; 446 chipname = "AR8113"; 447 } 448 } 449 450 printf(": %s, %s", chipname, intrstr); 451 452 /* 453 * All known controllers seems to require 4 bytes alignment 454 * of Tx buffers to make Tx checksum offload with custom 455 * checksum generation method work. 456 */ 457 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 458 459 /* 460 * All known controllers seems to have issues on Rx checksum 461 * offload for fragmented IP datagrams. 462 */ 463 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 464 465 /* 466 * Don't use Tx CMB. It is known to cause RRS update failure 467 * under certain circumstances. Typical phenomenon of the 468 * issue would be unexpected sequence number encountered in 469 * Rx handler. 470 */ 471 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 472 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 473 MASTER_CHIP_REV_SHIFT; 474 if (aledebug) { 475 printf("%s: PCI device revision : 0x%04x\n", 476 sc->sc_dev.dv_xname, sc->ale_rev); 477 printf("%s: Chip id/revision : 0x%04x\n", 478 sc->sc_dev.dv_xname, sc->ale_chip_rev); 479 } 480 481 /* 482 * Uninitialized hardware returns an invalid chip id/revision 483 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 484 */ 485 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 486 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 487 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 488 rxf_len == 0xFFFFFFF) { 489 printf("%s: chip revision : 0x%04x, %u Tx FIFO " 490 "%u Rx FIFO -- not initialized?\n", sc->sc_dev.dv_xname, 491 sc->ale_chip_rev, txf_len, rxf_len); 492 goto fail; 493 } 494 495 if (aledebug) { 496 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, 497 txf_len, rxf_len); 498 } 499 500 /* Set max allowable DMA size. */ 501 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 502 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 503 504 error = ale_dma_alloc(sc); 505 if (error) 506 goto fail; 507 508 /* Load station address. */ 509 ale_get_macaddr(sc); 510 511 ifp = &sc->sc_arpcom.ac_if; 512 ifp->if_softc = sc; 513 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 514 ifp->if_init = ale_init; 515 ifp->if_ioctl = ale_ioctl; 516 ifp->if_start = ale_start; 517 ifp->if_watchdog = ale_watchdog; 518 ifp->if_baudrate = IF_Gbps(1); 519 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 520 IFQ_SET_READY(&ifp->if_snd); 521 bcopy(sc->ale_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 522 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 523 524 ifp->if_capabilities = IFCAP_VLAN_MTU; 525 526 #ifdef ALE_CHECKSUM 527 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 528 IFCAP_CSUM_UDPv4; 529 #endif 530 531 #if NVLAN > 0 532 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 533 #endif 534 535 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 536 537 /* Set up MII bus. */ 538 sc->sc_miibus.mii_ifp = ifp; 539 sc->sc_miibus.mii_readreg = ale_miibus_readreg; 540 sc->sc_miibus.mii_writereg = ale_miibus_writereg; 541 sc->sc_miibus.mii_statchg = ale_miibus_statchg; 542 543 ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, 544 ale_mediastatus); 545 mii_flags = 0; 546 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 547 mii_flags |= MIIF_DOPAUSE; 548 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 549 MII_OFFSET_ANY, mii_flags); 550 551 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 552 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 553 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 554 0, NULL); 555 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 556 } else 557 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 558 559 if_attach(ifp); 560 ether_ifattach(ifp); 561 562 timeout_set(&sc->ale_tick_ch, ale_tick, sc); 563 564 return; 565 fail: 566 ale_dma_free(sc); 567 if (sc->sc_irq_handle != NULL) 568 pci_intr_disestablish(pc, sc->sc_irq_handle); 569 if (sc->sc_mem_size) 570 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 571 } 572 573 int 574 ale_detach(struct device *self, int flags) 575 { 576 struct ale_softc *sc = (struct ale_softc *)self; 577 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 578 int s; 579 580 s = splnet(); 581 ale_stop(sc); 582 splx(s); 583 584 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 585 586 /* Delete all remaining media. */ 587 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 588 589 ether_ifdetach(ifp); 590 if_detach(ifp); 591 ale_dma_free(sc); 592 593 if (sc->sc_irq_handle != NULL) { 594 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 595 sc->sc_irq_handle = NULL; 596 } 597 598 return (0); 599 } 600 601 602 int 603 ale_dma_alloc(struct ale_softc *sc) 604 { 605 struct ale_txdesc *txd; 606 int nsegs, error, guard_size, i; 607 608 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 609 guard_size = ALE_JUMBO_FRAMELEN; 610 else 611 guard_size = ALE_MAX_FRAMELEN; 612 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 613 ALE_RX_PAGE_ALIGN); 614 615 /* 616 * Create DMA stuffs for TX ring 617 */ 618 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 619 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 620 if (error) 621 return (ENOBUFS); 622 623 /* Allocate DMA'able memory for TX ring */ 624 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 625 ETHER_ALIGN, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 626 &nsegs, BUS_DMA_WAITOK); 627 if (error) { 628 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 629 sc->sc_dev.dv_xname); 630 return error; 631 } 632 633 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 634 nsegs, ALE_TX_RING_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_ring, 635 BUS_DMA_NOWAIT); 636 if (error) 637 return (ENOBUFS); 638 639 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 640 641 /* Load the DMA map for Tx ring. */ 642 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 643 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 644 if (error) { 645 printf("%s: could not load DMA'able memory for Tx ring.\n", 646 sc->sc_dev.dv_xname); 647 bus_dmamem_free(sc->sc_dmat, 648 (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_ring, 1); 649 return error; 650 } 651 sc->ale_cdata.ale_tx_ring_paddr = 652 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 653 654 for (i = 0; i < ALE_RX_PAGES; i++) { 655 /* 656 * Create DMA stuffs for RX pages 657 */ 658 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 659 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 660 &sc->ale_cdata.ale_rx_page[i].page_map); 661 if (error) 662 return (ENOBUFS); 663 664 /* Allocate DMA'able memory for RX pages */ 665 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 666 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 667 1, &nsegs, BUS_DMA_WAITOK); 668 if (error) { 669 printf("%s: could not allocate DMA'able memory for " 670 "Rx ring.\n", sc->sc_dev.dv_xname); 671 return error; 672 } 673 error = bus_dmamem_map(sc->sc_dmat, 674 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 675 sc->ale_pagesize, 676 (caddr_t *)&sc->ale_cdata.ale_rx_page[i].page_addr, 677 BUS_DMA_NOWAIT); 678 if (error) 679 return (ENOBUFS); 680 681 bzero(sc->ale_cdata.ale_rx_page[i].page_addr, sc->ale_pagesize); 682 683 /* Load the DMA map for Rx pages. */ 684 error = bus_dmamap_load(sc->sc_dmat, 685 sc->ale_cdata.ale_rx_page[i].page_map, 686 sc->ale_cdata.ale_rx_page[i].page_addr, 687 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 688 if (error) { 689 printf("%s: could not load DMA'able memory for " 690 "Rx pages.\n", sc->sc_dev.dv_xname); 691 bus_dmamem_free(sc->sc_dmat, 692 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].page_addr, 1); 693 return error; 694 } 695 sc->ale_cdata.ale_rx_page[i].page_paddr = 696 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 697 } 698 699 /* 700 * Create DMA stuffs for Tx CMB. 701 */ 702 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 703 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 704 if (error) 705 return (ENOBUFS); 706 707 /* Allocate DMA'able memory for Tx CMB. */ 708 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 709 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, BUS_DMA_WAITOK); 710 711 if (error) { 712 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 713 sc->sc_dev.dv_xname); 714 return error; 715 } 716 717 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 718 nsegs, ALE_TX_CMB_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_cmb, 719 BUS_DMA_NOWAIT); 720 if (error) 721 return (ENOBUFS); 722 723 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 724 725 /* Load the DMA map for Tx CMB. */ 726 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 727 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 728 if (error) { 729 printf("%s: could not load DMA'able memory for Tx CMB.\n", 730 sc->sc_dev.dv_xname); 731 bus_dmamem_free(sc->sc_dmat, 732 (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_cmb, 1); 733 return error; 734 } 735 736 sc->ale_cdata.ale_tx_cmb_paddr = 737 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 738 739 for (i = 0; i < ALE_RX_PAGES; i++) { 740 /* 741 * Create DMA stuffs for Rx CMB. 742 */ 743 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 744 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 745 &sc->ale_cdata.ale_rx_page[i].cmb_map); 746 if (error) 747 return (ENOBUFS); 748 749 /* Allocate DMA'able memory for Rx CMB */ 750 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 751 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 752 &nsegs, BUS_DMA_WAITOK); 753 if (error) { 754 printf("%s: could not allocate DMA'able memory for " 755 "Rx CMB\n", sc->sc_dev.dv_xname); 756 return error; 757 } 758 error = bus_dmamem_map(sc->sc_dmat, 759 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 760 ALE_RX_CMB_SZ, 761 (caddr_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 762 BUS_DMA_NOWAIT); 763 if (error) 764 return (ENOBUFS); 765 766 bzero(sc->ale_cdata.ale_rx_page[i].cmb_addr, ALE_RX_CMB_SZ); 767 768 /* Load the DMA map for Rx CMB */ 769 error = bus_dmamap_load(sc->sc_dmat, 770 sc->ale_cdata.ale_rx_page[i].cmb_map, 771 sc->ale_cdata.ale_rx_page[i].cmb_addr, 772 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 773 if (error) { 774 printf("%s: could not load DMA'able memory for Rx CMB" 775 "\n", sc->sc_dev.dv_xname); 776 bus_dmamem_free(sc->sc_dmat, 777 (bus_dma_segment_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1); 778 return error; 779 } 780 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 781 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 782 } 783 784 785 /* Create DMA maps for Tx buffers. */ 786 for (i = 0; i < ALE_TX_RING_CNT; i++) { 787 txd = &sc->ale_cdata.ale_txdesc[i]; 788 txd->tx_m = NULL; 789 txd->tx_dmamap = NULL; 790 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 791 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 792 &txd->tx_dmamap); 793 if (error) { 794 printf("%s: could not create Tx dmamap.\n", 795 sc->sc_dev.dv_xname); 796 return error; 797 } 798 } 799 800 return (0); 801 } 802 803 void 804 ale_dma_free(struct ale_softc *sc) 805 { 806 struct ale_txdesc *txd; 807 int i; 808 809 /* Tx buffers. */ 810 for (i = 0; i < ALE_TX_RING_CNT; i++) { 811 txd = &sc->ale_cdata.ale_txdesc[i]; 812 if (txd->tx_dmamap != NULL) { 813 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 814 txd->tx_dmamap = NULL; 815 } 816 } 817 818 /* Tx descriptor ring. */ 819 if (sc->ale_cdata.ale_tx_ring_map != NULL) 820 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 821 if (sc->ale_cdata.ale_tx_ring_map != NULL && 822 sc->ale_cdata.ale_tx_ring != NULL) 823 bus_dmamem_free(sc->sc_dmat, 824 (bus_dma_segment_t *)sc->ale_cdata.ale_tx_ring, 1); 825 sc->ale_cdata.ale_tx_ring = NULL; 826 sc->ale_cdata.ale_tx_ring_map = NULL; 827 828 /* Rx page block. */ 829 for (i = 0; i < ALE_RX_PAGES; i++) { 830 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 831 bus_dmamap_unload(sc->sc_dmat, 832 sc->ale_cdata.ale_rx_page[i].page_map); 833 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 834 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 835 bus_dmamem_free(sc->sc_dmat, 836 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].page_addr, 1); 837 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 838 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 839 } 840 841 /* Rx CMB. */ 842 for (i = 0; i < ALE_RX_PAGES; i++) { 843 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 844 bus_dmamap_unload(sc->sc_dmat, 845 sc->ale_cdata.ale_rx_page[i].cmb_map); 846 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 847 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 848 bus_dmamem_free(sc->sc_dmat, 849 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].cmb_addr, 1); 850 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 851 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 852 } 853 854 /* Tx CMB. */ 855 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 856 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 857 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 858 sc->ale_cdata.ale_tx_cmb != NULL) 859 bus_dmamem_free(sc->sc_dmat, 860 (bus_dma_segment_t *)sc->ale_cdata.ale_tx_cmb, 1); 861 sc->ale_cdata.ale_tx_cmb = NULL; 862 sc->ale_cdata.ale_tx_cmb_map = NULL; 863 864 } 865 866 int 867 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 868 { 869 struct ale_txdesc *txd, *txd_last; 870 struct tx_desc *desc; 871 struct mbuf *m; 872 bus_dmamap_t map; 873 uint32_t cflags, poff, vtag; 874 int error, i, nsegs, prod; 875 876 m = *m_head; 877 cflags = vtag = 0; 878 poff = 0; 879 880 prod = sc->ale_cdata.ale_tx_prod; 881 txd = &sc->ale_cdata.ale_txdesc[prod]; 882 txd_last = txd; 883 map = txd->tx_dmamap; 884 885 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 886 887 if (error != 0) { 888 bus_dmamap_unload(sc->sc_dmat, map); 889 error = EFBIG; 890 } 891 if (error == EFBIG) { 892 if (m_defrag(*m_head, M_DONTWAIT)) { 893 printf("%s: can't defrag TX mbuf\n", 894 sc->sc_dev.dv_xname); 895 m_freem(*m_head); 896 *m_head = NULL; 897 return (ENOBUFS); 898 } 899 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 900 BUS_DMA_NOWAIT); 901 if (error != 0) { 902 printf("%s: could not load defragged TX mbuf\n", 903 sc->sc_dev.dv_xname); 904 m_freem(*m_head); 905 *m_head = NULL; 906 return (error); 907 } 908 } else if (error) { 909 printf("%s: could not load TX mbuf\n", sc->sc_dev.dv_xname); 910 return (error); 911 } 912 913 nsegs = map->dm_nsegs; 914 915 if (nsegs == 0) { 916 m_freem(*m_head); 917 *m_head = NULL; 918 return (EIO); 919 } 920 921 /* Check descriptor overrun. */ 922 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 923 bus_dmamap_unload(sc->sc_dmat, map); 924 return (ENOBUFS); 925 } 926 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 927 BUS_DMASYNC_PREWRITE); 928 929 m = *m_head; 930 /* Configure Tx checksum offload. */ 931 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 932 /* 933 * AR81xx supports Tx custom checksum offload feature 934 * that offloads single 16bit checksum computation. 935 * So you can choose one among IP, TCP and UDP. 936 * Normally driver sets checksum start/insertion 937 * position from the information of TCP/UDP frame as 938 * TCP/UDP checksum takes more time than that of IP. 939 * However it seems that custom checksum offload 940 * requires 4 bytes aligned Tx buffers due to hardware 941 * bug. 942 * AR81xx also supports explicit Tx checksum computation 943 * if it is told that the size of IP header and TCP 944 * header(for UDP, the header size does not matter 945 * because it's fixed length). However with this scheme 946 * TSO does not work so you have to choose one either 947 * TSO or explicit Tx checksum offload. I chosen TSO 948 * plus custom checksum offload with work-around which 949 * will cover most common usage for this consumer 950 * ethernet controller. The work-around takes a lot of 951 * CPU cycles if Tx buffer is not aligned on 4 bytes 952 * boundary, though. 953 */ 954 cflags |= ALE_TD_CXSUM; 955 /* Set checksum start offset. */ 956 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 957 } 958 959 #if NVLAN > 0 960 /* Configure VLAN hardware tag insertion. */ 961 if (m->m_flags & M_VLANTAG) { 962 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 963 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 964 cflags |= ALE_TD_INSERT_VLAN_TAG; 965 } 966 #endif 967 968 desc = NULL; 969 for (i = 0; i < nsegs; i++) { 970 desc = &sc->ale_cdata.ale_tx_ring[prod]; 971 desc->addr = htole64(map->dm_segs[i].ds_addr); 972 desc->len = 973 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 974 desc->flags = htole32(cflags); 975 sc->ale_cdata.ale_tx_cnt++; 976 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 977 } 978 /* Update producer index. */ 979 sc->ale_cdata.ale_tx_prod = prod; 980 981 /* Finally set EOP on the last descriptor. */ 982 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 983 desc = &sc->ale_cdata.ale_tx_ring[prod]; 984 desc->flags |= htole32(ALE_TD_EOP); 985 986 /* Swap dmamap of the first and the last. */ 987 txd = &sc->ale_cdata.ale_txdesc[prod]; 988 map = txd_last->tx_dmamap; 989 txd_last->tx_dmamap = txd->tx_dmamap; 990 txd->tx_dmamap = map; 991 txd->tx_m = m; 992 993 /* Sync descriptors. */ 994 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 995 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 996 997 return (0); 998 } 999 1000 void 1001 ale_start(struct ifnet *ifp) 1002 { 1003 struct ale_softc *sc = ifp->if_softc; 1004 struct mbuf *m_head; 1005 int enq; 1006 1007 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1008 return; 1009 1010 /* Reclaim transmitted frames. */ 1011 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1012 ale_txeof(sc); 1013 1014 enq = 0; 1015 for (;;) { 1016 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1017 if (m_head == NULL) 1018 break; 1019 1020 /* 1021 * Pack the data into the transmit ring. If we 1022 * don't have room, set the OACTIVE flag and wait 1023 * for the NIC to drain the ring. 1024 */ 1025 if (ale_encap(sc, &m_head)) { 1026 if (m_head == NULL) 1027 break; 1028 ifp->if_flags |= IFF_OACTIVE; 1029 break; 1030 } 1031 enq = 1; 1032 1033 #if NBPFILTER > 0 1034 /* 1035 * If there's a BPF listener, bounce a copy of this frame 1036 * to him. 1037 */ 1038 if (ifp->if_bpf != NULL) 1039 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1040 #endif 1041 } 1042 1043 if (enq) { 1044 /* Kick. */ 1045 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1046 sc->ale_cdata.ale_tx_prod); 1047 1048 /* Set a timeout in case the chip goes out to lunch. */ 1049 ifp->if_timer = ALE_TX_TIMEOUT; 1050 } 1051 } 1052 1053 void 1054 ale_watchdog(struct ifnet *ifp) 1055 { 1056 struct ale_softc *sc = ifp->if_softc; 1057 1058 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1059 printf("%s: watchdog timeout (missed link)\n", 1060 sc->sc_dev.dv_xname); 1061 ifp->if_oerrors++; 1062 ale_init(ifp); 1063 return; 1064 } 1065 1066 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1067 ifp->if_oerrors++; 1068 ale_init(ifp); 1069 1070 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1071 ale_start(ifp); 1072 } 1073 1074 int 1075 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1076 { 1077 struct ale_softc *sc = ifp->if_softc; 1078 struct mii_data *mii = &sc->sc_miibus; 1079 struct ifaddr *ifa = (struct ifaddr *)data; 1080 struct ifreq *ifr = (struct ifreq *)data; 1081 int s, error = 0; 1082 1083 s = splnet(); 1084 1085 switch (cmd) { 1086 case SIOCSIFADDR: 1087 ifp->if_flags |= IFF_UP; 1088 if (!(ifp->if_flags & IFF_RUNNING)) 1089 ale_init(ifp); 1090 #ifdef INET 1091 if (ifa->ifa_addr->sa_family == AF_INET) 1092 arp_ifinit(&sc->sc_arpcom, ifa); 1093 #endif 1094 break; 1095 1096 case SIOCSIFFLAGS: 1097 if (ifp->if_flags & IFF_UP) { 1098 if (ifp->if_flags & IFF_RUNNING) 1099 error = ENETRESET; 1100 else 1101 ale_init(ifp); 1102 } else { 1103 if (ifp->if_flags & IFF_RUNNING) 1104 ale_stop(sc); 1105 } 1106 break; 1107 1108 case SIOCSIFMEDIA: 1109 case SIOCGIFMEDIA: 1110 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1111 break; 1112 1113 default: 1114 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1115 break; 1116 } 1117 1118 if (error == ENETRESET) { 1119 if (ifp->if_flags & IFF_RUNNING) 1120 ale_rxfilter(sc); 1121 error = 0; 1122 } 1123 1124 splx(s); 1125 return (error); 1126 } 1127 1128 void 1129 ale_mac_config(struct ale_softc *sc) 1130 { 1131 struct mii_data *mii; 1132 uint32_t reg; 1133 1134 mii = &sc->sc_miibus; 1135 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1136 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1137 MAC_CFG_SPEED_MASK); 1138 /* Reprogram MAC with resolved speed/duplex. */ 1139 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1140 case IFM_10_T: 1141 case IFM_100_TX: 1142 reg |= MAC_CFG_SPEED_10_100; 1143 break; 1144 case IFM_1000_T: 1145 reg |= MAC_CFG_SPEED_1000; 1146 break; 1147 } 1148 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1149 reg |= MAC_CFG_FULL_DUPLEX; 1150 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1151 reg |= MAC_CFG_TX_FC; 1152 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1153 reg |= MAC_CFG_RX_FC; 1154 } 1155 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1156 } 1157 1158 void 1159 ale_stats_clear(struct ale_softc *sc) 1160 { 1161 struct smb sb; 1162 uint32_t *reg; 1163 int i; 1164 1165 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1166 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1167 i += sizeof(uint32_t); 1168 } 1169 /* Read Tx statistics. */ 1170 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1171 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1172 i += sizeof(uint32_t); 1173 } 1174 } 1175 1176 void 1177 ale_stats_update(struct ale_softc *sc) 1178 { 1179 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1180 struct ale_hw_stats *stat; 1181 struct smb sb, *smb; 1182 uint32_t *reg; 1183 int i; 1184 1185 stat = &sc->ale_stats; 1186 smb = &sb; 1187 1188 /* Read Rx statistics. */ 1189 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1190 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1191 i += sizeof(uint32_t); 1192 } 1193 /* Read Tx statistics. */ 1194 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1195 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1196 i += sizeof(uint32_t); 1197 } 1198 1199 /* Rx stats. */ 1200 stat->rx_frames += smb->rx_frames; 1201 stat->rx_bcast_frames += smb->rx_bcast_frames; 1202 stat->rx_mcast_frames += smb->rx_mcast_frames; 1203 stat->rx_pause_frames += smb->rx_pause_frames; 1204 stat->rx_control_frames += smb->rx_control_frames; 1205 stat->rx_crcerrs += smb->rx_crcerrs; 1206 stat->rx_lenerrs += smb->rx_lenerrs; 1207 stat->rx_bytes += smb->rx_bytes; 1208 stat->rx_runts += smb->rx_runts; 1209 stat->rx_fragments += smb->rx_fragments; 1210 stat->rx_pkts_64 += smb->rx_pkts_64; 1211 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1212 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1213 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1214 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1215 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1216 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1217 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1218 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1219 stat->rx_rrs_errs += smb->rx_rrs_errs; 1220 stat->rx_alignerrs += smb->rx_alignerrs; 1221 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1222 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1223 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1224 1225 /* Tx stats. */ 1226 stat->tx_frames += smb->tx_frames; 1227 stat->tx_bcast_frames += smb->tx_bcast_frames; 1228 stat->tx_mcast_frames += smb->tx_mcast_frames; 1229 stat->tx_pause_frames += smb->tx_pause_frames; 1230 stat->tx_excess_defer += smb->tx_excess_defer; 1231 stat->tx_control_frames += smb->tx_control_frames; 1232 stat->tx_deferred += smb->tx_deferred; 1233 stat->tx_bytes += smb->tx_bytes; 1234 stat->tx_pkts_64 += smb->tx_pkts_64; 1235 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1236 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1237 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1238 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1239 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1240 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1241 stat->tx_single_colls += smb->tx_single_colls; 1242 stat->tx_multi_colls += smb->tx_multi_colls; 1243 stat->tx_late_colls += smb->tx_late_colls; 1244 stat->tx_excess_colls += smb->tx_excess_colls; 1245 stat->tx_abort += smb->tx_abort; 1246 stat->tx_underrun += smb->tx_underrun; 1247 stat->tx_desc_underrun += smb->tx_desc_underrun; 1248 stat->tx_lenerrs += smb->tx_lenerrs; 1249 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1250 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1251 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1252 1253 /* Update counters in ifnet. */ 1254 ifp->if_opackets += smb->tx_frames; 1255 1256 ifp->if_collisions += smb->tx_single_colls + 1257 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1258 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1259 1260 /* 1261 * XXX 1262 * tx_pkts_truncated counter looks suspicious. It constantly 1263 * increments with no sign of Tx errors. This may indicate 1264 * the counter name is not correct one so I've removed the 1265 * counter in output errors. 1266 */ 1267 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1268 smb->tx_underrun; 1269 1270 ifp->if_ipackets += smb->rx_frames; 1271 1272 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1273 smb->rx_runts + smb->rx_pkts_truncated + 1274 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1275 smb->rx_alignerrs; 1276 } 1277 1278 int 1279 ale_intr(void *xsc) 1280 { 1281 struct ale_softc *sc = xsc; 1282 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1283 uint32_t status; 1284 1285 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1286 if ((status & ALE_INTRS) == 0) 1287 return (0); 1288 1289 /* Acknowledge and disable interrupts. */ 1290 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1291 1292 if (ifp->if_flags & IFF_RUNNING) { 1293 int error; 1294 1295 error = ale_rxeof(sc); 1296 if (error) { 1297 sc->ale_stats.reset_brk_seq++; 1298 ale_init(ifp); 1299 return (0); 1300 } 1301 1302 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1303 if (status & INTR_DMA_RD_TO_RST) 1304 printf("%s: DMA read error! -- resetting\n", 1305 sc->sc_dev.dv_xname); 1306 if (status & INTR_DMA_WR_TO_RST) 1307 printf("%s: DMA write error! -- resetting\n", 1308 sc->sc_dev.dv_xname); 1309 ale_init(ifp); 1310 return (0); 1311 } 1312 1313 ale_txeof(sc); 1314 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1315 ale_start(ifp); 1316 } 1317 1318 /* Re-enable interrupts. */ 1319 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1320 return (1); 1321 } 1322 1323 void 1324 ale_txeof(struct ale_softc *sc) 1325 { 1326 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1327 struct ale_txdesc *txd; 1328 uint32_t cons, prod; 1329 int prog; 1330 1331 if (sc->ale_cdata.ale_tx_cnt == 0) 1332 return; 1333 1334 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1335 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1336 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1337 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1338 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1339 BUS_DMASYNC_POSTREAD); 1340 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1341 } else 1342 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1343 cons = sc->ale_cdata.ale_tx_cons; 1344 /* 1345 * Go through our Tx list and free mbufs for those 1346 * frames which have been transmitted. 1347 */ 1348 for (prog = 0; cons != prod; prog++, 1349 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1350 if (sc->ale_cdata.ale_tx_cnt <= 0) 1351 break; 1352 prog++; 1353 ifp->if_flags &= ~IFF_OACTIVE; 1354 sc->ale_cdata.ale_tx_cnt--; 1355 txd = &sc->ale_cdata.ale_txdesc[cons]; 1356 if (txd->tx_m != NULL) { 1357 /* Reclaim transmitted mbufs. */ 1358 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1359 m_freem(txd->tx_m); 1360 txd->tx_m = NULL; 1361 } 1362 } 1363 1364 if (prog > 0) { 1365 sc->ale_cdata.ale_tx_cons = cons; 1366 /* 1367 * Unarm watchdog timer only when there is no pending 1368 * Tx descriptors in queue. 1369 */ 1370 if (sc->ale_cdata.ale_tx_cnt == 0) 1371 ifp->if_timer = 0; 1372 } 1373 } 1374 1375 void 1376 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1377 uint32_t length, uint32_t *prod) 1378 { 1379 struct ale_rx_page *rx_page; 1380 1381 rx_page = *page; 1382 /* Update consumer position. */ 1383 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1384 ALE_RX_PAGE_ALIGN); 1385 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1386 /* 1387 * End of Rx page reached, let hardware reuse 1388 * this page. 1389 */ 1390 rx_page->cons = 0; 1391 *rx_page->cmb_addr = 0; 1392 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1393 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1394 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1395 RXF_VALID); 1396 /* Switch to alternate Rx page. */ 1397 sc->ale_cdata.ale_rx_curp ^= 1; 1398 rx_page = *page = 1399 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1400 /* Page flipped, sync CMB and Rx page. */ 1401 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1402 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1403 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1404 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1405 /* Sync completed, cache updated producer index. */ 1406 *prod = *rx_page->cmb_addr; 1407 } 1408 } 1409 1410 1411 /* 1412 * It seems that AR81xx controller can compute partial checksum. 1413 * The partial checksum value can be used to accelerate checksum 1414 * computation for fragmented TCP/UDP packets. Upper network stack 1415 * already takes advantage of the partial checksum value in IP 1416 * reassembly stage. But I'm not sure the correctness of the 1417 * partial hardware checksum assistance due to lack of data sheet. 1418 * In addition, the Rx feature of controller that requires copying 1419 * for every frames effectively nullifies one of most nice offload 1420 * capability of controller. 1421 */ 1422 void 1423 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1424 { 1425 struct ip *ip; 1426 char *p; 1427 1428 if ((status & ALE_RD_IPCSUM_NOK) == 0) 1429 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1430 1431 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1432 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1433 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1434 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 1435 m->m_pkthdr.csum_flags |= 1436 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1437 } 1438 } else { 1439 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 1440 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 1441 p = mtod(m, char *); 1442 p += ETHER_HDR_LEN; 1443 if ((status & ALE_RD_802_3) != 0) 1444 p += LLC_SNAPFRAMELEN; 1445 #if NVLAN > 0 1446 if (status & ALE_RD_VLAN) 1447 p += EVL_ENCAPLEN; 1448 #endif 1449 ip = (struct ip *)p; 1450 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 1451 return; 1452 m->m_pkthdr.csum_flags |= 1453 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1454 } 1455 } 1456 /* 1457 * Don't mark bad checksum for TCP/UDP frames 1458 * as fragmented frames may always have set 1459 * bad checksummed bit of frame status. 1460 */ 1461 } 1462 1463 /* Process received frames. */ 1464 int 1465 ale_rxeof(struct ale_softc *sc) 1466 { 1467 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1468 struct ale_rx_page *rx_page; 1469 struct rx_rs *rs; 1470 struct mbuf *m; 1471 uint32_t length, prod, seqno, status; 1472 int prog; 1473 1474 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1475 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1476 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1477 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1478 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1479 /* 1480 * Don't directly access producer index as hardware may 1481 * update it while Rx handler is in progress. It would 1482 * be even better if there is a way to let hardware 1483 * know how far driver processed its received frames. 1484 * Alternatively, hardware could provide a way to disable 1485 * CMB updates until driver acknowledges the end of CMB 1486 * access. 1487 */ 1488 prod = *rx_page->cmb_addr; 1489 for (prog = 0; ; prog++) { 1490 if (rx_page->cons >= prod) 1491 break; 1492 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1493 seqno = ALE_RX_SEQNO(letoh32(rs->seqno)); 1494 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1495 /* 1496 * Normally I believe this should not happen unless 1497 * severe driver bug or corrupted memory. However 1498 * it seems to happen under certain conditions which 1499 * is triggered by abrupt Rx events such as initiation 1500 * of bulk transfer of remote host. It's not easy to 1501 * reproduce this and I doubt it could be related 1502 * with FIFO overflow of hardware or activity of Tx 1503 * CMB updates. I also remember similar behaviour 1504 * seen on RealTek 8139 which uses resembling Rx 1505 * scheme. 1506 */ 1507 if (aledebug) 1508 printf("%s: garbled seq: %u, expected: %u -- " 1509 "resetting!\n", sc->sc_dev.dv_xname, 1510 seqno, sc->ale_cdata.ale_rx_seqno); 1511 return (EIO); 1512 } 1513 /* Frame received. */ 1514 sc->ale_cdata.ale_rx_seqno++; 1515 length = ALE_RX_BYTES(letoh32(rs->length)); 1516 status = letoh32(rs->flags); 1517 if (status & ALE_RD_ERROR) { 1518 /* 1519 * We want to pass the following frames to upper 1520 * layer regardless of error status of Rx return 1521 * status. 1522 * 1523 * o IP/TCP/UDP checksum is bad. 1524 * o frame length and protocol specific length 1525 * does not match. 1526 */ 1527 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1528 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1529 ALE_RD_TRUNC)) { 1530 ale_rx_update_page(sc, &rx_page, length, &prod); 1531 continue; 1532 } 1533 } 1534 /* 1535 * m_devget(9) is major bottle-neck of ale(4)(It comes 1536 * from hardware limitation). For jumbo frames we could 1537 * get a slightly better performance if driver use 1538 * m_getjcl(9) with proper buffer size argument. However 1539 * that would make code more complicated and I don't 1540 * think users would expect good Rx performance numbers 1541 * on these low-end consumer ethernet controller. 1542 */ 1543 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1544 ETHER_ALIGN, ifp, NULL); 1545 if (m == NULL) { 1546 ifp->if_iqdrops++; 1547 ale_rx_update_page(sc, &rx_page, length, &prod); 1548 continue; 1549 } 1550 if (status & ALE_RD_IPV4) 1551 ale_rxcsum(sc, m, status); 1552 #if NVLAN > 0 1553 if (status & ALE_RD_VLAN) { 1554 uint32_t vtags = ALE_RX_VLAN(letoh32(rs->vtags)); 1555 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 1556 m->m_flags |= M_VLANTAG; 1557 } 1558 #endif 1559 1560 1561 #if NBPFILTER > 0 1562 if (ifp->if_bpf) 1563 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1564 #endif 1565 1566 /* Pass it to upper layer. */ 1567 ether_input_mbuf(ifp, m); 1568 1569 ale_rx_update_page(sc, &rx_page, length, &prod); 1570 } 1571 1572 return 0; 1573 } 1574 1575 void 1576 ale_tick(void *xsc) 1577 { 1578 struct ale_softc *sc = xsc; 1579 struct mii_data *mii = &sc->sc_miibus; 1580 int s; 1581 1582 s = splnet(); 1583 mii_tick(mii); 1584 ale_stats_update(sc); 1585 1586 timeout_add_sec(&sc->ale_tick_ch, 1); 1587 splx(s); 1588 } 1589 1590 void 1591 ale_reset(struct ale_softc *sc) 1592 { 1593 uint32_t reg; 1594 int i; 1595 1596 /* Initialize PCIe module. From Linux. */ 1597 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1598 1599 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1600 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1601 DELAY(10); 1602 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1603 break; 1604 } 1605 if (i == 0) 1606 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); 1607 1608 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1609 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1610 break; 1611 DELAY(10); 1612 } 1613 1614 if (i == 0) 1615 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 1616 reg); 1617 } 1618 1619 int 1620 ale_init(struct ifnet *ifp) 1621 { 1622 struct ale_softc *sc = ifp->if_softc; 1623 struct mii_data *mii; 1624 uint8_t eaddr[ETHER_ADDR_LEN]; 1625 bus_addr_t paddr; 1626 uint32_t reg, rxf_hi, rxf_lo; 1627 1628 /* 1629 * Cancel any pending I/O. 1630 */ 1631 ale_stop(sc); 1632 1633 /* 1634 * Reset the chip to a known state. 1635 */ 1636 ale_reset(sc); 1637 1638 /* Initialize Tx descriptors, DMA memory blocks. */ 1639 ale_init_rx_pages(sc); 1640 ale_init_tx_ring(sc); 1641 1642 /* Reprogram the station address. */ 1643 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 1644 CSR_WRITE_4(sc, ALE_PAR0, 1645 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1646 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1647 1648 /* 1649 * Clear WOL status and disable all WOL feature as WOL 1650 * would interfere Rx operation under normal environments. 1651 */ 1652 CSR_READ_4(sc, ALE_WOL_CFG); 1653 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1654 1655 /* 1656 * Set Tx descriptor/RXF0/CMB base addresses. They share 1657 * the same high address part of DMAable region. 1658 */ 1659 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1660 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1661 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1662 CSR_WRITE_4(sc, ALE_TPD_CNT, 1663 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1664 1665 /* Set Rx page base address, note we use single queue. */ 1666 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1667 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1668 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1669 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1670 1671 /* Set Tx/Rx CMB addresses. */ 1672 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1673 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1674 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1675 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1676 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1677 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1678 1679 /* Mark RXF0 is valid. */ 1680 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1681 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1682 /* 1683 * No need to initialize RFX1/RXF2/RXF3. We don't use 1684 * multi-queue yet. 1685 */ 1686 1687 /* Set Rx page size, excluding guard frame size. */ 1688 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1689 1690 /* Tell hardware that we're ready to load DMA blocks. */ 1691 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1692 1693 /* Set Rx/Tx interrupt trigger threshold. */ 1694 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1695 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1696 /* 1697 * XXX 1698 * Set interrupt trigger timer, its purpose and relation 1699 * with interrupt moderation mechanism is not clear yet. 1700 */ 1701 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1702 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1703 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1704 1705 /* Configure interrupt moderation timer. */ 1706 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1707 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1708 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1709 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1710 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1711 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1712 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1713 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1714 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1715 reg |= MASTER_IM_RX_TIMER_ENB; 1716 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1717 reg |= MASTER_IM_TX_TIMER_ENB; 1718 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1719 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1720 1721 /* Set Maximum frame size of controller. */ 1722 if (ifp->if_mtu < ETHERMTU) 1723 sc->ale_max_frame_size = ETHERMTU; 1724 else 1725 sc->ale_max_frame_size = ifp->if_mtu; 1726 sc->ale_max_frame_size += ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN; 1727 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1728 1729 /* Configure IPG/IFG parameters. */ 1730 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1731 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1732 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1733 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1734 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1735 1736 /* Set parameters for half-duplex media. */ 1737 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1738 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1739 HDPX_CFG_LCOL_MASK) | 1740 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1741 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1742 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1743 HDPX_CFG_ABEBT_MASK) | 1744 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1745 HDPX_CFG_JAMIPG_MASK)); 1746 1747 /* Configure Tx jumbo frame parameters. */ 1748 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1749 if (ifp->if_mtu < ETHERMTU) 1750 reg = sc->ale_max_frame_size; 1751 else if (ifp->if_mtu < 6 * 1024) 1752 reg = (sc->ale_max_frame_size * 2) / 3; 1753 else 1754 reg = sc->ale_max_frame_size / 2; 1755 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1756 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1757 TX_JUMBO_THRESH_UNIT_SHIFT); 1758 } 1759 1760 /* Configure TxQ. */ 1761 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1762 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1763 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1764 TXQ_CFG_TPD_BURST_MASK; 1765 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1766 1767 /* Configure Rx jumbo frame & flow control parameters. */ 1768 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1769 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1770 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1771 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1772 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1773 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1774 RX_JUMBO_LKAH_MASK)); 1775 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1776 rxf_hi = (reg * 7) / 10; 1777 rxf_lo = (reg * 3)/ 10; 1778 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1779 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1780 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1781 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1782 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1783 } 1784 1785 /* Disable RSS. */ 1786 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1787 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1788 1789 /* Configure RxQ. */ 1790 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1791 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1792 1793 /* Configure DMA parameters. */ 1794 reg = 0; 1795 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1796 reg |= DMA_CFG_TXCMB_ENB; 1797 CSR_WRITE_4(sc, ALE_DMA_CFG, 1798 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1799 sc->ale_dma_rd_burst | reg | 1800 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1801 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1802 DMA_CFG_RD_DELAY_CNT_MASK) | 1803 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1804 DMA_CFG_WR_DELAY_CNT_MASK)); 1805 1806 /* 1807 * Hardware can be configured to issue SMB interrupt based 1808 * on programmed interval. Since there is a callout that is 1809 * invoked for every hz in driver we use that instead of 1810 * relying on periodic SMB interrupt. 1811 */ 1812 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1813 1814 /* Clear MAC statistics. */ 1815 ale_stats_clear(sc); 1816 1817 /* 1818 * Configure Tx/Rx MACs. 1819 * - Auto-padding for short frames. 1820 * - Enable CRC generation. 1821 * Actual reconfiguration of MAC for resolved speed/duplex 1822 * is followed after detection of link establishment. 1823 * AR81xx always does checksum computation regardless of 1824 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1825 * cause Rx handling issue for fragmented IP datagrams due 1826 * to silicon bug. 1827 */ 1828 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1829 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1830 MAC_CFG_PREAMBLE_MASK); 1831 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1832 reg |= MAC_CFG_SPEED_10_100; 1833 else 1834 reg |= MAC_CFG_SPEED_1000; 1835 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1836 1837 /* Set up the receive filter. */ 1838 ale_rxfilter(sc); 1839 ale_rxvlan(sc); 1840 1841 /* Acknowledge all pending interrupts and clear it. */ 1842 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1843 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1844 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1845 1846 sc->ale_flags &= ~ALE_FLAG_LINK; 1847 1848 /* Switch to the current media. */ 1849 mii = &sc->sc_miibus; 1850 mii_mediachg(mii); 1851 1852 timeout_add_sec(&sc->ale_tick_ch, 1); 1853 1854 ifp->if_flags |= IFF_RUNNING; 1855 ifp->if_flags &= ~IFF_OACTIVE; 1856 1857 return 0; 1858 } 1859 1860 void 1861 ale_stop(struct ale_softc *sc) 1862 { 1863 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1864 struct ale_txdesc *txd; 1865 uint32_t reg; 1866 int i; 1867 1868 /* 1869 * Mark the interface down and cancel the watchdog timer. 1870 */ 1871 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1872 ifp->if_timer = 0; 1873 1874 timeout_del(&sc->ale_tick_ch); 1875 sc->ale_flags &= ~ALE_FLAG_LINK; 1876 1877 ale_stats_update(sc); 1878 1879 /* Disable interrupts. */ 1880 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1881 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1882 1883 /* Disable queue processing and DMA. */ 1884 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1885 reg &= ~TXQ_CFG_ENB; 1886 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1887 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1888 reg &= ~RXQ_CFG_ENB; 1889 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1890 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1891 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1892 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1893 DELAY(1000); 1894 1895 /* Stop Rx/Tx MACs. */ 1896 ale_stop_mac(sc); 1897 1898 /* Disable interrupts again? XXX */ 1899 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1900 1901 /* 1902 * Free TX mbufs still in the queues. 1903 */ 1904 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1905 txd = &sc->ale_cdata.ale_txdesc[i]; 1906 if (txd->tx_m != NULL) { 1907 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1908 m_freem(txd->tx_m); 1909 txd->tx_m = NULL; 1910 } 1911 } 1912 } 1913 1914 void 1915 ale_stop_mac(struct ale_softc *sc) 1916 { 1917 uint32_t reg; 1918 int i; 1919 1920 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1921 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1922 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1923 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1924 } 1925 1926 for (i = ALE_TIMEOUT; i > 0; i--) { 1927 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1928 if (reg == 0) 1929 break; 1930 DELAY(10); 1931 } 1932 if (i == 0) 1933 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1934 sc->sc_dev.dv_xname, reg); 1935 } 1936 1937 void 1938 ale_init_tx_ring(struct ale_softc *sc) 1939 { 1940 struct ale_txdesc *txd; 1941 int i; 1942 1943 sc->ale_cdata.ale_tx_prod = 0; 1944 sc->ale_cdata.ale_tx_cons = 0; 1945 sc->ale_cdata.ale_tx_cnt = 0; 1946 1947 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 1948 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 1949 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1950 txd = &sc->ale_cdata.ale_txdesc[i]; 1951 txd->tx_m = NULL; 1952 } 1953 *sc->ale_cdata.ale_tx_cmb = 0; 1954 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1955 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1956 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1957 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1958 } 1959 1960 void 1961 ale_init_rx_pages(struct ale_softc *sc) 1962 { 1963 struct ale_rx_page *rx_page; 1964 int i; 1965 1966 sc->ale_cdata.ale_rx_seqno = 0; 1967 sc->ale_cdata.ale_rx_curp = 0; 1968 1969 for (i = 0; i < ALE_RX_PAGES; i++) { 1970 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1971 bzero(rx_page->page_addr, sc->ale_pagesize); 1972 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 1973 rx_page->cons = 0; 1974 *rx_page->cmb_addr = 0; 1975 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1976 rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1977 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1978 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1979 } 1980 } 1981 1982 void 1983 ale_rxvlan(struct ale_softc *sc) 1984 { 1985 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1986 uint32_t reg; 1987 1988 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1989 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 1990 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1991 reg |= MAC_CFG_VLAN_TAG_STRIP; 1992 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1993 } 1994 1995 void 1996 ale_rxfilter(struct ale_softc *sc) 1997 { 1998 struct arpcom *ac = &sc->sc_arpcom; 1999 struct ifnet *ifp = &ac->ac_if; 2000 struct ether_multi *enm; 2001 struct ether_multistep step; 2002 uint32_t crc; 2003 uint32_t mchash[2]; 2004 uint32_t rxcfg; 2005 2006 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 2007 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2008 ifp->if_flags &= ~IFF_ALLMULTI; 2009 2010 /* 2011 * Always accept broadcast frames. 2012 */ 2013 rxcfg |= MAC_CFG_BCAST; 2014 2015 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 2016 ifp->if_flags |= IFF_ALLMULTI; 2017 if (ifp->if_flags & IFF_PROMISC) 2018 rxcfg |= MAC_CFG_PROMISC; 2019 else 2020 rxcfg |= MAC_CFG_ALLMULTI; 2021 mchash[0] = mchash[1] = 0xFFFFFFFF; 2022 } else { 2023 /* Program new filter. */ 2024 bzero(mchash, sizeof(mchash)); 2025 2026 ETHER_FIRST_MULTI(step, ac, enm); 2027 while (enm != NULL) { 2028 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2029 2030 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2031 2032 ETHER_NEXT_MULTI(step, enm); 2033 } 2034 } 2035 2036 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2037 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2038 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2039 } 2040