1 /* $OpenBSD: if_ale.c,v 1.25 2012/11/29 21:10:32 brad Exp $ */ 2 /*- 3 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 29 */ 30 31 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 32 33 #include "bpfilter.h" 34 #include "vlan.h" 35 36 #include <sys/param.h> 37 #include <sys/endian.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/queue.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/timeout.h> 46 #include <sys/socket.h> 47 48 #include <machine/bus.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_llc.h> 53 #include <net/if_media.h> 54 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/in_var.h> 59 #include <netinet/ip.h> 60 #include <netinet/if_ether.h> 61 #endif 62 63 #include <net/if_types.h> 64 #include <net/if_vlan_var.h> 65 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #endif 69 70 #include <dev/rndvar.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/if_alereg.h> 80 81 int ale_match(struct device *, void *, void *); 82 void ale_attach(struct device *, struct device *, void *); 83 int ale_detach(struct device *, int); 84 int ale_activate(struct device *, int); 85 86 int ale_miibus_readreg(struct device *, int, int); 87 void ale_miibus_writereg(struct device *, int, int, int); 88 void ale_miibus_statchg(struct device *); 89 90 int ale_init(struct ifnet *); 91 void ale_start(struct ifnet *); 92 int ale_ioctl(struct ifnet *, u_long, caddr_t); 93 void ale_watchdog(struct ifnet *); 94 int ale_mediachange(struct ifnet *); 95 void ale_mediastatus(struct ifnet *, struct ifmediareq *); 96 97 int ale_intr(void *); 98 int ale_rxeof(struct ale_softc *sc); 99 void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 100 uint32_t, uint32_t *); 101 void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 102 void ale_txeof(struct ale_softc *); 103 104 int ale_dma_alloc(struct ale_softc *); 105 void ale_dma_free(struct ale_softc *); 106 int ale_encap(struct ale_softc *, struct mbuf **); 107 void ale_init_rx_pages(struct ale_softc *); 108 void ale_init_tx_ring(struct ale_softc *); 109 110 void ale_stop(struct ale_softc *); 111 void ale_tick(void *); 112 void ale_get_macaddr(struct ale_softc *); 113 void ale_mac_config(struct ale_softc *); 114 void ale_phy_reset(struct ale_softc *); 115 void ale_reset(struct ale_softc *); 116 void ale_iff(struct ale_softc *); 117 void ale_rxvlan(struct ale_softc *); 118 void ale_stats_clear(struct ale_softc *); 119 void ale_stats_update(struct ale_softc *); 120 void ale_stop_mac(struct ale_softc *); 121 122 const struct pci_matchid ale_devices[] = { 123 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1E } 124 }; 125 126 struct cfattach ale_ca = { 127 sizeof (struct ale_softc), ale_match, ale_attach, NULL, 128 ale_activate 129 }; 130 131 struct cfdriver ale_cd = { 132 NULL, "ale", DV_IFNET 133 }; 134 135 int aledebug = 0; 136 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 137 138 #define ALE_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) 139 140 int 141 ale_miibus_readreg(struct device *dev, int phy, int reg) 142 { 143 struct ale_softc *sc = (struct ale_softc *)dev; 144 uint32_t v; 145 int i; 146 147 if (phy != sc->ale_phyaddr) 148 return (0); 149 150 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0 && 151 reg == MII_EXTSR) 152 return (0); 153 154 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 155 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 156 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 157 DELAY(5); 158 v = CSR_READ_4(sc, ALE_MDIO); 159 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 160 break; 161 } 162 163 if (i == 0) { 164 printf("%s: phy read timeout: phy %d, reg %d\n", 165 sc->sc_dev.dv_xname, phy, reg); 166 return (0); 167 } 168 169 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 170 } 171 172 void 173 ale_miibus_writereg(struct device *dev, int phy, int reg, int val) 174 { 175 struct ale_softc *sc = (struct ale_softc *)dev; 176 uint32_t v; 177 int i; 178 179 if (phy != sc->ale_phyaddr) 180 return; 181 182 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 183 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 184 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 185 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 186 DELAY(5); 187 v = CSR_READ_4(sc, ALE_MDIO); 188 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 189 break; 190 } 191 192 if (i == 0) 193 printf("%s: phy write timeout: phy %d, reg %d\n", 194 sc->sc_dev.dv_xname, phy, reg); 195 } 196 197 void 198 ale_miibus_statchg(struct device *dev) 199 { 200 struct ale_softc *sc = (struct ale_softc *)dev; 201 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 202 struct mii_data *mii = &sc->sc_miibus; 203 uint32_t reg; 204 205 if ((ifp->if_flags & IFF_RUNNING) == 0) 206 return; 207 208 sc->ale_flags &= ~ALE_FLAG_LINK; 209 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 210 (IFM_ACTIVE | IFM_AVALID)) { 211 switch (IFM_SUBTYPE(mii->mii_media_active)) { 212 case IFM_10_T: 213 case IFM_100_TX: 214 sc->ale_flags |= ALE_FLAG_LINK; 215 break; 216 217 case IFM_1000_T: 218 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 219 sc->ale_flags |= ALE_FLAG_LINK; 220 break; 221 222 default: 223 break; 224 } 225 } 226 227 /* Stop Rx/Tx MACs. */ 228 ale_stop_mac(sc); 229 230 /* Program MACs with resolved speed/duplex/flow-control. */ 231 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 232 ale_mac_config(sc); 233 /* Reenable Tx/Rx MACs. */ 234 reg = CSR_READ_4(sc, ALE_MAC_CFG); 235 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 236 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 237 } 238 } 239 240 void 241 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 242 { 243 struct ale_softc *sc = ifp->if_softc; 244 struct mii_data *mii = &sc->sc_miibus; 245 246 if ((ifp->if_flags & IFF_UP) == 0) 247 return; 248 249 mii_pollstat(mii); 250 ifmr->ifm_status = mii->mii_media_status; 251 ifmr->ifm_active = mii->mii_media_active; 252 } 253 254 int 255 ale_mediachange(struct ifnet *ifp) 256 { 257 struct ale_softc *sc = ifp->if_softc; 258 struct mii_data *mii = &sc->sc_miibus; 259 int error; 260 261 if (mii->mii_instance != 0) { 262 struct mii_softc *miisc; 263 264 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 265 mii_phy_reset(miisc); 266 } 267 error = mii_mediachg(mii); 268 269 return (error); 270 } 271 272 int 273 ale_match(struct device *dev, void *match, void *aux) 274 { 275 return pci_matchbyid((struct pci_attach_args *)aux, ale_devices, 276 sizeof (ale_devices) / sizeof (ale_devices[0])); 277 } 278 279 void 280 ale_get_macaddr(struct ale_softc *sc) 281 { 282 uint32_t ea[2], reg; 283 int i, vpdc; 284 285 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 286 if ((reg & SPI_VPD_ENB) != 0) { 287 reg &= ~SPI_VPD_ENB; 288 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 289 } 290 291 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 292 &vpdc, NULL)) { 293 /* 294 * PCI VPD capability found, let TWSI reload EEPROM. 295 * This will set ethernet address of controller. 296 */ 297 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 298 TWSI_CTRL_SW_LD_START); 299 for (i = 100; i > 0; i--) { 300 DELAY(1000); 301 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 302 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 303 break; 304 } 305 if (i == 0) 306 printf("%s: reloading EEPROM timeout!\n", 307 sc->sc_dev.dv_xname); 308 } else { 309 if (aledebug) 310 printf("%s: PCI VPD capability not found!\n", 311 sc->sc_dev.dv_xname); 312 } 313 314 ea[0] = CSR_READ_4(sc, ALE_PAR0); 315 ea[1] = CSR_READ_4(sc, ALE_PAR1); 316 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 317 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 318 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 319 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 320 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 321 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 322 } 323 324 void 325 ale_phy_reset(struct ale_softc *sc) 326 { 327 /* Reset magic from Linux. */ 328 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 329 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 330 GPHY_CTRL_PHY_PLL_ON); 331 DELAY(1000); 332 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 333 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 334 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 335 DELAY(1000); 336 337 #define ATPHY_DBG_ADDR 0x1D 338 #define ATPHY_DBG_DATA 0x1E 339 340 /* Enable hibernation mode. */ 341 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 342 ATPHY_DBG_ADDR, 0x0B); 343 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 344 ATPHY_DBG_DATA, 0xBC00); 345 /* Set Class A/B for all modes. */ 346 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 347 ATPHY_DBG_ADDR, 0x00); 348 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 349 ATPHY_DBG_DATA, 0x02EF); 350 /* Enable 10BT power saving. */ 351 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 352 ATPHY_DBG_ADDR, 0x12); 353 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 354 ATPHY_DBG_DATA, 0x4C04); 355 /* Adjust 1000T power. */ 356 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 357 ATPHY_DBG_ADDR, 0x04); 358 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 359 ATPHY_DBG_ADDR, 0x8BBB); 360 /* 10BT center tap voltage. */ 361 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 362 ATPHY_DBG_ADDR, 0x05); 363 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 364 ATPHY_DBG_ADDR, 0x2C46); 365 366 #undef ATPHY_DBG_ADDR 367 #undef ATPHY_DBG_DATA 368 DELAY(1000); 369 } 370 371 void 372 ale_attach(struct device *parent, struct device *self, void *aux) 373 { 374 struct ale_softc *sc = (struct ale_softc *)self; 375 struct pci_attach_args *pa = aux; 376 pci_chipset_tag_t pc = pa->pa_pc; 377 pci_intr_handle_t ih; 378 const char *intrstr; 379 struct ifnet *ifp; 380 pcireg_t memtype; 381 int mii_flags, error = 0; 382 uint32_t rxf_len, txf_len; 383 const char *chipname; 384 385 /* 386 * Allocate IO memory 387 */ 388 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALE_PCIR_BAR); 389 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 390 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 391 printf(": can't map mem space\n"); 392 return; 393 } 394 395 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 396 printf(": can't map interrupt\n"); 397 goto fail; 398 } 399 400 /* 401 * Allocate IRQ 402 */ 403 intrstr = pci_intr_string(pc, ih); 404 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc, 405 sc->sc_dev.dv_xname); 406 if (sc->sc_irq_handle == NULL) { 407 printf(": could not establish interrupt"); 408 if (intrstr != NULL) 409 printf(" at %s", intrstr); 410 printf("\n"); 411 goto fail; 412 } 413 414 sc->sc_dmat = pa->pa_dmat; 415 sc->sc_pct = pa->pa_pc; 416 sc->sc_pcitag = pa->pa_tag; 417 418 /* Set PHY address. */ 419 sc->ale_phyaddr = ALE_PHY_ADDR; 420 421 /* Reset PHY. */ 422 ale_phy_reset(sc); 423 424 /* Reset the ethernet controller. */ 425 ale_reset(sc); 426 427 /* Get PCI and chip id/revision. */ 428 sc->ale_rev = PCI_REVISION(pa->pa_class); 429 if (sc->ale_rev >= 0xF0) { 430 /* L2E Rev. B. AR8114 */ 431 sc->ale_flags |= ALE_FLAG_FASTETHER; 432 chipname = "AR8114"; 433 } else { 434 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 435 /* L1E AR8121 */ 436 sc->ale_flags |= ALE_FLAG_JUMBO; 437 chipname = "AR8121"; 438 } else { 439 /* L2E Rev. A. AR8113 */ 440 sc->ale_flags |= ALE_FLAG_FASTETHER; 441 chipname = "AR8113"; 442 } 443 } 444 445 printf(": %s, %s", chipname, intrstr); 446 447 /* 448 * All known controllers seems to require 4 bytes alignment 449 * of Tx buffers to make Tx checksum offload with custom 450 * checksum generation method work. 451 */ 452 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 453 454 /* 455 * All known controllers seems to have issues on Rx checksum 456 * offload for fragmented IP datagrams. 457 */ 458 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 459 460 /* 461 * Don't use Tx CMB. It is known to cause RRS update failure 462 * under certain circumstances. Typical phenomenon of the 463 * issue would be unexpected sequence number encountered in 464 * Rx handler. 465 */ 466 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 467 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 468 MASTER_CHIP_REV_SHIFT; 469 if (aledebug) { 470 printf("%s: PCI device revision : 0x%04x\n", 471 sc->sc_dev.dv_xname, sc->ale_rev); 472 printf("%s: Chip id/revision : 0x%04x\n", 473 sc->sc_dev.dv_xname, sc->ale_chip_rev); 474 } 475 476 /* 477 * Uninitialized hardware returns an invalid chip id/revision 478 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 479 */ 480 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 481 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 482 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 483 rxf_len == 0xFFFFFFF) { 484 printf("%s: chip revision : 0x%04x, %u Tx FIFO " 485 "%u Rx FIFO -- not initialized?\n", sc->sc_dev.dv_xname, 486 sc->ale_chip_rev, txf_len, rxf_len); 487 goto fail; 488 } 489 490 if (aledebug) { 491 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, 492 txf_len, rxf_len); 493 } 494 495 /* Set max allowable DMA size. */ 496 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 497 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 498 499 error = ale_dma_alloc(sc); 500 if (error) 501 goto fail; 502 503 /* Load station address. */ 504 ale_get_macaddr(sc); 505 506 ifp = &sc->sc_arpcom.ac_if; 507 ifp->if_softc = sc; 508 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 509 ifp->if_ioctl = ale_ioctl; 510 ifp->if_start = ale_start; 511 ifp->if_watchdog = ale_watchdog; 512 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 513 IFQ_SET_READY(&ifp->if_snd); 514 bcopy(sc->ale_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 515 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 516 517 ifp->if_capabilities = IFCAP_VLAN_MTU; 518 519 #ifdef ALE_CHECKSUM 520 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 521 IFCAP_CSUM_UDPv4; 522 #endif 523 524 #if NVLAN > 0 525 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 526 #endif 527 528 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 529 530 /* Set up MII bus. */ 531 sc->sc_miibus.mii_ifp = ifp; 532 sc->sc_miibus.mii_readreg = ale_miibus_readreg; 533 sc->sc_miibus.mii_writereg = ale_miibus_writereg; 534 sc->sc_miibus.mii_statchg = ale_miibus_statchg; 535 536 ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, 537 ale_mediastatus); 538 mii_flags = 0; 539 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 540 mii_flags |= MIIF_DOPAUSE; 541 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 542 MII_OFFSET_ANY, mii_flags); 543 544 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 545 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 546 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 547 0, NULL); 548 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 549 } else 550 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 551 552 if_attach(ifp); 553 ether_ifattach(ifp); 554 555 timeout_set(&sc->ale_tick_ch, ale_tick, sc); 556 557 return; 558 fail: 559 ale_dma_free(sc); 560 if (sc->sc_irq_handle != NULL) 561 pci_intr_disestablish(pc, sc->sc_irq_handle); 562 if (sc->sc_mem_size) 563 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 564 } 565 566 int 567 ale_detach(struct device *self, int flags) 568 { 569 struct ale_softc *sc = (struct ale_softc *)self; 570 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 571 int s; 572 573 s = splnet(); 574 ale_stop(sc); 575 splx(s); 576 577 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 578 579 /* Delete all remaining media. */ 580 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 581 582 ether_ifdetach(ifp); 583 if_detach(ifp); 584 ale_dma_free(sc); 585 586 if (sc->sc_irq_handle != NULL) { 587 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 588 sc->sc_irq_handle = NULL; 589 } 590 591 return (0); 592 } 593 594 int 595 ale_activate(struct device *self, int act) 596 { 597 struct ale_softc *sc = (struct ale_softc *)self; 598 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 599 int rv = 0; 600 601 switch (act) { 602 case DVACT_QUIESCE: 603 rv = config_activate_children(self, act); 604 break; 605 case DVACT_SUSPEND: 606 if (ifp->if_flags & IFF_RUNNING) 607 ale_stop(sc); 608 rv = config_activate_children(self, act); 609 break; 610 case DVACT_RESUME: 611 rv = config_activate_children(self, act); 612 if (ifp->if_flags & IFF_UP) 613 ale_init(ifp); 614 break; 615 } 616 return (rv); 617 } 618 619 int 620 ale_dma_alloc(struct ale_softc *sc) 621 { 622 struct ale_txdesc *txd; 623 int nsegs, error, guard_size, i; 624 625 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 626 guard_size = ALE_JUMBO_FRAMELEN; 627 else 628 guard_size = ALE_MAX_FRAMELEN; 629 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 630 ALE_RX_PAGE_ALIGN); 631 632 /* 633 * Create DMA stuffs for TX ring 634 */ 635 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 636 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 637 if (error) 638 return (ENOBUFS); 639 640 /* Allocate DMA'able memory for TX ring */ 641 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 642 ETHER_ALIGN, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 643 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 644 if (error) { 645 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 646 sc->sc_dev.dv_xname); 647 return error; 648 } 649 650 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 651 nsegs, ALE_TX_RING_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_ring, 652 BUS_DMA_NOWAIT); 653 if (error) 654 return (ENOBUFS); 655 656 /* Load the DMA map for Tx ring. */ 657 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 658 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 659 if (error) { 660 printf("%s: could not load DMA'able memory for Tx ring.\n", 661 sc->sc_dev.dv_xname); 662 bus_dmamem_free(sc->sc_dmat, 663 (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_ring, 1); 664 return error; 665 } 666 sc->ale_cdata.ale_tx_ring_paddr = 667 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 668 669 for (i = 0; i < ALE_RX_PAGES; i++) { 670 /* 671 * Create DMA stuffs for RX pages 672 */ 673 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 674 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 675 &sc->ale_cdata.ale_rx_page[i].page_map); 676 if (error) 677 return (ENOBUFS); 678 679 /* Allocate DMA'able memory for RX pages */ 680 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 681 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 682 1, &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 683 if (error) { 684 printf("%s: could not allocate DMA'able memory for " 685 "Rx ring.\n", sc->sc_dev.dv_xname); 686 return error; 687 } 688 error = bus_dmamem_map(sc->sc_dmat, 689 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 690 sc->ale_pagesize, 691 (caddr_t *)&sc->ale_cdata.ale_rx_page[i].page_addr, 692 BUS_DMA_NOWAIT); 693 if (error) 694 return (ENOBUFS); 695 696 /* Load the DMA map for Rx pages. */ 697 error = bus_dmamap_load(sc->sc_dmat, 698 sc->ale_cdata.ale_rx_page[i].page_map, 699 sc->ale_cdata.ale_rx_page[i].page_addr, 700 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 701 if (error) { 702 printf("%s: could not load DMA'able memory for " 703 "Rx pages.\n", sc->sc_dev.dv_xname); 704 bus_dmamem_free(sc->sc_dmat, 705 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].page_addr, 1); 706 return error; 707 } 708 sc->ale_cdata.ale_rx_page[i].page_paddr = 709 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 710 } 711 712 /* 713 * Create DMA stuffs for Tx CMB. 714 */ 715 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 716 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 717 if (error) 718 return (ENOBUFS); 719 720 /* Allocate DMA'able memory for Tx CMB. */ 721 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 722 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, 723 BUS_DMA_WAITOK |BUS_DMA_ZERO); 724 725 if (error) { 726 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 727 sc->sc_dev.dv_xname); 728 return error; 729 } 730 731 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 732 nsegs, ALE_TX_CMB_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_cmb, 733 BUS_DMA_NOWAIT); 734 if (error) 735 return (ENOBUFS); 736 737 /* Load the DMA map for Tx CMB. */ 738 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 739 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 740 if (error) { 741 printf("%s: could not load DMA'able memory for Tx CMB.\n", 742 sc->sc_dev.dv_xname); 743 bus_dmamem_free(sc->sc_dmat, 744 (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_cmb, 1); 745 return error; 746 } 747 748 sc->ale_cdata.ale_tx_cmb_paddr = 749 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 750 751 for (i = 0; i < ALE_RX_PAGES; i++) { 752 /* 753 * Create DMA stuffs for Rx CMB. 754 */ 755 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 756 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 757 &sc->ale_cdata.ale_rx_page[i].cmb_map); 758 if (error) 759 return (ENOBUFS); 760 761 /* Allocate DMA'able memory for Rx CMB */ 762 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 763 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 764 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 765 if (error) { 766 printf("%s: could not allocate DMA'able memory for " 767 "Rx CMB\n", sc->sc_dev.dv_xname); 768 return error; 769 } 770 error = bus_dmamem_map(sc->sc_dmat, 771 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 772 ALE_RX_CMB_SZ, 773 (caddr_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 774 BUS_DMA_NOWAIT); 775 if (error) 776 return (ENOBUFS); 777 778 /* Load the DMA map for Rx CMB */ 779 error = bus_dmamap_load(sc->sc_dmat, 780 sc->ale_cdata.ale_rx_page[i].cmb_map, 781 sc->ale_cdata.ale_rx_page[i].cmb_addr, 782 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 783 if (error) { 784 printf("%s: could not load DMA'able memory for Rx CMB" 785 "\n", sc->sc_dev.dv_xname); 786 bus_dmamem_free(sc->sc_dmat, 787 (bus_dma_segment_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1); 788 return error; 789 } 790 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 791 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 792 } 793 794 795 /* Create DMA maps for Tx buffers. */ 796 for (i = 0; i < ALE_TX_RING_CNT; i++) { 797 txd = &sc->ale_cdata.ale_txdesc[i]; 798 txd->tx_m = NULL; 799 txd->tx_dmamap = NULL; 800 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 801 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 802 &txd->tx_dmamap); 803 if (error) { 804 printf("%s: could not create Tx dmamap.\n", 805 sc->sc_dev.dv_xname); 806 return error; 807 } 808 } 809 810 return (0); 811 } 812 813 void 814 ale_dma_free(struct ale_softc *sc) 815 { 816 struct ale_txdesc *txd; 817 int i; 818 819 /* Tx buffers. */ 820 for (i = 0; i < ALE_TX_RING_CNT; i++) { 821 txd = &sc->ale_cdata.ale_txdesc[i]; 822 if (txd->tx_dmamap != NULL) { 823 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 824 txd->tx_dmamap = NULL; 825 } 826 } 827 828 /* Tx descriptor ring. */ 829 if (sc->ale_cdata.ale_tx_ring_map != NULL) 830 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 831 if (sc->ale_cdata.ale_tx_ring_map != NULL && 832 sc->ale_cdata.ale_tx_ring != NULL) 833 bus_dmamem_free(sc->sc_dmat, 834 (bus_dma_segment_t *)sc->ale_cdata.ale_tx_ring, 1); 835 sc->ale_cdata.ale_tx_ring = NULL; 836 sc->ale_cdata.ale_tx_ring_map = NULL; 837 838 /* Rx page block. */ 839 for (i = 0; i < ALE_RX_PAGES; i++) { 840 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 841 bus_dmamap_unload(sc->sc_dmat, 842 sc->ale_cdata.ale_rx_page[i].page_map); 843 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 844 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 845 bus_dmamem_free(sc->sc_dmat, 846 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].page_addr, 1); 847 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 848 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 849 } 850 851 /* Rx CMB. */ 852 for (i = 0; i < ALE_RX_PAGES; i++) { 853 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 854 bus_dmamap_unload(sc->sc_dmat, 855 sc->ale_cdata.ale_rx_page[i].cmb_map); 856 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 857 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 858 bus_dmamem_free(sc->sc_dmat, 859 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].cmb_addr, 1); 860 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 861 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 862 } 863 864 /* Tx CMB. */ 865 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 866 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 867 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 868 sc->ale_cdata.ale_tx_cmb != NULL) 869 bus_dmamem_free(sc->sc_dmat, 870 (bus_dma_segment_t *)sc->ale_cdata.ale_tx_cmb, 1); 871 sc->ale_cdata.ale_tx_cmb = NULL; 872 sc->ale_cdata.ale_tx_cmb_map = NULL; 873 874 } 875 876 int 877 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 878 { 879 struct ale_txdesc *txd, *txd_last; 880 struct tx_desc *desc; 881 struct mbuf *m; 882 bus_dmamap_t map; 883 uint32_t cflags, poff, vtag; 884 int error, i, prod; 885 886 m = *m_head; 887 cflags = vtag = 0; 888 poff = 0; 889 890 prod = sc->ale_cdata.ale_tx_prod; 891 txd = &sc->ale_cdata.ale_txdesc[prod]; 892 txd_last = txd; 893 map = txd->tx_dmamap; 894 895 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 896 if (error != 0 && error != EFBIG) 897 goto drop; 898 if (error != 0) { 899 if (m_defrag(*m_head, M_DONTWAIT)) { 900 error = ENOBUFS; 901 goto drop; 902 } 903 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 904 BUS_DMA_NOWAIT); 905 if (error != 0) 906 goto drop; 907 } 908 909 /* Check descriptor overrun. */ 910 if (sc->ale_cdata.ale_tx_cnt + map->dm_nsegs >= ALE_TX_RING_CNT - 2) { 911 bus_dmamap_unload(sc->sc_dmat, map); 912 return (ENOBUFS); 913 } 914 915 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 916 BUS_DMASYNC_PREWRITE); 917 918 m = *m_head; 919 /* Configure Tx checksum offload. */ 920 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 921 /* 922 * AR81xx supports Tx custom checksum offload feature 923 * that offloads single 16bit checksum computation. 924 * So you can choose one among IP, TCP and UDP. 925 * Normally driver sets checksum start/insertion 926 * position from the information of TCP/UDP frame as 927 * TCP/UDP checksum takes more time than that of IP. 928 * However it seems that custom checksum offload 929 * requires 4 bytes aligned Tx buffers due to hardware 930 * bug. 931 * AR81xx also supports explicit Tx checksum computation 932 * if it is told that the size of IP header and TCP 933 * header(for UDP, the header size does not matter 934 * because it's fixed length). However with this scheme 935 * TSO does not work so you have to choose one either 936 * TSO or explicit Tx checksum offload. I chosen TSO 937 * plus custom checksum offload with work-around which 938 * will cover most common usage for this consumer 939 * ethernet controller. The work-around takes a lot of 940 * CPU cycles if Tx buffer is not aligned on 4 bytes 941 * boundary, though. 942 */ 943 cflags |= ALE_TD_CXSUM; 944 /* Set checksum start offset. */ 945 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 946 } 947 948 #if NVLAN > 0 949 /* Configure VLAN hardware tag insertion. */ 950 if (m->m_flags & M_VLANTAG) { 951 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 952 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 953 cflags |= ALE_TD_INSERT_VLAN_TAG; 954 } 955 #endif 956 957 desc = NULL; 958 for (i = 0; i < map->dm_nsegs; i++) { 959 desc = &sc->ale_cdata.ale_tx_ring[prod]; 960 desc->addr = htole64(map->dm_segs[i].ds_addr); 961 desc->len = 962 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 963 desc->flags = htole32(cflags); 964 sc->ale_cdata.ale_tx_cnt++; 965 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 966 } 967 968 /* Update producer index. */ 969 sc->ale_cdata.ale_tx_prod = prod; 970 971 /* Finally set EOP on the last descriptor. */ 972 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 973 desc = &sc->ale_cdata.ale_tx_ring[prod]; 974 desc->flags |= htole32(ALE_TD_EOP); 975 976 /* Swap dmamap of the first and the last. */ 977 txd = &sc->ale_cdata.ale_txdesc[prod]; 978 map = txd_last->tx_dmamap; 979 txd_last->tx_dmamap = txd->tx_dmamap; 980 txd->tx_dmamap = map; 981 txd->tx_m = m; 982 983 /* Sync descriptors. */ 984 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 985 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, 986 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 987 988 return (0); 989 990 drop: 991 m_freem(*m_head); 992 *m_head = NULL; 993 return (error); 994 } 995 996 void 997 ale_start(struct ifnet *ifp) 998 { 999 struct ale_softc *sc = ifp->if_softc; 1000 struct mbuf *m_head; 1001 int enq; 1002 1003 /* Reclaim transmitted frames. */ 1004 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1005 ale_txeof(sc); 1006 1007 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1008 return; 1009 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) 1010 return; 1011 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1012 return; 1013 1014 enq = 0; 1015 for (;;) { 1016 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1017 if (m_head == NULL) 1018 break; 1019 1020 /* 1021 * Pack the data into the transmit ring. If we 1022 * don't have room, set the OACTIVE flag and wait 1023 * for the NIC to drain the ring. 1024 */ 1025 if (ale_encap(sc, &m_head)) { 1026 if (m_head == NULL) 1027 ifp->if_oerrors++; 1028 else { 1029 IF_PREPEND(&ifp->if_snd, m_head); 1030 ifp->if_flags |= IFF_OACTIVE; 1031 } 1032 break; 1033 } 1034 1035 enq = 1; 1036 1037 #if NBPFILTER > 0 1038 /* 1039 * If there's a BPF listener, bounce a copy of this frame 1040 * to him. 1041 */ 1042 if (ifp->if_bpf != NULL) 1043 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1044 #endif 1045 } 1046 1047 if (enq) { 1048 /* Kick. */ 1049 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1050 sc->ale_cdata.ale_tx_prod); 1051 1052 /* Set a timeout in case the chip goes out to lunch. */ 1053 ifp->if_timer = ALE_TX_TIMEOUT; 1054 } 1055 } 1056 1057 void 1058 ale_watchdog(struct ifnet *ifp) 1059 { 1060 struct ale_softc *sc = ifp->if_softc; 1061 1062 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1063 printf("%s: watchdog timeout (missed link)\n", 1064 sc->sc_dev.dv_xname); 1065 ifp->if_oerrors++; 1066 ale_init(ifp); 1067 return; 1068 } 1069 1070 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1071 ifp->if_oerrors++; 1072 ale_init(ifp); 1073 ale_start(ifp); 1074 } 1075 1076 int 1077 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1078 { 1079 struct ale_softc *sc = ifp->if_softc; 1080 struct mii_data *mii = &sc->sc_miibus; 1081 struct ifaddr *ifa = (struct ifaddr *)data; 1082 struct ifreq *ifr = (struct ifreq *)data; 1083 int s, error = 0; 1084 1085 s = splnet(); 1086 1087 switch (cmd) { 1088 case SIOCSIFADDR: 1089 ifp->if_flags |= IFF_UP; 1090 if (!(ifp->if_flags & IFF_RUNNING)) 1091 ale_init(ifp); 1092 #ifdef INET 1093 if (ifa->ifa_addr->sa_family == AF_INET) 1094 arp_ifinit(&sc->sc_arpcom, ifa); 1095 #endif 1096 break; 1097 1098 case SIOCSIFFLAGS: 1099 if (ifp->if_flags & IFF_UP) { 1100 if (ifp->if_flags & IFF_RUNNING) 1101 error = ENETRESET; 1102 else 1103 ale_init(ifp); 1104 } else { 1105 if (ifp->if_flags & IFF_RUNNING) 1106 ale_stop(sc); 1107 } 1108 break; 1109 1110 case SIOCSIFMEDIA: 1111 case SIOCGIFMEDIA: 1112 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1113 break; 1114 1115 default: 1116 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1117 break; 1118 } 1119 1120 if (error == ENETRESET) { 1121 if (ifp->if_flags & IFF_RUNNING) 1122 ale_iff(sc); 1123 error = 0; 1124 } 1125 1126 splx(s); 1127 return (error); 1128 } 1129 1130 void 1131 ale_mac_config(struct ale_softc *sc) 1132 { 1133 struct mii_data *mii; 1134 uint32_t reg; 1135 1136 mii = &sc->sc_miibus; 1137 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1138 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1139 MAC_CFG_SPEED_MASK); 1140 /* Reprogram MAC with resolved speed/duplex. */ 1141 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1142 case IFM_10_T: 1143 case IFM_100_TX: 1144 reg |= MAC_CFG_SPEED_10_100; 1145 break; 1146 case IFM_1000_T: 1147 reg |= MAC_CFG_SPEED_1000; 1148 break; 1149 } 1150 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1151 reg |= MAC_CFG_FULL_DUPLEX; 1152 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1153 reg |= MAC_CFG_TX_FC; 1154 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1155 reg |= MAC_CFG_RX_FC; 1156 } 1157 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1158 } 1159 1160 void 1161 ale_stats_clear(struct ale_softc *sc) 1162 { 1163 struct smb sb; 1164 uint32_t *reg; 1165 int i; 1166 1167 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1168 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1169 i += sizeof(uint32_t); 1170 } 1171 /* Read Tx statistics. */ 1172 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1173 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1174 i += sizeof(uint32_t); 1175 } 1176 } 1177 1178 void 1179 ale_stats_update(struct ale_softc *sc) 1180 { 1181 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1182 struct ale_hw_stats *stat; 1183 struct smb sb, *smb; 1184 uint32_t *reg; 1185 int i; 1186 1187 stat = &sc->ale_stats; 1188 smb = &sb; 1189 1190 /* Read Rx statistics. */ 1191 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1192 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1193 i += sizeof(uint32_t); 1194 } 1195 /* Read Tx statistics. */ 1196 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1197 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1198 i += sizeof(uint32_t); 1199 } 1200 1201 /* Rx stats. */ 1202 stat->rx_frames += smb->rx_frames; 1203 stat->rx_bcast_frames += smb->rx_bcast_frames; 1204 stat->rx_mcast_frames += smb->rx_mcast_frames; 1205 stat->rx_pause_frames += smb->rx_pause_frames; 1206 stat->rx_control_frames += smb->rx_control_frames; 1207 stat->rx_crcerrs += smb->rx_crcerrs; 1208 stat->rx_lenerrs += smb->rx_lenerrs; 1209 stat->rx_bytes += smb->rx_bytes; 1210 stat->rx_runts += smb->rx_runts; 1211 stat->rx_fragments += smb->rx_fragments; 1212 stat->rx_pkts_64 += smb->rx_pkts_64; 1213 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1214 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1215 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1216 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1217 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1218 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1219 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1220 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1221 stat->rx_rrs_errs += smb->rx_rrs_errs; 1222 stat->rx_alignerrs += smb->rx_alignerrs; 1223 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1224 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1225 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1226 1227 /* Tx stats. */ 1228 stat->tx_frames += smb->tx_frames; 1229 stat->tx_bcast_frames += smb->tx_bcast_frames; 1230 stat->tx_mcast_frames += smb->tx_mcast_frames; 1231 stat->tx_pause_frames += smb->tx_pause_frames; 1232 stat->tx_excess_defer += smb->tx_excess_defer; 1233 stat->tx_control_frames += smb->tx_control_frames; 1234 stat->tx_deferred += smb->tx_deferred; 1235 stat->tx_bytes += smb->tx_bytes; 1236 stat->tx_pkts_64 += smb->tx_pkts_64; 1237 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1238 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1239 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1240 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1241 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1242 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1243 stat->tx_single_colls += smb->tx_single_colls; 1244 stat->tx_multi_colls += smb->tx_multi_colls; 1245 stat->tx_late_colls += smb->tx_late_colls; 1246 stat->tx_excess_colls += smb->tx_excess_colls; 1247 stat->tx_abort += smb->tx_abort; 1248 stat->tx_underrun += smb->tx_underrun; 1249 stat->tx_desc_underrun += smb->tx_desc_underrun; 1250 stat->tx_lenerrs += smb->tx_lenerrs; 1251 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1252 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1253 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1254 1255 /* Update counters in ifnet. */ 1256 ifp->if_opackets += smb->tx_frames; 1257 1258 ifp->if_collisions += smb->tx_single_colls + 1259 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1260 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1261 1262 /* 1263 * XXX 1264 * tx_pkts_truncated counter looks suspicious. It constantly 1265 * increments with no sign of Tx errors. This may indicate 1266 * the counter name is not correct one so I've removed the 1267 * counter in output errors. 1268 */ 1269 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1270 smb->tx_underrun; 1271 1272 ifp->if_ipackets += smb->rx_frames; 1273 1274 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1275 smb->rx_runts + smb->rx_pkts_truncated + 1276 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1277 smb->rx_alignerrs; 1278 } 1279 1280 int 1281 ale_intr(void *xsc) 1282 { 1283 struct ale_softc *sc = xsc; 1284 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1285 uint32_t status; 1286 1287 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1288 if ((status & ALE_INTRS) == 0) 1289 return (0); 1290 1291 /* Acknowledge and disable interrupts. */ 1292 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1293 1294 if (ifp->if_flags & IFF_RUNNING) { 1295 int error; 1296 1297 error = ale_rxeof(sc); 1298 if (error) { 1299 sc->ale_stats.reset_brk_seq++; 1300 ale_init(ifp); 1301 return (0); 1302 } 1303 1304 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1305 if (status & INTR_DMA_RD_TO_RST) 1306 printf("%s: DMA read error! -- resetting\n", 1307 sc->sc_dev.dv_xname); 1308 if (status & INTR_DMA_WR_TO_RST) 1309 printf("%s: DMA write error! -- resetting\n", 1310 sc->sc_dev.dv_xname); 1311 ale_init(ifp); 1312 return (0); 1313 } 1314 1315 ale_txeof(sc); 1316 ale_start(ifp); 1317 } 1318 1319 /* Re-enable interrupts. */ 1320 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1321 return (1); 1322 } 1323 1324 void 1325 ale_txeof(struct ale_softc *sc) 1326 { 1327 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1328 struct ale_txdesc *txd; 1329 uint32_t cons, prod; 1330 int prog; 1331 1332 if (sc->ale_cdata.ale_tx_cnt == 0) 1333 return; 1334 1335 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1336 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1337 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1338 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1339 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1340 BUS_DMASYNC_POSTREAD); 1341 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1342 } else 1343 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1344 cons = sc->ale_cdata.ale_tx_cons; 1345 /* 1346 * Go through our Tx list and free mbufs for those 1347 * frames which have been transmitted. 1348 */ 1349 for (prog = 0; cons != prod; prog++, 1350 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1351 if (sc->ale_cdata.ale_tx_cnt <= 0) 1352 break; 1353 prog++; 1354 ifp->if_flags &= ~IFF_OACTIVE; 1355 sc->ale_cdata.ale_tx_cnt--; 1356 txd = &sc->ale_cdata.ale_txdesc[cons]; 1357 if (txd->tx_m != NULL) { 1358 /* Reclaim transmitted mbufs. */ 1359 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 1360 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1361 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1362 m_freem(txd->tx_m); 1363 txd->tx_m = NULL; 1364 } 1365 } 1366 1367 if (prog > 0) { 1368 sc->ale_cdata.ale_tx_cons = cons; 1369 /* 1370 * Unarm watchdog timer only when there is no pending 1371 * Tx descriptors in queue. 1372 */ 1373 if (sc->ale_cdata.ale_tx_cnt == 0) 1374 ifp->if_timer = 0; 1375 } 1376 } 1377 1378 void 1379 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1380 uint32_t length, uint32_t *prod) 1381 { 1382 struct ale_rx_page *rx_page; 1383 1384 rx_page = *page; 1385 /* Update consumer position. */ 1386 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1387 ALE_RX_PAGE_ALIGN); 1388 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1389 /* 1390 * End of Rx page reached, let hardware reuse 1391 * this page. 1392 */ 1393 rx_page->cons = 0; 1394 *rx_page->cmb_addr = 0; 1395 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1396 rx_page->cmb_map->dm_mapsize, 1397 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1398 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1399 RXF_VALID); 1400 /* Switch to alternate Rx page. */ 1401 sc->ale_cdata.ale_rx_curp ^= 1; 1402 rx_page = *page = 1403 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1404 /* Page flipped, sync CMB and Rx page. */ 1405 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1406 rx_page->page_map->dm_mapsize, 1407 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1408 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1409 rx_page->cmb_map->dm_mapsize, 1410 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1411 /* Sync completed, cache updated producer index. */ 1412 *prod = *rx_page->cmb_addr; 1413 } 1414 } 1415 1416 1417 /* 1418 * It seems that AR81xx controller can compute partial checksum. 1419 * The partial checksum value can be used to accelerate checksum 1420 * computation for fragmented TCP/UDP packets. Upper network stack 1421 * already takes advantage of the partial checksum value in IP 1422 * reassembly stage. But I'm not sure the correctness of the 1423 * partial hardware checksum assistance due to lack of data sheet. 1424 * In addition, the Rx feature of controller that requires copying 1425 * for every frames effectively nullifies one of most nice offload 1426 * capability of controller. 1427 */ 1428 void 1429 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1430 { 1431 struct ip *ip; 1432 char *p; 1433 1434 if ((status & ALE_RD_IPCSUM_NOK) == 0) 1435 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1436 1437 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1438 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1439 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1440 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 1441 m->m_pkthdr.csum_flags |= 1442 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1443 } 1444 } else { 1445 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 1446 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 1447 p = mtod(m, char *); 1448 p += ETHER_HDR_LEN; 1449 if ((status & ALE_RD_802_3) != 0) 1450 p += LLC_SNAPFRAMELEN; 1451 #if NVLAN > 0 1452 if (status & ALE_RD_VLAN) 1453 p += EVL_ENCAPLEN; 1454 #endif 1455 ip = (struct ip *)p; 1456 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 1457 return; 1458 m->m_pkthdr.csum_flags |= 1459 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1460 } 1461 } 1462 /* 1463 * Don't mark bad checksum for TCP/UDP frames 1464 * as fragmented frames may always have set 1465 * bad checksummed bit of frame status. 1466 */ 1467 } 1468 1469 /* Process received frames. */ 1470 int 1471 ale_rxeof(struct ale_softc *sc) 1472 { 1473 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1474 struct ale_rx_page *rx_page; 1475 struct rx_rs *rs; 1476 struct mbuf *m; 1477 uint32_t length, prod, seqno, status; 1478 int prog; 1479 1480 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1481 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1482 rx_page->cmb_map->dm_mapsize, 1483 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1484 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1485 rx_page->page_map->dm_mapsize, 1486 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1487 /* 1488 * Don't directly access producer index as hardware may 1489 * update it while Rx handler is in progress. It would 1490 * be even better if there is a way to let hardware 1491 * know how far driver processed its received frames. 1492 * Alternatively, hardware could provide a way to disable 1493 * CMB updates until driver acknowledges the end of CMB 1494 * access. 1495 */ 1496 prod = *rx_page->cmb_addr; 1497 for (prog = 0; ; prog++) { 1498 if (rx_page->cons >= prod) 1499 break; 1500 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1501 seqno = ALE_RX_SEQNO(letoh32(rs->seqno)); 1502 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1503 /* 1504 * Normally I believe this should not happen unless 1505 * severe driver bug or corrupted memory. However 1506 * it seems to happen under certain conditions which 1507 * is triggered by abrupt Rx events such as initiation 1508 * of bulk transfer of remote host. It's not easy to 1509 * reproduce this and I doubt it could be related 1510 * with FIFO overflow of hardware or activity of Tx 1511 * CMB updates. I also remember similar behaviour 1512 * seen on RealTek 8139 which uses resembling Rx 1513 * scheme. 1514 */ 1515 if (aledebug) 1516 printf("%s: garbled seq: %u, expected: %u -- " 1517 "resetting!\n", sc->sc_dev.dv_xname, 1518 seqno, sc->ale_cdata.ale_rx_seqno); 1519 return (EIO); 1520 } 1521 /* Frame received. */ 1522 sc->ale_cdata.ale_rx_seqno++; 1523 length = ALE_RX_BYTES(letoh32(rs->length)); 1524 status = letoh32(rs->flags); 1525 if (status & ALE_RD_ERROR) { 1526 /* 1527 * We want to pass the following frames to upper 1528 * layer regardless of error status of Rx return 1529 * status. 1530 * 1531 * o IP/TCP/UDP checksum is bad. 1532 * o frame length and protocol specific length 1533 * does not match. 1534 */ 1535 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1536 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1537 ALE_RD_TRUNC)) { 1538 ale_rx_update_page(sc, &rx_page, length, &prod); 1539 continue; 1540 } 1541 } 1542 /* 1543 * m_devget(9) is major bottle-neck of ale(4)(It comes 1544 * from hardware limitation). For jumbo frames we could 1545 * get a slightly better performance if driver use 1546 * m_getjcl(9) with proper buffer size argument. However 1547 * that would make code more complicated and I don't 1548 * think users would expect good Rx performance numbers 1549 * on these low-end consumer ethernet controller. 1550 */ 1551 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1552 ETHER_ALIGN, ifp, NULL); 1553 if (m == NULL) { 1554 ifp->if_iqdrops++; 1555 ale_rx_update_page(sc, &rx_page, length, &prod); 1556 continue; 1557 } 1558 if (status & ALE_RD_IPV4) 1559 ale_rxcsum(sc, m, status); 1560 #if NVLAN > 0 1561 if (status & ALE_RD_VLAN) { 1562 uint32_t vtags = ALE_RX_VLAN(letoh32(rs->vtags)); 1563 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 1564 m->m_flags |= M_VLANTAG; 1565 } 1566 #endif 1567 1568 1569 #if NBPFILTER > 0 1570 if (ifp->if_bpf) 1571 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1572 #endif 1573 1574 /* Pass it to upper layer. */ 1575 ether_input_mbuf(ifp, m); 1576 1577 ale_rx_update_page(sc, &rx_page, length, &prod); 1578 } 1579 1580 return 0; 1581 } 1582 1583 void 1584 ale_tick(void *xsc) 1585 { 1586 struct ale_softc *sc = xsc; 1587 struct mii_data *mii = &sc->sc_miibus; 1588 int s; 1589 1590 s = splnet(); 1591 mii_tick(mii); 1592 ale_stats_update(sc); 1593 1594 timeout_add_sec(&sc->ale_tick_ch, 1); 1595 splx(s); 1596 } 1597 1598 void 1599 ale_reset(struct ale_softc *sc) 1600 { 1601 uint32_t reg; 1602 int i; 1603 1604 /* Initialize PCIe module. From Linux. */ 1605 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1606 1607 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1608 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1609 DELAY(10); 1610 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1611 break; 1612 } 1613 if (i == 0) 1614 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); 1615 1616 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1617 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1618 break; 1619 DELAY(10); 1620 } 1621 1622 if (i == 0) 1623 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 1624 reg); 1625 } 1626 1627 int 1628 ale_init(struct ifnet *ifp) 1629 { 1630 struct ale_softc *sc = ifp->if_softc; 1631 struct mii_data *mii; 1632 uint8_t eaddr[ETHER_ADDR_LEN]; 1633 bus_addr_t paddr; 1634 uint32_t reg, rxf_hi, rxf_lo; 1635 1636 /* 1637 * Cancel any pending I/O. 1638 */ 1639 ale_stop(sc); 1640 1641 /* 1642 * Reset the chip to a known state. 1643 */ 1644 ale_reset(sc); 1645 1646 /* Initialize Tx descriptors, DMA memory blocks. */ 1647 ale_init_rx_pages(sc); 1648 ale_init_tx_ring(sc); 1649 1650 /* Reprogram the station address. */ 1651 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 1652 CSR_WRITE_4(sc, ALE_PAR0, 1653 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1654 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1655 1656 /* 1657 * Clear WOL status and disable all WOL feature as WOL 1658 * would interfere Rx operation under normal environments. 1659 */ 1660 CSR_READ_4(sc, ALE_WOL_CFG); 1661 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1662 1663 /* 1664 * Set Tx descriptor/RXF0/CMB base addresses. They share 1665 * the same high address part of DMAable region. 1666 */ 1667 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1668 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1669 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1670 CSR_WRITE_4(sc, ALE_TPD_CNT, 1671 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1672 1673 /* Set Rx page base address, note we use single queue. */ 1674 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1675 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1676 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1677 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1678 1679 /* Set Tx/Rx CMB addresses. */ 1680 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1681 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1682 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1683 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1684 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1685 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1686 1687 /* Mark RXF0 is valid. */ 1688 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1689 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1690 /* 1691 * No need to initialize RFX1/RXF2/RXF3. We don't use 1692 * multi-queue yet. 1693 */ 1694 1695 /* Set Rx page size, excluding guard frame size. */ 1696 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1697 1698 /* Tell hardware that we're ready to load DMA blocks. */ 1699 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1700 1701 /* Set Rx/Tx interrupt trigger threshold. */ 1702 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1703 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1704 /* 1705 * XXX 1706 * Set interrupt trigger timer, its purpose and relation 1707 * with interrupt moderation mechanism is not clear yet. 1708 */ 1709 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1710 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1711 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1712 1713 /* Configure interrupt moderation timer. */ 1714 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1715 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1716 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1717 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1718 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1719 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1720 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1721 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1722 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1723 reg |= MASTER_IM_RX_TIMER_ENB; 1724 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1725 reg |= MASTER_IM_TX_TIMER_ENB; 1726 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1727 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1728 1729 /* Set Maximum frame size of controller. */ 1730 if (ifp->if_mtu < ETHERMTU) 1731 sc->ale_max_frame_size = ETHERMTU; 1732 else 1733 sc->ale_max_frame_size = ifp->if_mtu; 1734 sc->ale_max_frame_size += ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN; 1735 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1736 1737 /* Configure IPG/IFG parameters. */ 1738 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1739 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1740 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1741 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1742 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1743 1744 /* Set parameters for half-duplex media. */ 1745 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1746 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1747 HDPX_CFG_LCOL_MASK) | 1748 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1749 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1750 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1751 HDPX_CFG_ABEBT_MASK) | 1752 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1753 HDPX_CFG_JAMIPG_MASK)); 1754 1755 /* Configure Tx jumbo frame parameters. */ 1756 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1757 if (ifp->if_mtu < ETHERMTU) 1758 reg = sc->ale_max_frame_size; 1759 else if (ifp->if_mtu < 6 * 1024) 1760 reg = (sc->ale_max_frame_size * 2) / 3; 1761 else 1762 reg = sc->ale_max_frame_size / 2; 1763 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1764 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1765 TX_JUMBO_THRESH_UNIT_SHIFT); 1766 } 1767 1768 /* Configure TxQ. */ 1769 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1770 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1771 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1772 TXQ_CFG_TPD_BURST_MASK; 1773 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1774 1775 /* Configure Rx jumbo frame & flow control parameters. */ 1776 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1777 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1778 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1779 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1780 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1781 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1782 RX_JUMBO_LKAH_MASK)); 1783 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1784 rxf_hi = (reg * 7) / 10; 1785 rxf_lo = (reg * 3)/ 10; 1786 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1787 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1788 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1789 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1790 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1791 } 1792 1793 /* Disable RSS. */ 1794 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1795 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1796 1797 /* Configure RxQ. */ 1798 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1799 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1800 1801 /* Configure DMA parameters. */ 1802 reg = 0; 1803 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1804 reg |= DMA_CFG_TXCMB_ENB; 1805 CSR_WRITE_4(sc, ALE_DMA_CFG, 1806 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1807 sc->ale_dma_rd_burst | reg | 1808 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1809 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1810 DMA_CFG_RD_DELAY_CNT_MASK) | 1811 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1812 DMA_CFG_WR_DELAY_CNT_MASK)); 1813 1814 /* 1815 * Hardware can be configured to issue SMB interrupt based 1816 * on programmed interval. Since there is a callout that is 1817 * invoked for every hz in driver we use that instead of 1818 * relying on periodic SMB interrupt. 1819 */ 1820 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1821 1822 /* Clear MAC statistics. */ 1823 ale_stats_clear(sc); 1824 1825 /* 1826 * Configure Tx/Rx MACs. 1827 * - Auto-padding for short frames. 1828 * - Enable CRC generation. 1829 * Actual reconfiguration of MAC for resolved speed/duplex 1830 * is followed after detection of link establishment. 1831 * AR81xx always does checksum computation regardless of 1832 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1833 * cause Rx handling issue for fragmented IP datagrams due 1834 * to silicon bug. 1835 */ 1836 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1837 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1838 MAC_CFG_PREAMBLE_MASK); 1839 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1840 reg |= MAC_CFG_SPEED_10_100; 1841 else 1842 reg |= MAC_CFG_SPEED_1000; 1843 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1844 1845 /* Set up the receive filter. */ 1846 ale_iff(sc); 1847 1848 ale_rxvlan(sc); 1849 1850 /* Acknowledge all pending interrupts and clear it. */ 1851 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1852 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1853 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1854 1855 sc->ale_flags &= ~ALE_FLAG_LINK; 1856 1857 /* Switch to the current media. */ 1858 mii = &sc->sc_miibus; 1859 mii_mediachg(mii); 1860 1861 timeout_add_sec(&sc->ale_tick_ch, 1); 1862 1863 ifp->if_flags |= IFF_RUNNING; 1864 ifp->if_flags &= ~IFF_OACTIVE; 1865 1866 return 0; 1867 } 1868 1869 void 1870 ale_stop(struct ale_softc *sc) 1871 { 1872 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1873 struct ale_txdesc *txd; 1874 uint32_t reg; 1875 int i; 1876 1877 /* 1878 * Mark the interface down and cancel the watchdog timer. 1879 */ 1880 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1881 ifp->if_timer = 0; 1882 1883 timeout_del(&sc->ale_tick_ch); 1884 sc->ale_flags &= ~ALE_FLAG_LINK; 1885 1886 ale_stats_update(sc); 1887 1888 /* Disable interrupts. */ 1889 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1890 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1891 1892 /* Disable queue processing and DMA. */ 1893 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1894 reg &= ~TXQ_CFG_ENB; 1895 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1896 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1897 reg &= ~RXQ_CFG_ENB; 1898 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1899 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1900 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1901 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1902 DELAY(1000); 1903 1904 /* Stop Rx/Tx MACs. */ 1905 ale_stop_mac(sc); 1906 1907 /* Disable interrupts again? XXX */ 1908 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1909 1910 /* 1911 * Free TX mbufs still in the queues. 1912 */ 1913 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1914 txd = &sc->ale_cdata.ale_txdesc[i]; 1915 if (txd->tx_m != NULL) { 1916 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 1917 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1918 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1919 m_freem(txd->tx_m); 1920 txd->tx_m = NULL; 1921 } 1922 } 1923 } 1924 1925 void 1926 ale_stop_mac(struct ale_softc *sc) 1927 { 1928 uint32_t reg; 1929 int i; 1930 1931 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1932 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1933 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1934 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1935 } 1936 1937 for (i = ALE_TIMEOUT; i > 0; i--) { 1938 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1939 if (reg == 0) 1940 break; 1941 DELAY(10); 1942 } 1943 if (i == 0) 1944 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1945 sc->sc_dev.dv_xname, reg); 1946 } 1947 1948 void 1949 ale_init_tx_ring(struct ale_softc *sc) 1950 { 1951 struct ale_txdesc *txd; 1952 int i; 1953 1954 sc->ale_cdata.ale_tx_prod = 0; 1955 sc->ale_cdata.ale_tx_cons = 0; 1956 sc->ale_cdata.ale_tx_cnt = 0; 1957 1958 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 1959 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 1960 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1961 txd = &sc->ale_cdata.ale_txdesc[i]; 1962 txd->tx_m = NULL; 1963 } 1964 *sc->ale_cdata.ale_tx_cmb = 0; 1965 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1966 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1967 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1968 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1969 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, 1970 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1971 } 1972 1973 void 1974 ale_init_rx_pages(struct ale_softc *sc) 1975 { 1976 struct ale_rx_page *rx_page; 1977 int i; 1978 1979 sc->ale_cdata.ale_rx_seqno = 0; 1980 sc->ale_cdata.ale_rx_curp = 0; 1981 1982 for (i = 0; i < ALE_RX_PAGES; i++) { 1983 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1984 bzero(rx_page->page_addr, sc->ale_pagesize); 1985 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 1986 rx_page->cons = 0; 1987 *rx_page->cmb_addr = 0; 1988 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1989 rx_page->page_map->dm_mapsize, 1990 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1991 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1992 rx_page->cmb_map->dm_mapsize, 1993 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1994 } 1995 } 1996 1997 void 1998 ale_rxvlan(struct ale_softc *sc) 1999 { 2000 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2001 uint32_t reg; 2002 2003 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2004 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2005 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 2006 reg |= MAC_CFG_VLAN_TAG_STRIP; 2007 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2008 } 2009 2010 void 2011 ale_iff(struct ale_softc *sc) 2012 { 2013 struct arpcom *ac = &sc->sc_arpcom; 2014 struct ifnet *ifp = &ac->ac_if; 2015 struct ether_multi *enm; 2016 struct ether_multistep step; 2017 uint32_t crc; 2018 uint32_t mchash[2]; 2019 uint32_t rxcfg; 2020 2021 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 2022 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2023 ifp->if_flags &= ~IFF_ALLMULTI; 2024 2025 /* 2026 * Always accept broadcast frames. 2027 */ 2028 rxcfg |= MAC_CFG_BCAST; 2029 2030 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 2031 ifp->if_flags |= IFF_ALLMULTI; 2032 if (ifp->if_flags & IFF_PROMISC) 2033 rxcfg |= MAC_CFG_PROMISC; 2034 else 2035 rxcfg |= MAC_CFG_ALLMULTI; 2036 mchash[0] = mchash[1] = 0xFFFFFFFF; 2037 } else { 2038 /* Program new filter. */ 2039 bzero(mchash, sizeof(mchash)); 2040 2041 ETHER_FIRST_MULTI(step, ac, enm); 2042 while (enm != NULL) { 2043 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2044 2045 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2046 2047 ETHER_NEXT_MULTI(step, enm); 2048 } 2049 } 2050 2051 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2052 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2053 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2054 } 2055