1 /* $OpenBSD: if_ale.c,v 1.30 2013/12/28 03:34:54 deraadt Exp $ */ 2 /*- 3 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 29 */ 30 31 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 32 33 #include "bpfilter.h" 34 #include "vlan.h" 35 36 #include <sys/param.h> 37 #include <sys/endian.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/queue.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/timeout.h> 46 #include <sys/socket.h> 47 48 #include <machine/bus.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_llc.h> 53 #include <net/if_media.h> 54 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_ether.h> 60 #endif 61 62 #include <net/if_types.h> 63 #include <net/if_vlan_var.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <dev/rndvar.h> 70 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcidevs.h> 77 78 #include <dev/pci/if_alereg.h> 79 80 int ale_match(struct device *, void *, void *); 81 void ale_attach(struct device *, struct device *, void *); 82 int ale_detach(struct device *, int); 83 int ale_activate(struct device *, int); 84 85 int ale_miibus_readreg(struct device *, int, int); 86 void ale_miibus_writereg(struct device *, int, int, int); 87 void ale_miibus_statchg(struct device *); 88 89 int ale_init(struct ifnet *); 90 void ale_start(struct ifnet *); 91 int ale_ioctl(struct ifnet *, u_long, caddr_t); 92 void ale_watchdog(struct ifnet *); 93 int ale_mediachange(struct ifnet *); 94 void ale_mediastatus(struct ifnet *, struct ifmediareq *); 95 96 int ale_intr(void *); 97 int ale_rxeof(struct ale_softc *sc); 98 void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 99 uint32_t, uint32_t *); 100 void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 101 void ale_txeof(struct ale_softc *); 102 103 int ale_dma_alloc(struct ale_softc *); 104 void ale_dma_free(struct ale_softc *); 105 int ale_encap(struct ale_softc *, struct mbuf **); 106 void ale_init_rx_pages(struct ale_softc *); 107 void ale_init_tx_ring(struct ale_softc *); 108 109 void ale_stop(struct ale_softc *); 110 void ale_tick(void *); 111 void ale_get_macaddr(struct ale_softc *); 112 void ale_mac_config(struct ale_softc *); 113 void ale_phy_reset(struct ale_softc *); 114 void ale_reset(struct ale_softc *); 115 void ale_iff(struct ale_softc *); 116 void ale_rxvlan(struct ale_softc *); 117 void ale_stats_clear(struct ale_softc *); 118 void ale_stats_update(struct ale_softc *); 119 void ale_stop_mac(struct ale_softc *); 120 121 const struct pci_matchid ale_devices[] = { 122 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1E } 123 }; 124 125 struct cfattach ale_ca = { 126 sizeof (struct ale_softc), ale_match, ale_attach, NULL, 127 ale_activate 128 }; 129 130 struct cfdriver ale_cd = { 131 NULL, "ale", DV_IFNET 132 }; 133 134 int aledebug = 0; 135 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 136 137 #define ALE_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) 138 139 int 140 ale_miibus_readreg(struct device *dev, int phy, int reg) 141 { 142 struct ale_softc *sc = (struct ale_softc *)dev; 143 uint32_t v; 144 int i; 145 146 if (phy != sc->ale_phyaddr) 147 return (0); 148 149 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0 && 150 reg == MII_EXTSR) 151 return (0); 152 153 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 154 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 155 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 156 DELAY(5); 157 v = CSR_READ_4(sc, ALE_MDIO); 158 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 159 break; 160 } 161 162 if (i == 0) { 163 printf("%s: phy read timeout: phy %d, reg %d\n", 164 sc->sc_dev.dv_xname, phy, reg); 165 return (0); 166 } 167 168 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 169 } 170 171 void 172 ale_miibus_writereg(struct device *dev, int phy, int reg, int val) 173 { 174 struct ale_softc *sc = (struct ale_softc *)dev; 175 uint32_t v; 176 int i; 177 178 if (phy != sc->ale_phyaddr) 179 return; 180 181 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 182 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 183 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 184 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 185 DELAY(5); 186 v = CSR_READ_4(sc, ALE_MDIO); 187 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 188 break; 189 } 190 191 if (i == 0) 192 printf("%s: phy write timeout: phy %d, reg %d\n", 193 sc->sc_dev.dv_xname, phy, reg); 194 } 195 196 void 197 ale_miibus_statchg(struct device *dev) 198 { 199 struct ale_softc *sc = (struct ale_softc *)dev; 200 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 201 struct mii_data *mii = &sc->sc_miibus; 202 uint32_t reg; 203 204 if ((ifp->if_flags & IFF_RUNNING) == 0) 205 return; 206 207 sc->ale_flags &= ~ALE_FLAG_LINK; 208 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 209 (IFM_ACTIVE | IFM_AVALID)) { 210 switch (IFM_SUBTYPE(mii->mii_media_active)) { 211 case IFM_10_T: 212 case IFM_100_TX: 213 sc->ale_flags |= ALE_FLAG_LINK; 214 break; 215 216 case IFM_1000_T: 217 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 218 sc->ale_flags |= ALE_FLAG_LINK; 219 break; 220 221 default: 222 break; 223 } 224 } 225 226 /* Stop Rx/Tx MACs. */ 227 ale_stop_mac(sc); 228 229 /* Program MACs with resolved speed/duplex/flow-control. */ 230 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 231 ale_mac_config(sc); 232 /* Reenable Tx/Rx MACs. */ 233 reg = CSR_READ_4(sc, ALE_MAC_CFG); 234 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 235 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 236 } 237 } 238 239 void 240 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 241 { 242 struct ale_softc *sc = ifp->if_softc; 243 struct mii_data *mii = &sc->sc_miibus; 244 245 if ((ifp->if_flags & IFF_UP) == 0) 246 return; 247 248 mii_pollstat(mii); 249 ifmr->ifm_status = mii->mii_media_status; 250 ifmr->ifm_active = mii->mii_media_active; 251 } 252 253 int 254 ale_mediachange(struct ifnet *ifp) 255 { 256 struct ale_softc *sc = ifp->if_softc; 257 struct mii_data *mii = &sc->sc_miibus; 258 int error; 259 260 if (mii->mii_instance != 0) { 261 struct mii_softc *miisc; 262 263 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 264 mii_phy_reset(miisc); 265 } 266 error = mii_mediachg(mii); 267 268 return (error); 269 } 270 271 int 272 ale_match(struct device *dev, void *match, void *aux) 273 { 274 return pci_matchbyid((struct pci_attach_args *)aux, ale_devices, 275 sizeof (ale_devices) / sizeof (ale_devices[0])); 276 } 277 278 void 279 ale_get_macaddr(struct ale_softc *sc) 280 { 281 uint32_t ea[2], reg; 282 int i, vpdc; 283 284 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 285 if ((reg & SPI_VPD_ENB) != 0) { 286 reg &= ~SPI_VPD_ENB; 287 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 288 } 289 290 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 291 &vpdc, NULL)) { 292 /* 293 * PCI VPD capability found, let TWSI reload EEPROM. 294 * This will set ethernet address of controller. 295 */ 296 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 297 TWSI_CTRL_SW_LD_START); 298 for (i = 100; i > 0; i--) { 299 DELAY(1000); 300 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 301 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 302 break; 303 } 304 if (i == 0) 305 printf("%s: reloading EEPROM timeout!\n", 306 sc->sc_dev.dv_xname); 307 } else { 308 if (aledebug) 309 printf("%s: PCI VPD capability not found!\n", 310 sc->sc_dev.dv_xname); 311 } 312 313 ea[0] = CSR_READ_4(sc, ALE_PAR0); 314 ea[1] = CSR_READ_4(sc, ALE_PAR1); 315 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 316 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 317 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 318 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 319 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 320 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 321 } 322 323 void 324 ale_phy_reset(struct ale_softc *sc) 325 { 326 /* Reset magic from Linux. */ 327 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 328 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 329 GPHY_CTRL_PHY_PLL_ON); 330 DELAY(1000); 331 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 332 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 333 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 334 DELAY(1000); 335 336 #define ATPHY_DBG_ADDR 0x1D 337 #define ATPHY_DBG_DATA 0x1E 338 339 /* Enable hibernation mode. */ 340 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 341 ATPHY_DBG_ADDR, 0x0B); 342 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 343 ATPHY_DBG_DATA, 0xBC00); 344 /* Set Class A/B for all modes. */ 345 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 346 ATPHY_DBG_ADDR, 0x00); 347 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 348 ATPHY_DBG_DATA, 0x02EF); 349 /* Enable 10BT power saving. */ 350 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 351 ATPHY_DBG_ADDR, 0x12); 352 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 353 ATPHY_DBG_DATA, 0x4C04); 354 /* Adjust 1000T power. */ 355 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 356 ATPHY_DBG_ADDR, 0x04); 357 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 358 ATPHY_DBG_ADDR, 0x8BBB); 359 /* 10BT center tap voltage. */ 360 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 361 ATPHY_DBG_ADDR, 0x05); 362 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 363 ATPHY_DBG_ADDR, 0x2C46); 364 365 #undef ATPHY_DBG_ADDR 366 #undef ATPHY_DBG_DATA 367 DELAY(1000); 368 } 369 370 void 371 ale_attach(struct device *parent, struct device *self, void *aux) 372 { 373 struct ale_softc *sc = (struct ale_softc *)self; 374 struct pci_attach_args *pa = aux; 375 pci_chipset_tag_t pc = pa->pa_pc; 376 pci_intr_handle_t ih; 377 const char *intrstr; 378 struct ifnet *ifp; 379 pcireg_t memtype; 380 int mii_flags, error = 0; 381 uint32_t rxf_len, txf_len; 382 const char *chipname; 383 384 /* 385 * Allocate IO memory 386 */ 387 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALE_PCIR_BAR); 388 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 389 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 390 printf(": can't map mem space\n"); 391 return; 392 } 393 394 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 395 printf(": can't map interrupt\n"); 396 goto fail; 397 } 398 399 /* 400 * Allocate IRQ 401 */ 402 intrstr = pci_intr_string(pc, ih); 403 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc, 404 sc->sc_dev.dv_xname); 405 if (sc->sc_irq_handle == NULL) { 406 printf(": could not establish interrupt"); 407 if (intrstr != NULL) 408 printf(" at %s", intrstr); 409 printf("\n"); 410 goto fail; 411 } 412 413 sc->sc_dmat = pa->pa_dmat; 414 sc->sc_pct = pa->pa_pc; 415 sc->sc_pcitag = pa->pa_tag; 416 417 /* Set PHY address. */ 418 sc->ale_phyaddr = ALE_PHY_ADDR; 419 420 /* Reset PHY. */ 421 ale_phy_reset(sc); 422 423 /* Reset the ethernet controller. */ 424 ale_reset(sc); 425 426 /* Get PCI and chip id/revision. */ 427 sc->ale_rev = PCI_REVISION(pa->pa_class); 428 if (sc->ale_rev >= 0xF0) { 429 /* L2E Rev. B. AR8114 */ 430 sc->ale_flags |= ALE_FLAG_FASTETHER; 431 chipname = "AR8114"; 432 } else { 433 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 434 /* L1E AR8121 */ 435 sc->ale_flags |= ALE_FLAG_JUMBO; 436 chipname = "AR8121"; 437 } else { 438 /* L2E Rev. A. AR8113 */ 439 sc->ale_flags |= ALE_FLAG_FASTETHER; 440 chipname = "AR8113"; 441 } 442 } 443 444 printf(": %s, %s", chipname, intrstr); 445 446 /* 447 * All known controllers seems to require 4 bytes alignment 448 * of Tx buffers to make Tx checksum offload with custom 449 * checksum generation method work. 450 */ 451 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 452 453 /* 454 * All known controllers seems to have issues on Rx checksum 455 * offload for fragmented IP datagrams. 456 */ 457 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 458 459 /* 460 * Don't use Tx CMB. It is known to cause RRS update failure 461 * under certain circumstances. Typical phenomenon of the 462 * issue would be unexpected sequence number encountered in 463 * Rx handler. 464 */ 465 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 466 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 467 MASTER_CHIP_REV_SHIFT; 468 if (aledebug) { 469 printf("%s: PCI device revision : 0x%04x\n", 470 sc->sc_dev.dv_xname, sc->ale_rev); 471 printf("%s: Chip id/revision : 0x%04x\n", 472 sc->sc_dev.dv_xname, sc->ale_chip_rev); 473 } 474 475 /* 476 * Uninitialized hardware returns an invalid chip id/revision 477 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 478 */ 479 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 480 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 481 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 482 rxf_len == 0xFFFFFFF) { 483 printf("%s: chip revision : 0x%04x, %u Tx FIFO " 484 "%u Rx FIFO -- not initialized?\n", sc->sc_dev.dv_xname, 485 sc->ale_chip_rev, txf_len, rxf_len); 486 goto fail; 487 } 488 489 if (aledebug) { 490 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, 491 txf_len, rxf_len); 492 } 493 494 /* Set max allowable DMA size. */ 495 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 496 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 497 498 error = ale_dma_alloc(sc); 499 if (error) 500 goto fail; 501 502 /* Load station address. */ 503 ale_get_macaddr(sc); 504 505 ifp = &sc->sc_arpcom.ac_if; 506 ifp->if_softc = sc; 507 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 508 ifp->if_ioctl = ale_ioctl; 509 ifp->if_start = ale_start; 510 ifp->if_watchdog = ale_watchdog; 511 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 512 IFQ_SET_READY(&ifp->if_snd); 513 bcopy(sc->ale_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 514 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 515 516 ifp->if_capabilities = IFCAP_VLAN_MTU; 517 518 #ifdef ALE_CHECKSUM 519 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 520 IFCAP_CSUM_UDPv4; 521 #endif 522 523 #if NVLAN > 0 524 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 525 #endif 526 527 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 528 529 /* Set up MII bus. */ 530 sc->sc_miibus.mii_ifp = ifp; 531 sc->sc_miibus.mii_readreg = ale_miibus_readreg; 532 sc->sc_miibus.mii_writereg = ale_miibus_writereg; 533 sc->sc_miibus.mii_statchg = ale_miibus_statchg; 534 535 ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, 536 ale_mediastatus); 537 mii_flags = 0; 538 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 539 mii_flags |= MIIF_DOPAUSE; 540 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 541 MII_OFFSET_ANY, mii_flags); 542 543 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 544 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 545 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 546 0, NULL); 547 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 548 } else 549 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 550 551 if_attach(ifp); 552 ether_ifattach(ifp); 553 554 timeout_set(&sc->ale_tick_ch, ale_tick, sc); 555 556 return; 557 fail: 558 ale_dma_free(sc); 559 if (sc->sc_irq_handle != NULL) 560 pci_intr_disestablish(pc, sc->sc_irq_handle); 561 if (sc->sc_mem_size) 562 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 563 } 564 565 int 566 ale_detach(struct device *self, int flags) 567 { 568 struct ale_softc *sc = (struct ale_softc *)self; 569 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 570 int s; 571 572 s = splnet(); 573 ale_stop(sc); 574 splx(s); 575 576 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 577 578 /* Delete all remaining media. */ 579 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 580 581 ether_ifdetach(ifp); 582 if_detach(ifp); 583 ale_dma_free(sc); 584 585 if (sc->sc_irq_handle != NULL) { 586 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 587 sc->sc_irq_handle = NULL; 588 } 589 590 return (0); 591 } 592 593 int 594 ale_activate(struct device *self, int act) 595 { 596 struct ale_softc *sc = (struct ale_softc *)self; 597 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 598 int rv = 0; 599 600 switch (act) { 601 case DVACT_SUSPEND: 602 if (ifp->if_flags & IFF_RUNNING) 603 ale_stop(sc); 604 rv = config_activate_children(self, act); 605 break; 606 case DVACT_RESUME: 607 if (ifp->if_flags & IFF_UP) 608 ale_init(ifp); 609 break; 610 default: 611 rv = config_activate_children(self, act); 612 break; 613 } 614 return (rv); 615 } 616 617 int 618 ale_dma_alloc(struct ale_softc *sc) 619 { 620 struct ale_txdesc *txd; 621 int nsegs, error, guard_size, i; 622 623 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 624 guard_size = ALE_JUMBO_FRAMELEN; 625 else 626 guard_size = ALE_MAX_FRAMELEN; 627 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 628 ALE_RX_PAGE_ALIGN); 629 630 /* 631 * Create DMA stuffs for TX ring 632 */ 633 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 634 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 635 if (error) 636 return (ENOBUFS); 637 638 /* Allocate DMA'able memory for TX ring */ 639 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 640 ETHER_ALIGN, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 641 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 642 if (error) { 643 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 644 sc->sc_dev.dv_xname); 645 return error; 646 } 647 648 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 649 nsegs, ALE_TX_RING_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_ring, 650 BUS_DMA_NOWAIT); 651 if (error) 652 return (ENOBUFS); 653 654 /* Load the DMA map for Tx ring. */ 655 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 656 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 657 if (error) { 658 printf("%s: could not load DMA'able memory for Tx ring.\n", 659 sc->sc_dev.dv_xname); 660 bus_dmamem_free(sc->sc_dmat, 661 (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_ring, 1); 662 return error; 663 } 664 sc->ale_cdata.ale_tx_ring_paddr = 665 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 666 667 for (i = 0; i < ALE_RX_PAGES; i++) { 668 /* 669 * Create DMA stuffs for RX pages 670 */ 671 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 672 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 673 &sc->ale_cdata.ale_rx_page[i].page_map); 674 if (error) 675 return (ENOBUFS); 676 677 /* Allocate DMA'able memory for RX pages */ 678 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 679 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 680 1, &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 681 if (error) { 682 printf("%s: could not allocate DMA'able memory for " 683 "Rx ring.\n", sc->sc_dev.dv_xname); 684 return error; 685 } 686 error = bus_dmamem_map(sc->sc_dmat, 687 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 688 sc->ale_pagesize, 689 (caddr_t *)&sc->ale_cdata.ale_rx_page[i].page_addr, 690 BUS_DMA_NOWAIT); 691 if (error) 692 return (ENOBUFS); 693 694 /* Load the DMA map for Rx pages. */ 695 error = bus_dmamap_load(sc->sc_dmat, 696 sc->ale_cdata.ale_rx_page[i].page_map, 697 sc->ale_cdata.ale_rx_page[i].page_addr, 698 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 699 if (error) { 700 printf("%s: could not load DMA'able memory for " 701 "Rx pages.\n", sc->sc_dev.dv_xname); 702 bus_dmamem_free(sc->sc_dmat, 703 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].page_addr, 1); 704 return error; 705 } 706 sc->ale_cdata.ale_rx_page[i].page_paddr = 707 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 708 } 709 710 /* 711 * Create DMA stuffs for Tx CMB. 712 */ 713 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 714 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 715 if (error) 716 return (ENOBUFS); 717 718 /* Allocate DMA'able memory for Tx CMB. */ 719 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 720 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, 721 BUS_DMA_WAITOK |BUS_DMA_ZERO); 722 723 if (error) { 724 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 725 sc->sc_dev.dv_xname); 726 return error; 727 } 728 729 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 730 nsegs, ALE_TX_CMB_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_cmb, 731 BUS_DMA_NOWAIT); 732 if (error) 733 return (ENOBUFS); 734 735 /* Load the DMA map for Tx CMB. */ 736 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 737 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 738 if (error) { 739 printf("%s: could not load DMA'able memory for Tx CMB.\n", 740 sc->sc_dev.dv_xname); 741 bus_dmamem_free(sc->sc_dmat, 742 (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_cmb, 1); 743 return error; 744 } 745 746 sc->ale_cdata.ale_tx_cmb_paddr = 747 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 748 749 for (i = 0; i < ALE_RX_PAGES; i++) { 750 /* 751 * Create DMA stuffs for Rx CMB. 752 */ 753 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 754 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 755 &sc->ale_cdata.ale_rx_page[i].cmb_map); 756 if (error) 757 return (ENOBUFS); 758 759 /* Allocate DMA'able memory for Rx CMB */ 760 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 761 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 762 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 763 if (error) { 764 printf("%s: could not allocate DMA'able memory for " 765 "Rx CMB\n", sc->sc_dev.dv_xname); 766 return error; 767 } 768 error = bus_dmamem_map(sc->sc_dmat, 769 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 770 ALE_RX_CMB_SZ, 771 (caddr_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 772 BUS_DMA_NOWAIT); 773 if (error) 774 return (ENOBUFS); 775 776 /* Load the DMA map for Rx CMB */ 777 error = bus_dmamap_load(sc->sc_dmat, 778 sc->ale_cdata.ale_rx_page[i].cmb_map, 779 sc->ale_cdata.ale_rx_page[i].cmb_addr, 780 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 781 if (error) { 782 printf("%s: could not load DMA'able memory for Rx CMB" 783 "\n", sc->sc_dev.dv_xname); 784 bus_dmamem_free(sc->sc_dmat, 785 (bus_dma_segment_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1); 786 return error; 787 } 788 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 789 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 790 } 791 792 793 /* Create DMA maps for Tx buffers. */ 794 for (i = 0; i < ALE_TX_RING_CNT; i++) { 795 txd = &sc->ale_cdata.ale_txdesc[i]; 796 txd->tx_m = NULL; 797 txd->tx_dmamap = NULL; 798 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 799 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 800 &txd->tx_dmamap); 801 if (error) { 802 printf("%s: could not create Tx dmamap.\n", 803 sc->sc_dev.dv_xname); 804 return error; 805 } 806 } 807 808 return (0); 809 } 810 811 void 812 ale_dma_free(struct ale_softc *sc) 813 { 814 struct ale_txdesc *txd; 815 int i; 816 817 /* Tx buffers. */ 818 for (i = 0; i < ALE_TX_RING_CNT; i++) { 819 txd = &sc->ale_cdata.ale_txdesc[i]; 820 if (txd->tx_dmamap != NULL) { 821 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 822 txd->tx_dmamap = NULL; 823 } 824 } 825 826 /* Tx descriptor ring. */ 827 if (sc->ale_cdata.ale_tx_ring_map != NULL) 828 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 829 if (sc->ale_cdata.ale_tx_ring_map != NULL && 830 sc->ale_cdata.ale_tx_ring != NULL) 831 bus_dmamem_free(sc->sc_dmat, 832 (bus_dma_segment_t *)sc->ale_cdata.ale_tx_ring, 1); 833 sc->ale_cdata.ale_tx_ring = NULL; 834 sc->ale_cdata.ale_tx_ring_map = NULL; 835 836 /* Rx page block. */ 837 for (i = 0; i < ALE_RX_PAGES; i++) { 838 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 839 bus_dmamap_unload(sc->sc_dmat, 840 sc->ale_cdata.ale_rx_page[i].page_map); 841 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 842 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 843 bus_dmamem_free(sc->sc_dmat, 844 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].page_addr, 1); 845 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 846 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 847 } 848 849 /* Rx CMB. */ 850 for (i = 0; i < ALE_RX_PAGES; i++) { 851 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 852 bus_dmamap_unload(sc->sc_dmat, 853 sc->ale_cdata.ale_rx_page[i].cmb_map); 854 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 855 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 856 bus_dmamem_free(sc->sc_dmat, 857 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].cmb_addr, 1); 858 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 859 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 860 } 861 862 /* Tx CMB. */ 863 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 864 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 865 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 866 sc->ale_cdata.ale_tx_cmb != NULL) 867 bus_dmamem_free(sc->sc_dmat, 868 (bus_dma_segment_t *)sc->ale_cdata.ale_tx_cmb, 1); 869 sc->ale_cdata.ale_tx_cmb = NULL; 870 sc->ale_cdata.ale_tx_cmb_map = NULL; 871 872 } 873 874 int 875 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 876 { 877 struct ale_txdesc *txd, *txd_last; 878 struct tx_desc *desc; 879 struct mbuf *m; 880 bus_dmamap_t map; 881 uint32_t cflags, poff, vtag; 882 int error, i, prod; 883 884 m = *m_head; 885 cflags = vtag = 0; 886 poff = 0; 887 888 prod = sc->ale_cdata.ale_tx_prod; 889 txd = &sc->ale_cdata.ale_txdesc[prod]; 890 txd_last = txd; 891 map = txd->tx_dmamap; 892 893 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 894 if (error != 0 && error != EFBIG) 895 goto drop; 896 if (error != 0) { 897 if (m_defrag(*m_head, M_DONTWAIT)) { 898 error = ENOBUFS; 899 goto drop; 900 } 901 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 902 BUS_DMA_NOWAIT); 903 if (error != 0) 904 goto drop; 905 } 906 907 /* Check descriptor overrun. */ 908 if (sc->ale_cdata.ale_tx_cnt + map->dm_nsegs >= ALE_TX_RING_CNT - 2) { 909 bus_dmamap_unload(sc->sc_dmat, map); 910 return (ENOBUFS); 911 } 912 913 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 914 BUS_DMASYNC_PREWRITE); 915 916 m = *m_head; 917 /* Configure Tx checksum offload. */ 918 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 919 /* 920 * AR81xx supports Tx custom checksum offload feature 921 * that offloads single 16bit checksum computation. 922 * So you can choose one among IP, TCP and UDP. 923 * Normally driver sets checksum start/insertion 924 * position from the information of TCP/UDP frame as 925 * TCP/UDP checksum takes more time than that of IP. 926 * However it seems that custom checksum offload 927 * requires 4 bytes aligned Tx buffers due to hardware 928 * bug. 929 * AR81xx also supports explicit Tx checksum computation 930 * if it is told that the size of IP header and TCP 931 * header(for UDP, the header size does not matter 932 * because it's fixed length). However with this scheme 933 * TSO does not work so you have to choose one either 934 * TSO or explicit Tx checksum offload. I chosen TSO 935 * plus custom checksum offload with work-around which 936 * will cover most common usage for this consumer 937 * ethernet controller. The work-around takes a lot of 938 * CPU cycles if Tx buffer is not aligned on 4 bytes 939 * boundary, though. 940 */ 941 cflags |= ALE_TD_CXSUM; 942 /* Set checksum start offset. */ 943 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 944 } 945 946 #if NVLAN > 0 947 /* Configure VLAN hardware tag insertion. */ 948 if (m->m_flags & M_VLANTAG) { 949 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 950 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 951 cflags |= ALE_TD_INSERT_VLAN_TAG; 952 } 953 #endif 954 955 desc = NULL; 956 for (i = 0; i < map->dm_nsegs; i++) { 957 desc = &sc->ale_cdata.ale_tx_ring[prod]; 958 desc->addr = htole64(map->dm_segs[i].ds_addr); 959 desc->len = 960 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 961 desc->flags = htole32(cflags); 962 sc->ale_cdata.ale_tx_cnt++; 963 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 964 } 965 966 /* Update producer index. */ 967 sc->ale_cdata.ale_tx_prod = prod; 968 969 /* Finally set EOP on the last descriptor. */ 970 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 971 desc = &sc->ale_cdata.ale_tx_ring[prod]; 972 desc->flags |= htole32(ALE_TD_EOP); 973 974 /* Swap dmamap of the first and the last. */ 975 txd = &sc->ale_cdata.ale_txdesc[prod]; 976 map = txd_last->tx_dmamap; 977 txd_last->tx_dmamap = txd->tx_dmamap; 978 txd->tx_dmamap = map; 979 txd->tx_m = m; 980 981 /* Sync descriptors. */ 982 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 983 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, 984 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 985 986 return (0); 987 988 drop: 989 m_freem(*m_head); 990 *m_head = NULL; 991 return (error); 992 } 993 994 void 995 ale_start(struct ifnet *ifp) 996 { 997 struct ale_softc *sc = ifp->if_softc; 998 struct mbuf *m_head; 999 int enq; 1000 1001 /* Reclaim transmitted frames. */ 1002 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1003 ale_txeof(sc); 1004 1005 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1006 return; 1007 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) 1008 return; 1009 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1010 return; 1011 1012 enq = 0; 1013 for (;;) { 1014 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1015 if (m_head == NULL) 1016 break; 1017 1018 /* 1019 * Pack the data into the transmit ring. If we 1020 * don't have room, set the OACTIVE flag and wait 1021 * for the NIC to drain the ring. 1022 */ 1023 if (ale_encap(sc, &m_head)) { 1024 if (m_head == NULL) 1025 ifp->if_oerrors++; 1026 else { 1027 IF_PREPEND(&ifp->if_snd, m_head); 1028 ifp->if_flags |= IFF_OACTIVE; 1029 } 1030 break; 1031 } 1032 1033 enq = 1; 1034 1035 #if NBPFILTER > 0 1036 /* 1037 * If there's a BPF listener, bounce a copy of this frame 1038 * to him. 1039 */ 1040 if (ifp->if_bpf != NULL) 1041 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1042 #endif 1043 } 1044 1045 if (enq) { 1046 /* Kick. */ 1047 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1048 sc->ale_cdata.ale_tx_prod); 1049 1050 /* Set a timeout in case the chip goes out to lunch. */ 1051 ifp->if_timer = ALE_TX_TIMEOUT; 1052 } 1053 } 1054 1055 void 1056 ale_watchdog(struct ifnet *ifp) 1057 { 1058 struct ale_softc *sc = ifp->if_softc; 1059 1060 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1061 printf("%s: watchdog timeout (missed link)\n", 1062 sc->sc_dev.dv_xname); 1063 ifp->if_oerrors++; 1064 ale_init(ifp); 1065 return; 1066 } 1067 1068 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1069 ifp->if_oerrors++; 1070 ale_init(ifp); 1071 ale_start(ifp); 1072 } 1073 1074 int 1075 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1076 { 1077 struct ale_softc *sc = ifp->if_softc; 1078 struct mii_data *mii = &sc->sc_miibus; 1079 struct ifaddr *ifa = (struct ifaddr *)data; 1080 struct ifreq *ifr = (struct ifreq *)data; 1081 int s, error = 0; 1082 1083 s = splnet(); 1084 1085 switch (cmd) { 1086 case SIOCSIFADDR: 1087 ifp->if_flags |= IFF_UP; 1088 if (!(ifp->if_flags & IFF_RUNNING)) 1089 ale_init(ifp); 1090 #ifdef INET 1091 if (ifa->ifa_addr->sa_family == AF_INET) 1092 arp_ifinit(&sc->sc_arpcom, ifa); 1093 #endif 1094 break; 1095 1096 case SIOCSIFFLAGS: 1097 if (ifp->if_flags & IFF_UP) { 1098 if (ifp->if_flags & IFF_RUNNING) 1099 error = ENETRESET; 1100 else 1101 ale_init(ifp); 1102 } else { 1103 if (ifp->if_flags & IFF_RUNNING) 1104 ale_stop(sc); 1105 } 1106 break; 1107 1108 case SIOCSIFMEDIA: 1109 case SIOCGIFMEDIA: 1110 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1111 break; 1112 1113 default: 1114 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1115 break; 1116 } 1117 1118 if (error == ENETRESET) { 1119 if (ifp->if_flags & IFF_RUNNING) 1120 ale_iff(sc); 1121 error = 0; 1122 } 1123 1124 splx(s); 1125 return (error); 1126 } 1127 1128 void 1129 ale_mac_config(struct ale_softc *sc) 1130 { 1131 struct mii_data *mii; 1132 uint32_t reg; 1133 1134 mii = &sc->sc_miibus; 1135 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1136 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1137 MAC_CFG_SPEED_MASK); 1138 /* Reprogram MAC with resolved speed/duplex. */ 1139 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1140 case IFM_10_T: 1141 case IFM_100_TX: 1142 reg |= MAC_CFG_SPEED_10_100; 1143 break; 1144 case IFM_1000_T: 1145 reg |= MAC_CFG_SPEED_1000; 1146 break; 1147 } 1148 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1149 reg |= MAC_CFG_FULL_DUPLEX; 1150 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1151 reg |= MAC_CFG_TX_FC; 1152 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1153 reg |= MAC_CFG_RX_FC; 1154 } 1155 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1156 } 1157 1158 void 1159 ale_stats_clear(struct ale_softc *sc) 1160 { 1161 struct smb sb; 1162 uint32_t *reg; 1163 int i; 1164 1165 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1166 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1167 i += sizeof(uint32_t); 1168 } 1169 /* Read Tx statistics. */ 1170 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1171 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1172 i += sizeof(uint32_t); 1173 } 1174 } 1175 1176 void 1177 ale_stats_update(struct ale_softc *sc) 1178 { 1179 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1180 struct ale_hw_stats *stat; 1181 struct smb sb, *smb; 1182 uint32_t *reg; 1183 int i; 1184 1185 stat = &sc->ale_stats; 1186 smb = &sb; 1187 1188 /* Read Rx statistics. */ 1189 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1190 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1191 i += sizeof(uint32_t); 1192 } 1193 /* Read Tx statistics. */ 1194 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1195 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1196 i += sizeof(uint32_t); 1197 } 1198 1199 /* Rx stats. */ 1200 stat->rx_frames += smb->rx_frames; 1201 stat->rx_bcast_frames += smb->rx_bcast_frames; 1202 stat->rx_mcast_frames += smb->rx_mcast_frames; 1203 stat->rx_pause_frames += smb->rx_pause_frames; 1204 stat->rx_control_frames += smb->rx_control_frames; 1205 stat->rx_crcerrs += smb->rx_crcerrs; 1206 stat->rx_lenerrs += smb->rx_lenerrs; 1207 stat->rx_bytes += smb->rx_bytes; 1208 stat->rx_runts += smb->rx_runts; 1209 stat->rx_fragments += smb->rx_fragments; 1210 stat->rx_pkts_64 += smb->rx_pkts_64; 1211 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1212 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1213 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1214 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1215 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1216 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1217 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1218 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1219 stat->rx_rrs_errs += smb->rx_rrs_errs; 1220 stat->rx_alignerrs += smb->rx_alignerrs; 1221 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1222 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1223 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1224 1225 /* Tx stats. */ 1226 stat->tx_frames += smb->tx_frames; 1227 stat->tx_bcast_frames += smb->tx_bcast_frames; 1228 stat->tx_mcast_frames += smb->tx_mcast_frames; 1229 stat->tx_pause_frames += smb->tx_pause_frames; 1230 stat->tx_excess_defer += smb->tx_excess_defer; 1231 stat->tx_control_frames += smb->tx_control_frames; 1232 stat->tx_deferred += smb->tx_deferred; 1233 stat->tx_bytes += smb->tx_bytes; 1234 stat->tx_pkts_64 += smb->tx_pkts_64; 1235 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1236 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1237 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1238 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1239 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1240 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1241 stat->tx_single_colls += smb->tx_single_colls; 1242 stat->tx_multi_colls += smb->tx_multi_colls; 1243 stat->tx_late_colls += smb->tx_late_colls; 1244 stat->tx_excess_colls += smb->tx_excess_colls; 1245 stat->tx_abort += smb->tx_abort; 1246 stat->tx_underrun += smb->tx_underrun; 1247 stat->tx_desc_underrun += smb->tx_desc_underrun; 1248 stat->tx_lenerrs += smb->tx_lenerrs; 1249 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1250 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1251 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1252 1253 /* Update counters in ifnet. */ 1254 ifp->if_opackets += smb->tx_frames; 1255 1256 ifp->if_collisions += smb->tx_single_colls + 1257 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1258 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1259 1260 /* 1261 * XXX 1262 * tx_pkts_truncated counter looks suspicious. It constantly 1263 * increments with no sign of Tx errors. This may indicate 1264 * the counter name is not correct one so I've removed the 1265 * counter in output errors. 1266 */ 1267 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1268 smb->tx_underrun; 1269 1270 ifp->if_ipackets += smb->rx_frames; 1271 1272 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1273 smb->rx_runts + smb->rx_pkts_truncated + 1274 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1275 smb->rx_alignerrs; 1276 } 1277 1278 int 1279 ale_intr(void *xsc) 1280 { 1281 struct ale_softc *sc = xsc; 1282 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1283 uint32_t status; 1284 1285 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1286 if ((status & ALE_INTRS) == 0) 1287 return (0); 1288 1289 /* Acknowledge and disable interrupts. */ 1290 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1291 1292 if (ifp->if_flags & IFF_RUNNING) { 1293 int error; 1294 1295 error = ale_rxeof(sc); 1296 if (error) { 1297 sc->ale_stats.reset_brk_seq++; 1298 ale_init(ifp); 1299 return (0); 1300 } 1301 1302 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1303 if (status & INTR_DMA_RD_TO_RST) 1304 printf("%s: DMA read error! -- resetting\n", 1305 sc->sc_dev.dv_xname); 1306 if (status & INTR_DMA_WR_TO_RST) 1307 printf("%s: DMA write error! -- resetting\n", 1308 sc->sc_dev.dv_xname); 1309 ale_init(ifp); 1310 return (0); 1311 } 1312 1313 ale_txeof(sc); 1314 ale_start(ifp); 1315 } 1316 1317 /* Re-enable interrupts. */ 1318 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1319 return (1); 1320 } 1321 1322 void 1323 ale_txeof(struct ale_softc *sc) 1324 { 1325 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1326 struct ale_txdesc *txd; 1327 uint32_t cons, prod; 1328 int prog; 1329 1330 if (sc->ale_cdata.ale_tx_cnt == 0) 1331 return; 1332 1333 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1334 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1335 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1336 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1337 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1338 BUS_DMASYNC_POSTREAD); 1339 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1340 } else 1341 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1342 cons = sc->ale_cdata.ale_tx_cons; 1343 /* 1344 * Go through our Tx list and free mbufs for those 1345 * frames which have been transmitted. 1346 */ 1347 for (prog = 0; cons != prod; prog++, 1348 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1349 if (sc->ale_cdata.ale_tx_cnt <= 0) 1350 break; 1351 prog++; 1352 ifp->if_flags &= ~IFF_OACTIVE; 1353 sc->ale_cdata.ale_tx_cnt--; 1354 txd = &sc->ale_cdata.ale_txdesc[cons]; 1355 if (txd->tx_m != NULL) { 1356 /* Reclaim transmitted mbufs. */ 1357 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 1358 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1359 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1360 m_freem(txd->tx_m); 1361 txd->tx_m = NULL; 1362 } 1363 } 1364 1365 if (prog > 0) { 1366 sc->ale_cdata.ale_tx_cons = cons; 1367 /* 1368 * Unarm watchdog timer only when there is no pending 1369 * Tx descriptors in queue. 1370 */ 1371 if (sc->ale_cdata.ale_tx_cnt == 0) 1372 ifp->if_timer = 0; 1373 } 1374 } 1375 1376 void 1377 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1378 uint32_t length, uint32_t *prod) 1379 { 1380 struct ale_rx_page *rx_page; 1381 1382 rx_page = *page; 1383 /* Update consumer position. */ 1384 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1385 ALE_RX_PAGE_ALIGN); 1386 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1387 /* 1388 * End of Rx page reached, let hardware reuse 1389 * this page. 1390 */ 1391 rx_page->cons = 0; 1392 *rx_page->cmb_addr = 0; 1393 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1394 rx_page->cmb_map->dm_mapsize, 1395 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1396 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1397 RXF_VALID); 1398 /* Switch to alternate Rx page. */ 1399 sc->ale_cdata.ale_rx_curp ^= 1; 1400 rx_page = *page = 1401 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1402 /* Page flipped, sync CMB and Rx page. */ 1403 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1404 rx_page->page_map->dm_mapsize, 1405 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1406 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1407 rx_page->cmb_map->dm_mapsize, 1408 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1409 /* Sync completed, cache updated producer index. */ 1410 *prod = *rx_page->cmb_addr; 1411 } 1412 } 1413 1414 1415 /* 1416 * It seems that AR81xx controller can compute partial checksum. 1417 * The partial checksum value can be used to accelerate checksum 1418 * computation for fragmented TCP/UDP packets. Upper network stack 1419 * already takes advantage of the partial checksum value in IP 1420 * reassembly stage. But I'm not sure the correctness of the 1421 * partial hardware checksum assistance due to lack of data sheet. 1422 * In addition, the Rx feature of controller that requires copying 1423 * for every frames effectively nullifies one of most nice offload 1424 * capability of controller. 1425 */ 1426 void 1427 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1428 { 1429 struct ip *ip; 1430 char *p; 1431 1432 if ((status & ALE_RD_IPCSUM_NOK) == 0) 1433 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1434 1435 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1436 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1437 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1438 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 1439 m->m_pkthdr.csum_flags |= 1440 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1441 } 1442 } else { 1443 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 1444 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 1445 p = mtod(m, char *); 1446 p += ETHER_HDR_LEN; 1447 if ((status & ALE_RD_802_3) != 0) 1448 p += LLC_SNAPFRAMELEN; 1449 #if NVLAN > 0 1450 if (status & ALE_RD_VLAN) 1451 p += EVL_ENCAPLEN; 1452 #endif 1453 ip = (struct ip *)p; 1454 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 1455 return; 1456 m->m_pkthdr.csum_flags |= 1457 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1458 } 1459 } 1460 /* 1461 * Don't mark bad checksum for TCP/UDP frames 1462 * as fragmented frames may always have set 1463 * bad checksummed bit of frame status. 1464 */ 1465 } 1466 1467 /* Process received frames. */ 1468 int 1469 ale_rxeof(struct ale_softc *sc) 1470 { 1471 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1472 struct ale_rx_page *rx_page; 1473 struct rx_rs *rs; 1474 struct mbuf *m; 1475 uint32_t length, prod, seqno, status; 1476 int prog; 1477 1478 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1479 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1480 rx_page->cmb_map->dm_mapsize, 1481 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1482 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1483 rx_page->page_map->dm_mapsize, 1484 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1485 /* 1486 * Don't directly access producer index as hardware may 1487 * update it while Rx handler is in progress. It would 1488 * be even better if there is a way to let hardware 1489 * know how far driver processed its received frames. 1490 * Alternatively, hardware could provide a way to disable 1491 * CMB updates until driver acknowledges the end of CMB 1492 * access. 1493 */ 1494 prod = *rx_page->cmb_addr; 1495 for (prog = 0; ; prog++) { 1496 if (rx_page->cons >= prod) 1497 break; 1498 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1499 seqno = ALE_RX_SEQNO(letoh32(rs->seqno)); 1500 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1501 /* 1502 * Normally I believe this should not happen unless 1503 * severe driver bug or corrupted memory. However 1504 * it seems to happen under certain conditions which 1505 * is triggered by abrupt Rx events such as initiation 1506 * of bulk transfer of remote host. It's not easy to 1507 * reproduce this and I doubt it could be related 1508 * with FIFO overflow of hardware or activity of Tx 1509 * CMB updates. I also remember similar behaviour 1510 * seen on RealTek 8139 which uses resembling Rx 1511 * scheme. 1512 */ 1513 if (aledebug) 1514 printf("%s: garbled seq: %u, expected: %u -- " 1515 "resetting!\n", sc->sc_dev.dv_xname, 1516 seqno, sc->ale_cdata.ale_rx_seqno); 1517 return (EIO); 1518 } 1519 /* Frame received. */ 1520 sc->ale_cdata.ale_rx_seqno++; 1521 length = ALE_RX_BYTES(letoh32(rs->length)); 1522 status = letoh32(rs->flags); 1523 if (status & ALE_RD_ERROR) { 1524 /* 1525 * We want to pass the following frames to upper 1526 * layer regardless of error status of Rx return 1527 * status. 1528 * 1529 * o IP/TCP/UDP checksum is bad. 1530 * o frame length and protocol specific length 1531 * does not match. 1532 */ 1533 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1534 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1535 ALE_RD_TRUNC)) { 1536 ale_rx_update_page(sc, &rx_page, length, &prod); 1537 continue; 1538 } 1539 } 1540 /* 1541 * m_devget(9) is major bottle-neck of ale(4)(It comes 1542 * from hardware limitation). For jumbo frames we could 1543 * get a slightly better performance if driver use 1544 * m_getjcl(9) with proper buffer size argument. However 1545 * that would make code more complicated and I don't 1546 * think users would expect good Rx performance numbers 1547 * on these low-end consumer ethernet controller. 1548 */ 1549 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1550 ETHER_ALIGN, ifp); 1551 if (m == NULL) { 1552 ifp->if_iqdrops++; 1553 ale_rx_update_page(sc, &rx_page, length, &prod); 1554 continue; 1555 } 1556 if (status & ALE_RD_IPV4) 1557 ale_rxcsum(sc, m, status); 1558 #if NVLAN > 0 1559 if (status & ALE_RD_VLAN) { 1560 uint32_t vtags = ALE_RX_VLAN(letoh32(rs->vtags)); 1561 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 1562 m->m_flags |= M_VLANTAG; 1563 } 1564 #endif 1565 1566 1567 #if NBPFILTER > 0 1568 if (ifp->if_bpf) 1569 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1570 #endif 1571 1572 /* Pass it to upper layer. */ 1573 ether_input_mbuf(ifp, m); 1574 1575 ale_rx_update_page(sc, &rx_page, length, &prod); 1576 } 1577 1578 return 0; 1579 } 1580 1581 void 1582 ale_tick(void *xsc) 1583 { 1584 struct ale_softc *sc = xsc; 1585 struct mii_data *mii = &sc->sc_miibus; 1586 int s; 1587 1588 s = splnet(); 1589 mii_tick(mii); 1590 ale_stats_update(sc); 1591 1592 timeout_add_sec(&sc->ale_tick_ch, 1); 1593 splx(s); 1594 } 1595 1596 void 1597 ale_reset(struct ale_softc *sc) 1598 { 1599 uint32_t reg; 1600 int i; 1601 1602 /* Initialize PCIe module. From Linux. */ 1603 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1604 1605 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1606 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1607 DELAY(10); 1608 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1609 break; 1610 } 1611 if (i == 0) 1612 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); 1613 1614 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1615 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1616 break; 1617 DELAY(10); 1618 } 1619 1620 if (i == 0) 1621 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 1622 reg); 1623 } 1624 1625 int 1626 ale_init(struct ifnet *ifp) 1627 { 1628 struct ale_softc *sc = ifp->if_softc; 1629 struct mii_data *mii; 1630 uint8_t eaddr[ETHER_ADDR_LEN]; 1631 bus_addr_t paddr; 1632 uint32_t reg, rxf_hi, rxf_lo; 1633 1634 /* 1635 * Cancel any pending I/O. 1636 */ 1637 ale_stop(sc); 1638 1639 /* 1640 * Reset the chip to a known state. 1641 */ 1642 ale_reset(sc); 1643 1644 /* Initialize Tx descriptors, DMA memory blocks. */ 1645 ale_init_rx_pages(sc); 1646 ale_init_tx_ring(sc); 1647 1648 /* Reprogram the station address. */ 1649 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 1650 CSR_WRITE_4(sc, ALE_PAR0, 1651 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1652 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1653 1654 /* 1655 * Clear WOL status and disable all WOL feature as WOL 1656 * would interfere Rx operation under normal environments. 1657 */ 1658 CSR_READ_4(sc, ALE_WOL_CFG); 1659 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1660 1661 /* 1662 * Set Tx descriptor/RXF0/CMB base addresses. They share 1663 * the same high address part of DMAable region. 1664 */ 1665 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1666 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1667 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1668 CSR_WRITE_4(sc, ALE_TPD_CNT, 1669 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1670 1671 /* Set Rx page base address, note we use single queue. */ 1672 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1673 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1674 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1675 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1676 1677 /* Set Tx/Rx CMB addresses. */ 1678 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1679 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1680 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1681 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1682 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1683 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1684 1685 /* Mark RXF0 is valid. */ 1686 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1687 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1688 /* 1689 * No need to initialize RFX1/RXF2/RXF3. We don't use 1690 * multi-queue yet. 1691 */ 1692 1693 /* Set Rx page size, excluding guard frame size. */ 1694 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1695 1696 /* Tell hardware that we're ready to load DMA blocks. */ 1697 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1698 1699 /* Set Rx/Tx interrupt trigger threshold. */ 1700 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1701 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1702 /* 1703 * XXX 1704 * Set interrupt trigger timer, its purpose and relation 1705 * with interrupt moderation mechanism is not clear yet. 1706 */ 1707 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1708 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1709 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1710 1711 /* Configure interrupt moderation timer. */ 1712 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1713 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1714 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1715 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1716 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1717 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1718 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1719 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1720 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1721 reg |= MASTER_IM_RX_TIMER_ENB; 1722 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1723 reg |= MASTER_IM_TX_TIMER_ENB; 1724 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1725 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1726 1727 /* Set Maximum frame size of controller. */ 1728 if (ifp->if_mtu < ETHERMTU) 1729 sc->ale_max_frame_size = ETHERMTU; 1730 else 1731 sc->ale_max_frame_size = ifp->if_mtu; 1732 sc->ale_max_frame_size += ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN; 1733 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1734 1735 /* Configure IPG/IFG parameters. */ 1736 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1737 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1738 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1739 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1740 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1741 1742 /* Set parameters for half-duplex media. */ 1743 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1744 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1745 HDPX_CFG_LCOL_MASK) | 1746 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1747 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1748 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1749 HDPX_CFG_ABEBT_MASK) | 1750 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1751 HDPX_CFG_JAMIPG_MASK)); 1752 1753 /* Configure Tx jumbo frame parameters. */ 1754 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1755 if (ifp->if_mtu < ETHERMTU) 1756 reg = sc->ale_max_frame_size; 1757 else if (ifp->if_mtu < 6 * 1024) 1758 reg = (sc->ale_max_frame_size * 2) / 3; 1759 else 1760 reg = sc->ale_max_frame_size / 2; 1761 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1762 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1763 TX_JUMBO_THRESH_UNIT_SHIFT); 1764 } 1765 1766 /* Configure TxQ. */ 1767 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1768 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1769 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1770 TXQ_CFG_TPD_BURST_MASK; 1771 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1772 1773 /* Configure Rx jumbo frame & flow control parameters. */ 1774 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1775 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1776 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1777 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1778 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1779 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1780 RX_JUMBO_LKAH_MASK)); 1781 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1782 rxf_hi = (reg * 7) / 10; 1783 rxf_lo = (reg * 3)/ 10; 1784 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1785 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1786 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1787 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1788 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1789 } 1790 1791 /* Disable RSS. */ 1792 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1793 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1794 1795 /* Configure RxQ. */ 1796 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1797 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1798 1799 /* Configure DMA parameters. */ 1800 reg = 0; 1801 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1802 reg |= DMA_CFG_TXCMB_ENB; 1803 CSR_WRITE_4(sc, ALE_DMA_CFG, 1804 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1805 sc->ale_dma_rd_burst | reg | 1806 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1807 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1808 DMA_CFG_RD_DELAY_CNT_MASK) | 1809 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1810 DMA_CFG_WR_DELAY_CNT_MASK)); 1811 1812 /* 1813 * Hardware can be configured to issue SMB interrupt based 1814 * on programmed interval. Since there is a callout that is 1815 * invoked for every hz in driver we use that instead of 1816 * relying on periodic SMB interrupt. 1817 */ 1818 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1819 1820 /* Clear MAC statistics. */ 1821 ale_stats_clear(sc); 1822 1823 /* 1824 * Configure Tx/Rx MACs. 1825 * - Auto-padding for short frames. 1826 * - Enable CRC generation. 1827 * Actual reconfiguration of MAC for resolved speed/duplex 1828 * is followed after detection of link establishment. 1829 * AR81xx always does checksum computation regardless of 1830 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1831 * cause Rx handling issue for fragmented IP datagrams due 1832 * to silicon bug. 1833 */ 1834 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1835 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1836 MAC_CFG_PREAMBLE_MASK); 1837 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1838 reg |= MAC_CFG_SPEED_10_100; 1839 else 1840 reg |= MAC_CFG_SPEED_1000; 1841 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1842 1843 /* Set up the receive filter. */ 1844 ale_iff(sc); 1845 1846 ale_rxvlan(sc); 1847 1848 /* Acknowledge all pending interrupts and clear it. */ 1849 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1850 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1851 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1852 1853 sc->ale_flags &= ~ALE_FLAG_LINK; 1854 1855 /* Switch to the current media. */ 1856 mii = &sc->sc_miibus; 1857 mii_mediachg(mii); 1858 1859 timeout_add_sec(&sc->ale_tick_ch, 1); 1860 1861 ifp->if_flags |= IFF_RUNNING; 1862 ifp->if_flags &= ~IFF_OACTIVE; 1863 1864 return 0; 1865 } 1866 1867 void 1868 ale_stop(struct ale_softc *sc) 1869 { 1870 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1871 struct ale_txdesc *txd; 1872 uint32_t reg; 1873 int i; 1874 1875 /* 1876 * Mark the interface down and cancel the watchdog timer. 1877 */ 1878 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1879 ifp->if_timer = 0; 1880 1881 timeout_del(&sc->ale_tick_ch); 1882 sc->ale_flags &= ~ALE_FLAG_LINK; 1883 1884 ale_stats_update(sc); 1885 1886 /* Disable interrupts. */ 1887 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1888 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1889 1890 /* Disable queue processing and DMA. */ 1891 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1892 reg &= ~TXQ_CFG_ENB; 1893 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1894 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1895 reg &= ~RXQ_CFG_ENB; 1896 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1897 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1898 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1899 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1900 DELAY(1000); 1901 1902 /* Stop Rx/Tx MACs. */ 1903 ale_stop_mac(sc); 1904 1905 /* Disable interrupts again? XXX */ 1906 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1907 1908 /* 1909 * Free TX mbufs still in the queues. 1910 */ 1911 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1912 txd = &sc->ale_cdata.ale_txdesc[i]; 1913 if (txd->tx_m != NULL) { 1914 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 1915 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1916 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1917 m_freem(txd->tx_m); 1918 txd->tx_m = NULL; 1919 } 1920 } 1921 } 1922 1923 void 1924 ale_stop_mac(struct ale_softc *sc) 1925 { 1926 uint32_t reg; 1927 int i; 1928 1929 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1930 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1931 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1932 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1933 } 1934 1935 for (i = ALE_TIMEOUT; i > 0; i--) { 1936 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1937 if (reg == 0) 1938 break; 1939 DELAY(10); 1940 } 1941 if (i == 0) 1942 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1943 sc->sc_dev.dv_xname, reg); 1944 } 1945 1946 void 1947 ale_init_tx_ring(struct ale_softc *sc) 1948 { 1949 struct ale_txdesc *txd; 1950 int i; 1951 1952 sc->ale_cdata.ale_tx_prod = 0; 1953 sc->ale_cdata.ale_tx_cons = 0; 1954 sc->ale_cdata.ale_tx_cnt = 0; 1955 1956 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 1957 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 1958 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1959 txd = &sc->ale_cdata.ale_txdesc[i]; 1960 txd->tx_m = NULL; 1961 } 1962 *sc->ale_cdata.ale_tx_cmb = 0; 1963 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1964 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1965 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1966 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1967 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, 1968 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1969 } 1970 1971 void 1972 ale_init_rx_pages(struct ale_softc *sc) 1973 { 1974 struct ale_rx_page *rx_page; 1975 int i; 1976 1977 sc->ale_cdata.ale_rx_seqno = 0; 1978 sc->ale_cdata.ale_rx_curp = 0; 1979 1980 for (i = 0; i < ALE_RX_PAGES; i++) { 1981 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1982 bzero(rx_page->page_addr, sc->ale_pagesize); 1983 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 1984 rx_page->cons = 0; 1985 *rx_page->cmb_addr = 0; 1986 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1987 rx_page->page_map->dm_mapsize, 1988 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1989 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1990 rx_page->cmb_map->dm_mapsize, 1991 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1992 } 1993 } 1994 1995 void 1996 ale_rxvlan(struct ale_softc *sc) 1997 { 1998 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1999 uint32_t reg; 2000 2001 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2002 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2003 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 2004 reg |= MAC_CFG_VLAN_TAG_STRIP; 2005 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2006 } 2007 2008 void 2009 ale_iff(struct ale_softc *sc) 2010 { 2011 struct arpcom *ac = &sc->sc_arpcom; 2012 struct ifnet *ifp = &ac->ac_if; 2013 struct ether_multi *enm; 2014 struct ether_multistep step; 2015 uint32_t crc; 2016 uint32_t mchash[2]; 2017 uint32_t rxcfg; 2018 2019 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 2020 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2021 ifp->if_flags &= ~IFF_ALLMULTI; 2022 2023 /* 2024 * Always accept broadcast frames. 2025 */ 2026 rxcfg |= MAC_CFG_BCAST; 2027 2028 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 2029 ifp->if_flags |= IFF_ALLMULTI; 2030 if (ifp->if_flags & IFF_PROMISC) 2031 rxcfg |= MAC_CFG_PROMISC; 2032 else 2033 rxcfg |= MAC_CFG_ALLMULTI; 2034 mchash[0] = mchash[1] = 0xFFFFFFFF; 2035 } else { 2036 /* Program new filter. */ 2037 bzero(mchash, sizeof(mchash)); 2038 2039 ETHER_FIRST_MULTI(step, ac, enm); 2040 while (enm != NULL) { 2041 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2042 2043 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2044 2045 ETHER_NEXT_MULTI(step, enm); 2046 } 2047 } 2048 2049 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2050 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2051 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2052 } 2053